From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 30/46] hw/arm: ast2400/ast2500: Wire up EHCI controllers
Date: Thu, 13 Feb 2020 14:41:29 +0000 [thread overview]
Message-ID: <20200213144145.818-31-peter.maydell@linaro.org> (raw)
In-Reply-To: <20200213144145.818-1-peter.maydell@linaro.org>
From: Guenter Roeck <linux@roeck-us.net>
Initialize EHCI controllers on AST2400 and AST2500 using the existing
TYPE_PLATFORM_EHCI. After this change, booting ast2500-evb into Linux
successfully instantiates a USB interface.
ehci-platform 1e6a3000.usb: EHCI Host Controller
ehci-platform 1e6a3000.usb: new USB bus registered, assigned bus number 1
ehci-platform 1e6a3000.usb: irq 21, io mem 0x1e6a3000
ehci-platform 1e6a3000.usb: USB 2.0 started, EHCI 1.00
usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 5.05
usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
usb usb1: Product: EHCI Host Controller
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200206183437.3979-1-linux@roeck-us.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/aspeed_soc.h | 6 ++++++
hw/arm/aspeed_soc.c | 25 +++++++++++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 90ac7f7ffa3..78b9f6ae532 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -26,8 +26,10 @@
#include "target/arm/cpu.h"
#include "hw/gpio/aspeed_gpio.h"
#include "hw/sd/aspeed_sdhci.h"
+#include "hw/usb/hcd-ehci.h"
#define ASPEED_SPIS_NUM 2
+#define ASPEED_EHCIS_NUM 2
#define ASPEED_WDTS_NUM 4
#define ASPEED_CPUS_NUM 2
#define ASPEED_MACS_NUM 4
@@ -50,6 +52,7 @@ typedef struct AspeedSoCState {
AspeedXDMAState xdma;
AspeedSMCState fmc;
AspeedSMCState spi[ASPEED_SPIS_NUM];
+ EHCISysBusState ehci[ASPEED_EHCIS_NUM];
AspeedSDMCState sdmc;
AspeedWDTState wdt[ASPEED_WDTS_NUM];
FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
@@ -71,6 +74,7 @@ typedef struct AspeedSoCClass {
uint32_t silicon_rev;
uint64_t sram_size;
int spis_num;
+ int ehcis_num;
int wdts_num;
int macs_num;
const int *irqmap;
@@ -94,6 +98,8 @@ enum {
ASPEED_FMC,
ASPEED_SPI1,
ASPEED_SPI2,
+ ASPEED_EHCI1,
+ ASPEED_EHCI2,
ASPEED_VIC,
ASPEED_SDMC,
ASPEED_SCU,
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index b5e809a1d3f..696c7fda14b 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -30,6 +30,7 @@ static const hwaddr aspeed_soc_ast2400_memmap[] = {
[ASPEED_IOMEM] = 0x1E600000,
[ASPEED_FMC] = 0x1E620000,
[ASPEED_SPI1] = 0x1E630000,
+ [ASPEED_EHCI1] = 0x1E6A1000,
[ASPEED_VIC] = 0x1E6C0000,
[ASPEED_SDMC] = 0x1E6E0000,
[ASPEED_SCU] = 0x1E6E2000,
@@ -59,6 +60,8 @@ static const hwaddr aspeed_soc_ast2500_memmap[] = {
[ASPEED_FMC] = 0x1E620000,
[ASPEED_SPI1] = 0x1E630000,
[ASPEED_SPI2] = 0x1E631000,
+ [ASPEED_EHCI1] = 0x1E6A1000,
+ [ASPEED_EHCI2] = 0x1E6A3000,
[ASPEED_VIC] = 0x1E6C0000,
[ASPEED_SDMC] = 0x1E6E0000,
[ASPEED_SCU] = 0x1E6E2000,
@@ -91,6 +94,8 @@ static const int aspeed_soc_ast2400_irqmap[] = {
[ASPEED_UART5] = 10,
[ASPEED_VUART] = 8,
[ASPEED_FMC] = 19,
+ [ASPEED_EHCI1] = 5,
+ [ASPEED_EHCI2] = 13,
[ASPEED_SDMC] = 0,
[ASPEED_SCU] = 21,
[ASPEED_ADC] = 31,
@@ -180,6 +185,11 @@ static void aspeed_soc_init(Object *obj)
sizeof(s->spi[i]), typename);
}
+ for (i = 0; i < sc->ehcis_num; i++) {
+ sysbus_init_child_obj(obj, "ehci[*]", OBJECT(&s->ehci[i]),
+ sizeof(s->ehci[i]), TYPE_PLATFORM_EHCI);
+ }
+
snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc),
typename);
@@ -364,6 +374,19 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
s->spi[i].ctrl->flash_window_base);
}
+ /* EHCI */
+ for (i = 0; i < sc->ehcis_num; i++) {
+ object_property_set_bool(OBJECT(&s->ehci[i]), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
+ sc->memmap[ASPEED_EHCI1 + i]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
+ aspeed_soc_get_irq(s, ASPEED_EHCI1 + i));
+ }
+
/* SDMC - SDRAM Memory Controller */
object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
if (err) {
@@ -472,6 +495,7 @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
sc->silicon_rev = AST2400_A1_SILICON_REV;
sc->sram_size = 0x8000;
sc->spis_num = 1;
+ sc->ehcis_num = 1;
sc->wdts_num = 2;
sc->macs_num = 2;
sc->irqmap = aspeed_soc_ast2400_irqmap;
@@ -496,6 +520,7 @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
sc->silicon_rev = AST2500_A1_SILICON_REV;
sc->sram_size = 0x9000;
sc->spis_num = 2;
+ sc->ehcis_num = 2;
sc->wdts_num = 3;
sc->macs_num = 2;
sc->irqmap = aspeed_soc_ast2500_irqmap;
--
2.20.1
next prev parent reply other threads:[~2020-02-13 15:14 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-13 14:40 [PULL 00/46] target-arm queue Peter Maydell
2020-02-13 14:41 ` [PULL 01/46] i.MX: Fix inverted register bits in wdt code Peter Maydell
2020-02-13 14:41 ` [PULL 02/46] i.MX: Add support for WDT on i.MX6 Peter Maydell
2020-02-13 14:41 ` [PULL 03/46] bios-tables-test: prepare to change ARM virt ACPI DSDT Peter Maydell
2020-02-13 14:41 ` [PULL 04/46] arm/virt/acpi: remove meaningless sub device "RP0" from PCI0 Peter Maydell
2020-02-13 14:41 ` [PULL 05/46] arm/virt/acpi: remove _ADR from devices identified by _HID Peter Maydell
2020-02-13 14:41 ` [PULL 06/46] arm/acpi: fix PCI _PRT definition Peter Maydell
2020-02-13 14:41 ` [PULL 07/46] arm/acpi: fix duplicated _UID of PCI interrupt link devices Peter Maydell
2020-02-13 14:41 ` [PULL 08/46] arm/acpi: simplify the description of PCI _CRS Peter Maydell
2020-02-13 14:41 ` [PULL 09/46] virt/acpi: update golden masters for DSDT update Peter Maydell
2020-02-13 14:41 ` [PULL 10/46] target/arm: Add arm_mmu_idx_is_stage1_of_2 Peter Maydell
2020-02-13 14:41 ` [PULL 11/46] target/arm: Add mmu_idx for EL1 and EL2 w/ PAN enabled Peter Maydell
2020-02-13 14:41 ` [PULL 12/46] target/arm: Add isar_feature tests for PAN + ATS1E1 Peter Maydell
2020-02-13 14:41 ` [PULL 13/46] target/arm: Move LOR regdefs to file scope Peter Maydell
2020-02-13 14:41 ` [PULL 14/46] target/arm: Split out aarch32_cpsr_valid_mask Peter Maydell
2020-02-13 14:41 ` [PULL 15/46] target/arm: Mask CPSR_J when Jazelle is not enabled Peter Maydell
2020-02-13 14:41 ` [PULL 16/46] target/arm: Replace CPSR_ERET_MASK with aarch32_cpsr_valid_mask Peter Maydell
2020-02-13 14:41 ` [PULL 17/46] target/arm: Use aarch32_cpsr_valid_mask in helper_exception_return Peter Maydell
2020-02-13 14:41 ` [PULL 18/46] target/arm: Remove CPSR_RESERVED Peter Maydell
2020-02-13 14:41 ` [PULL 19/46] target/arm: Introduce aarch64_pstate_valid_mask Peter Maydell
2020-02-13 14:41 ` [PULL 20/46] target/arm: Update MSR access for PAN Peter Maydell
2020-02-13 14:41 ` [PULL 21/46] target/arm: Update arm_mmu_idx_el " Peter Maydell
2020-02-13 14:41 ` [PULL 22/46] target/arm: Enforce PAN semantics in get_S1prot Peter Maydell
2020-02-13 14:41 ` [PULL 23/46] target/arm: Set PAN bit as required on exception entry Peter Maydell
2020-02-13 14:41 ` [PULL 24/46] target/arm: Implement ATS1E1 system registers Peter Maydell
2020-02-13 14:41 ` [PULL 25/46] target/arm: Enable ARMv8.2-ATS1E1 in -cpu max Peter Maydell
2020-02-13 14:41 ` [PULL 26/46] target/arm: Add ID_AA64MMFR2_EL1 Peter Maydell
2020-02-13 14:41 ` [PULL 27/46] target/arm: Update MSR access to UAO Peter Maydell
2020-02-13 14:41 ` [PULL 28/46] target/arm: Implement UAO semantics Peter Maydell
2020-02-13 14:41 ` [PULL 29/46] target/arm: Enable ARMv8.2-UAO in -cpu max Peter Maydell
2020-02-13 14:41 ` Peter Maydell [this message]
2020-02-13 14:41 ` [PULL 31/46] hw/arm: ast2600: Wire up EHCI controllers Peter Maydell
2020-02-13 14:41 ` [PULL 32/46] hw/char/exynos4210_uart: Fix memleaks in exynos4210_uart_init Peter Maydell
2020-02-13 14:41 ` [PULL 33/46] hw/arm/raspi: Use BCM2708 machine type with pre Device Tree kernels Peter Maydell
2020-02-13 14:41 ` [PULL 34/46] hw/arm/raspi: Correct the board descriptions Peter Maydell
2020-02-13 14:41 ` [PULL 35/46] hw/arm/raspi: Extract the version from the board revision Peter Maydell
2020-02-13 14:41 ` [PULL 36/46] hw/arm/raspi: Extract the RAM size " Peter Maydell
2020-02-13 14:41 ` [PULL 37/46] hw/arm/raspi: Extract the processor type " Peter Maydell
2020-02-13 14:41 ` [PULL 38/46] hw/arm/raspi: Trivial code movement Peter Maydell
2020-02-13 14:41 ` [PULL 39/46] hw/arm/raspi: Make machines children of abstract RaspiMachineClass Peter Maydell
2020-02-13 14:41 ` [PULL 40/46] hw/arm/raspi: Make board_rev a field of RaspiMachineClass Peter Maydell
2020-02-13 14:41 ` [PULL 41/46] hw/arm/raspi: Let class_init() directly call raspi_machine_init() Peter Maydell
2020-02-13 14:41 ` [PULL 42/46] hw/arm/raspi: Set default RAM size to size encoded in board revision Peter Maydell
2020-02-13 14:41 ` [PULL 43/46] hw/arm/raspi: Extract the board model from the " Peter Maydell
2020-02-13 14:41 ` [PULL 44/46] hw/arm/raspi: Use a unique raspi_machine_class_init() method Peter Maydell
2020-02-13 14:41 ` [PULL 45/46] hw/arm/raspi: Extract the cores count from the board revision Peter Maydell
2020-02-13 14:41 ` [PULL 46/46] target/arm: Implement ARMv8.1-VMID16 extension Peter Maydell
2020-02-14 16:43 ` [PULL 00/46] target-arm queue Peter Maydell
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