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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 05/46] arm/virt/acpi: remove _ADR from devices identified by _HID
Date: Thu, 13 Feb 2020 14:41:04 +0000	[thread overview]
Message-ID: <20200213144145.818-6-peter.maydell@linaro.org> (raw)
In-Reply-To: <20200213144145.818-1-peter.maydell@linaro.org>

From: Heyi Guo <guoheyi@huawei.com>

According to ACPI spec, _ADR should be used for device on a bus that
has a standard enumeration algorithm, but not for device which is on
system bus and must be enumerated by OSPM. And it is not recommended
to contain both _HID and _ADR in a single device.

See ACPI 6.3, section 6.1, top of page 343:

A device object must contain either an _HID object or an _ADR object,
but should not contain both.

(https://uefi.org/sites/default/files/resources/ACPI_6_3_May16.pdf)

Signed-off-by: Heyi Guo <guoheyi@huawei.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-id: 20200204014325.16279-4-guoheyi@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt-acpi-build.c | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 9f4c7d1889c..be752c0ad8e 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -78,11 +78,6 @@ static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
                              AML_EXCLUSIVE, &uart_irq, 1));
     aml_append(dev, aml_name_decl("_CRS", crs));
 
-    /* The _ADR entry is used to link this device to the UART described
-     * in the SPCR table, i.e. SPCR.base_address.address == _ADR.
-     */
-    aml_append(dev, aml_name_decl("_ADR", aml_int(uart_memmap->base)));
-
     aml_append(scope, dev);
 }
 
@@ -170,7 +165,6 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
     aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
     aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
     aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
-    aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
     aml_append(dev, aml_name_decl("_UID", aml_string("PCI0")));
     aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device")));
     aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
@@ -334,7 +328,6 @@ static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap,
 {
     Aml *dev = aml_device("GPO0");
     aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061")));
-    aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
     aml_append(dev, aml_name_decl("_UID", aml_int(0)));
 
     Aml *crs = aml_resource_template();
@@ -364,7 +357,6 @@ static void acpi_dsdt_add_power_button(Aml *scope)
 {
     Aml *dev = aml_device(ACPI_POWER_BUTTON_DEVICE);
     aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C0C")));
-    aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
     aml_append(dev, aml_name_decl("_UID", aml_int(0)));
     aml_append(scope, dev);
 }
-- 
2.20.1



  parent reply	other threads:[~2020-02-13 14:55 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-13 14:40 [PULL 00/46] target-arm queue Peter Maydell
2020-02-13 14:41 ` [PULL 01/46] i.MX: Fix inverted register bits in wdt code Peter Maydell
2020-02-13 14:41 ` [PULL 02/46] i.MX: Add support for WDT on i.MX6 Peter Maydell
2020-02-13 14:41 ` [PULL 03/46] bios-tables-test: prepare to change ARM virt ACPI DSDT Peter Maydell
2020-02-13 14:41 ` [PULL 04/46] arm/virt/acpi: remove meaningless sub device "RP0" from PCI0 Peter Maydell
2020-02-13 14:41 ` Peter Maydell [this message]
2020-02-13 14:41 ` [PULL 06/46] arm/acpi: fix PCI _PRT definition Peter Maydell
2020-02-13 14:41 ` [PULL 07/46] arm/acpi: fix duplicated _UID of PCI interrupt link devices Peter Maydell
2020-02-13 14:41 ` [PULL 08/46] arm/acpi: simplify the description of PCI _CRS Peter Maydell
2020-02-13 14:41 ` [PULL 09/46] virt/acpi: update golden masters for DSDT update Peter Maydell
2020-02-13 14:41 ` [PULL 10/46] target/arm: Add arm_mmu_idx_is_stage1_of_2 Peter Maydell
2020-02-13 14:41 ` [PULL 11/46] target/arm: Add mmu_idx for EL1 and EL2 w/ PAN enabled Peter Maydell
2020-02-13 14:41 ` [PULL 12/46] target/arm: Add isar_feature tests for PAN + ATS1E1 Peter Maydell
2020-02-13 14:41 ` [PULL 13/46] target/arm: Move LOR regdefs to file scope Peter Maydell
2020-02-13 14:41 ` [PULL 14/46] target/arm: Split out aarch32_cpsr_valid_mask Peter Maydell
2020-02-13 14:41 ` [PULL 15/46] target/arm: Mask CPSR_J when Jazelle is not enabled Peter Maydell
2020-02-13 14:41 ` [PULL 16/46] target/arm: Replace CPSR_ERET_MASK with aarch32_cpsr_valid_mask Peter Maydell
2020-02-13 14:41 ` [PULL 17/46] target/arm: Use aarch32_cpsr_valid_mask in helper_exception_return Peter Maydell
2020-02-13 14:41 ` [PULL 18/46] target/arm: Remove CPSR_RESERVED Peter Maydell
2020-02-13 14:41 ` [PULL 19/46] target/arm: Introduce aarch64_pstate_valid_mask Peter Maydell
2020-02-13 14:41 ` [PULL 20/46] target/arm: Update MSR access for PAN Peter Maydell
2020-02-13 14:41 ` [PULL 21/46] target/arm: Update arm_mmu_idx_el " Peter Maydell
2020-02-13 14:41 ` [PULL 22/46] target/arm: Enforce PAN semantics in get_S1prot Peter Maydell
2020-02-13 14:41 ` [PULL 23/46] target/arm: Set PAN bit as required on exception entry Peter Maydell
2020-02-13 14:41 ` [PULL 24/46] target/arm: Implement ATS1E1 system registers Peter Maydell
2020-02-13 14:41 ` [PULL 25/46] target/arm: Enable ARMv8.2-ATS1E1 in -cpu max Peter Maydell
2020-02-13 14:41 ` [PULL 26/46] target/arm: Add ID_AA64MMFR2_EL1 Peter Maydell
2020-02-13 14:41 ` [PULL 27/46] target/arm: Update MSR access to UAO Peter Maydell
2020-02-13 14:41 ` [PULL 28/46] target/arm: Implement UAO semantics Peter Maydell
2020-02-13 14:41 ` [PULL 29/46] target/arm: Enable ARMv8.2-UAO in -cpu max Peter Maydell
2020-02-13 14:41 ` [PULL 30/46] hw/arm: ast2400/ast2500: Wire up EHCI controllers Peter Maydell
2020-02-13 14:41 ` [PULL 31/46] hw/arm: ast2600: " Peter Maydell
2020-02-13 14:41 ` [PULL 32/46] hw/char/exynos4210_uart: Fix memleaks in exynos4210_uart_init Peter Maydell
2020-02-13 14:41 ` [PULL 33/46] hw/arm/raspi: Use BCM2708 machine type with pre Device Tree kernels Peter Maydell
2020-02-13 14:41 ` [PULL 34/46] hw/arm/raspi: Correct the board descriptions Peter Maydell
2020-02-13 14:41 ` [PULL 35/46] hw/arm/raspi: Extract the version from the board revision Peter Maydell
2020-02-13 14:41 ` [PULL 36/46] hw/arm/raspi: Extract the RAM size " Peter Maydell
2020-02-13 14:41 ` [PULL 37/46] hw/arm/raspi: Extract the processor type " Peter Maydell
2020-02-13 14:41 ` [PULL 38/46] hw/arm/raspi: Trivial code movement Peter Maydell
2020-02-13 14:41 ` [PULL 39/46] hw/arm/raspi: Make machines children of abstract RaspiMachineClass Peter Maydell
2020-02-13 14:41 ` [PULL 40/46] hw/arm/raspi: Make board_rev a field of RaspiMachineClass Peter Maydell
2020-02-13 14:41 ` [PULL 41/46] hw/arm/raspi: Let class_init() directly call raspi_machine_init() Peter Maydell
2020-02-13 14:41 ` [PULL 42/46] hw/arm/raspi: Set default RAM size to size encoded in board revision Peter Maydell
2020-02-13 14:41 ` [PULL 43/46] hw/arm/raspi: Extract the board model from the " Peter Maydell
2020-02-13 14:41 ` [PULL 44/46] hw/arm/raspi: Use a unique raspi_machine_class_init() method Peter Maydell
2020-02-13 14:41 ` [PULL 45/46] hw/arm/raspi: Extract the cores count from the board revision Peter Maydell
2020-02-13 14:41 ` [PULL 46/46] target/arm: Implement ARMv8.1-VMID16 extension Peter Maydell
2020-02-14 16:43 ` [PULL 00/46] target-arm queue Peter Maydell

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