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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id v8sm8001857wrw.2.2020.02.14.09.51.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 09:51:18 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 00/21] arm: ARMv8.1- and v8.4-PMU, ID reg cleanup, [H]ACTLR2 Date: Fri, 14 Feb 2020 17:50:55 +0000 Message-Id: <20200214175116.9164-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32f X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This patchset implements the ARMv8.1-PMU and ARMv8.4-PMU architecture extensions. These are fairly small changes on top of the basic PMUv3 we already implement, and in fact we already had most of the v8.1-PMU functionality implemented but unadvertised. In the course of doing this, I found that our naming and use of isar_feature ID register test functions was slightly inconsistent, so the first few patches straighten this out and align on an _aa32_/_aa64_/_any_ convention for which ID registers to test. The ARMv8.1-PMU extension requires: * the evtCount field in PMETYPER_EL0 is 16 bits, not 10 * MDCR_EL2.HPMD allows event counting to be disabled at EL2 * two new required events, STALL_FRONTEND and STALL_BACKEND * ID register bits in ID_AA64DFR0_EL1 and ID_DFR0 We already implement all of that except the new events; for QEMU our CPU never "stalls" in that sense, so we can just implement them as always-reads-zero. The ARMv8.4-PMU extension adds: * one new required event, STALL (again, reads-as-zero) * one new system register PMMIR_EL1, which provides information about the PMU implementation. Since the only currently defined field in it relates to an event we don't provide, we can validly implement the register as RAZ. Two patches fix some bugs I discovered while running this through Eric's recent kvm-unit-tests PMU tests: * we had the wrong definition of the PMCR.DP bit position * we incorrectly implemented PMCR.LC as RAZ/WI I also fix some random minor bugs I noticed while cleaning up the ID register handling. Finally there's an implementation of ACTLR2 and HACTLR2 sysregs; these are pretty trivial but required from Armv8.2 onward. This is strictly speaking unrelated to perf, but the patch depends on all the preceding cleanup stuff. I don't generally use the perf emulation, so testing would be welcome from people who do. Changes v1->v2: * now rebased on master, so patch 1 fixes up an extra new use of isar_feature_jazelle * patch 2 is new: take_aarch32_exception should check aa32_pan, not aa64_pan * minor fixups per review comments (mostly using 64-bit versions of extract/deposit where appropriate) * added code to get values of ID registers from KVM * when I added that code I ran into a bunch of problems which stemmed from our using the 32-bit DBGDIDR as the source of truth about numbers of breakpoints etc, which then breaks if the host KVM CPU is AArch64-only, so some patches clean that up * patch 18 fixes a cut-n-paste error I noticed where we were reading entirely the wrong register in aa32_pan and aa32_ats1e1 * patch 19 adds an isar_feature test to replace an opencoded examination of an ID register field * patch 20 uses FIELD_EX32 for 32-bit ID registers rather than FIELD_EX64 * patch 21 implements ACTLR2 and HACTLR2 Patches 1, 3-9, and 13-17 have already been reviewed; 2, 10-12, and 18-21 are new in v2. thanks -- PMM Peter Maydell (21): target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers target/arm: Check aa32_pan in take_aarch32_exception(), not aa64_pan target/arm: Add isar_feature_any_fp16 and document naming/usage conventions target/arm: Define and use any_predinv isar_feature test target/arm: Factor out PMU register definitions target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1 target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field target/arm: Define an aa32_pmu_8_1 isar feature test function target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks target/arm: Stop assuming DBGDIDR always exists target/arm: Move DBGDIDR into ARMISARegisters target/arm: Read debug-related ID registers from KVM target/arm: Implement ARMv8.1-PMU extension target/arm: Implement ARMv8.4-PMU extension target/arm: Provide ARMv8.4-PMU in '-cpu max' target/arm: Correct definition of PMCRDP target/arm: Correct handling of PMCR_EL0.LC bit target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks target/arm: Use isar_feature function for testing AA32HPD feature target/arm: Use FIELD_EX32 for testing 32-bit fields target/arm: Correctly implement ACTLR2, HACTLR2 target/arm/cpu.h | 143 +++++++++++++++--- target/arm/internals.h | 44 +++++- hw/intc/armv7m_nvic.c | 10 +- linux-user/elfload.c | 4 +- target/arm/cpu.c | 150 +++++++++--------- target/arm/cpu64.c | 58 ++++--- target/arm/debug_helper.c | 6 +- target/arm/helper.c | 311 ++++++++++++++++++++++---------------- target/arm/kvm32.c | 25 +++ target/arm/kvm64.c | 46 ++++++ target/arm/translate.c | 6 +- target/arm/vfp_helper.c | 2 +- 12 files changed, 544 insertions(+), 261 deletions(-) -- 2.20.1