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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id v8sm8001857wrw.2.2020.02.14.09.51.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2020 09:51:37 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 13/21] target/arm: Implement ARMv8.1-PMU extension Date: Fri, 14 Feb 2020 17:51:08 +0000 Message-Id: <20200214175116.9164-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200214175116.9164-1-peter.maydell@linaro.org> References: <20200214175116.9164-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Aaron Lindsay , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The ARMv8.1-PMU extension requires: * the evtCount field in PMETYPER_EL0 is 16 bits, not 10 * MDCR_EL2.HPMD allows event counting to be disabled at EL2 * two new required events, STALL_FRONTEND and STALL_BACKEND * ID register bits in ID_AA64DFR0_EL1 and ID_DFR0 We already implement the 16-bit evtCount field and the HPMD bit, so all that is missing is the two new events: STALL_FRONTEND "counts every cycle counted by the CPU_CYCLES event on which no operation was issued because there are no operations available to issue to this PE from the frontend" STALL_BACKEND "counts every cycle counted by the CPU_CYCLES event on which no operation was issued because the backend is unable to accept any available operations from the frontend" QEMU never stalls in this sense, so our implementation is trivial: always return a zero count. Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- target/arm/helper.c | 32 ++++++++++++++++++++++++++++++-- 1 file changed, 30 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 1dcbb68e49b..aeb01617150 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1124,6 +1124,24 @@ static int64_t instructions_ns_per(uint64_t icount) } #endif +static bool pmu_8_1_events_supported(CPUARMState *env) +{ + /* For events which are supported in any v8.1 PMU */ + return cpu_isar_feature(any_pmu_8_1, env_archcpu(env)); +} + +static uint64_t zero_event_get_count(CPUARMState *env) +{ + /* For events which on QEMU never fire, so their count is always zero */ + return 0; +} + +static int64_t zero_event_ns_per(uint64_t cycles) +{ + /* An event which never fires can never overflow */ + return -1; +} + static const pm_event pm_events[] = { { .number = 0x000, /* SW_INCR */ .supported = event_always_supported, @@ -1140,8 +1158,18 @@ static const pm_event pm_events[] = { .supported = event_always_supported, .get_count = cycles_get_count, .ns_per_count = cycles_ns_per, - } + }, #endif + { .number = 0x023, /* STALL_FRONTEND */ + .supported = pmu_8_1_events_supported, + .get_count = zero_event_get_count, + .ns_per_count = zero_event_ns_per, + }, + { .number = 0x024, /* STALL_BACKEND */ + .supported = pmu_8_1_events_supported, + .get_count = zero_event_get_count, + .ns_per_count = zero_event_ns_per, + }, }; /* @@ -1150,7 +1178,7 @@ static const pm_event pm_events[] = { * should first be updated to something sparse instead of the current * supported_event_map[] array. */ -#define MAX_EVENT_ID 0x11 +#define MAX_EVENT_ID 0x24 #define UNSUPPORTED_EVENT UINT16_MAX static uint16_t supported_event_map[MAX_EVENT_ID + 1]; -- 2.20.1