QEMU-Devel Archive on lore.kernel.org
 help / color / Atom feed
From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: "Eric Auger" <eric.auger@redhat.com>,
	"Aaron Lindsay" <aaron@os.amperecomputing.com>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Philippe Mathieu-Daudé" <philmd@redhat.com>
Subject: [PATCH v2 19/21] target/arm: Use isar_feature function for testing AA32HPD feature
Date: Fri, 14 Feb 2020 17:51:14 +0000
Message-ID: <20200214175116.9164-20-peter.maydell@linaro.org> (raw)
In-Reply-To: <20200214175116.9164-1-peter.maydell@linaro.org>

Now we have moved ID_MMFR4 into the ARMISARegisters struct, we
can define and use an isar_feature for the presence of the
ARMv8.2-AA32HPD feature, rather than open-coding the test.

While we're here, correct a comment typo which missed an 'A'
from the feature name.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h    | 5 +++++
 target/arm/helper.c | 4 ++--
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index ba97fc75c1d..276030a5cf3 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3526,6 +3526,11 @@ static inline bool isar_feature_aa32_pmu_8_4(const ARMISARegisters *id)
         FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
 }
 
+static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id)
+{
+    return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0;
+}
+
 /*
  * 64-bit feature tests via id registers.
  */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 492741a2b0b..56b1c08f027 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7408,8 +7408,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
     } else {
         define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
         define_arm_cp_regs(cpu, vmsa_cp_reginfo);
-        /* TTCBR2 is introduced with ARMv8.2-A32HPD.  */
-        if (FIELD_EX32(cpu->isar.id_mmfr4, ID_MMFR4, HPDS) != 0) {
+        /* TTCBR2 is introduced with ARMv8.2-AA32HPD.  */
+        if (cpu_isar_feature(aa32_hpd, cpu)) {
             define_one_arm_cp_reg(cpu, &ttbcr2_reginfo);
         }
     }
-- 
2.20.1



  parent reply index

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-14 17:50 [PATCH v2 00/21] arm: ARMv8.1- and v8.4-PMU, ID reg cleanup, [H]ACTLR2 Peter Maydell
2020-02-14 17:50 ` [PATCH v2 01/21] target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers Peter Maydell
2020-02-14 17:50 ` [PATCH v2 02/21] target/arm: Check aa32_pan in take_aarch32_exception(), not aa64_pan Peter Maydell
2020-02-14 20:10   ` Richard Henderson
2020-02-14 17:50 ` [PATCH v2 03/21] target/arm: Add isar_feature_any_fp16 and document naming/usage conventions Peter Maydell
2020-02-14 17:50 ` [PATCH v2 04/21] target/arm: Define and use any_predinv isar_feature test Peter Maydell
2020-02-14 17:51 ` [PATCH v2 05/21] target/arm: Factor out PMU register definitions Peter Maydell
2020-02-14 17:51 ` [PATCH v2 06/21] target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1 Peter Maydell
2020-02-14 17:51 ` [PATCH v2 07/21] target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field Peter Maydell
2020-02-14 17:51 ` [PATCH v2 08/21] target/arm: Define an aa32_pmu_8_1 isar feature test function Peter Maydell
2020-02-14 17:51 ` [PATCH v2 09/21] target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks Peter Maydell
2020-02-14 17:51 ` [PATCH v2 10/21] target/arm: Stop assuming DBGDIDR always exists Peter Maydell
2020-02-14 20:15   ` Richard Henderson
2020-02-14 17:51 ` [PATCH v2 11/21] target/arm: Move DBGDIDR into ARMISARegisters Peter Maydell
2020-02-14 20:16   ` Richard Henderson
2020-02-14 17:51 ` [PATCH v2 12/21] target/arm: Read debug-related ID registers from KVM Peter Maydell
2020-02-14 20:27   ` Richard Henderson
2020-02-14 17:51 ` [PATCH v2 13/21] target/arm: Implement ARMv8.1-PMU extension Peter Maydell
2020-02-14 17:51 ` [PATCH v2 14/21] target/arm: Implement ARMv8.4-PMU extension Peter Maydell
2020-02-14 17:51 ` [PATCH v2 15/21] target/arm: Provide ARMv8.4-PMU in '-cpu max' Peter Maydell
2020-02-14 17:51 ` [PATCH v2 16/21] target/arm: Correct definition of PMCRDP Peter Maydell
2020-02-14 17:51 ` [PATCH v2 17/21] target/arm: Correct handling of PMCR_EL0.LC bit Peter Maydell
2020-02-14 17:51 ` [PATCH v2 18/21] target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks Peter Maydell
2020-02-14 20:30   ` Richard Henderson
2020-02-14 17:51 ` Peter Maydell [this message]
2020-02-14 20:32   ` [PATCH v2 19/21] target/arm: Use isar_feature function for testing AA32HPD feature Richard Henderson
2020-02-14 17:51 ` [PATCH v2 20/21] target/arm: Use FIELD_EX32 for testing 32-bit fields Peter Maydell
2020-02-14 20:32   ` Richard Henderson
2020-02-14 17:51 ` [PATCH v2 21/21] target/arm: Correctly implement ACTLR2, HACTLR2 Peter Maydell
2020-02-14 20:42   ` Richard Henderson

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20200214175116.9164-20-peter.maydell@linaro.org \
    --to=peter.maydell@linaro.org \
    --cc=aaron@os.amperecomputing.com \
    --cc=eric.auger@redhat.com \
    --cc=philmd@redhat.com \
    --cc=qemu-arm@nongnu.org \
    --cc=qemu-devel@nongnu.org \
    --cc=richard.henderson@linaro.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

QEMU-Devel Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/qemu-devel/0 qemu-devel/git/0.git
	git clone --mirror https://lore.kernel.org/qemu-devel/1 qemu-devel/git/1.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 qemu-devel qemu-devel/ https://lore.kernel.org/qemu-devel \
		qemu-devel@nongnu.org
	public-inbox-index qemu-devel

Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.nongnu.qemu-devel


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git