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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [PATCH 19/19] target/arm: Split VMINMAXNM decode
Date: Fri, 14 Feb 2020 10:15:47 -0800	[thread overview]
Message-ID: <20200214181547.21408-20-richard.henderson@linaro.org> (raw)
In-Reply-To: <20200214181547.21408-1-richard.henderson@linaro.org>

Passing the raw op field from the manual is less instructive
than it might be.  Do the full decode and use the existing
helpers to perform the expansion.

Since these are v8 insns, VECLEN+VECSTRIDE are already RES0.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/vfp-uncond.decode   |  12 ++--
 target/arm/translate-vfp.inc.c | 109 +++++++++++----------------------
 2 files changed, 44 insertions(+), 77 deletions(-)

diff --git a/target/arm/vfp-uncond.decode b/target/arm/vfp-uncond.decode
index 5af1f2ee66..34ca164266 100644
--- a/target/arm/vfp-uncond.decode
+++ b/target/arm/vfp-uncond.decode
@@ -41,15 +41,19 @@
 %vd_dp  22:1 12:4
 %vd_sp  12:4 22:1
 
+@vfp_dnm_s   ................................ vm=%vm_sp vn=%vn_sp vd=%vd_sp
+@vfp_dnm_d   ................................ vm=%vm_dp vn=%vn_dp vd=%vd_dp
+
 VSEL        1111 1110 0. cc:2 .... .... 1010 .0.0 .... \
             vm=%vm_sp vn=%vn_sp vd=%vd_sp dp=0
 VSEL        1111 1110 0. cc:2 .... .... 1011 .0.0 .... \
             vm=%vm_dp vn=%vn_dp vd=%vd_dp dp=1
 
-VMINMAXNM   1111 1110 1.00 .... .... 1010 . op:1 .0 .... \
-            vm=%vm_sp vn=%vn_sp vd=%vd_sp dp=0
-VMINMAXNM   1111 1110 1.00 .... .... 1011 . op:1 .0 .... \
-            vm=%vm_dp vn=%vn_dp vd=%vd_dp dp=1
+VMAXNM_sp   1111 1110 1.00 .... .... 1010 .0.0 ....         @vfp_dnm_s
+VMINNM_sp   1111 1110 1.00 .... .... 1010 .1.0 ....         @vfp_dnm_s
+
+VMAXNM_dp   1111 1110 1.00 .... .... 1011 .0.0 ....         @vfp_dnm_d
+VMINNM_dp   1111 1110 1.00 .... .... 1011 .1.0 ....         @vfp_dnm_d
 
 VRINT       1111 1110 1.11 10 rm:2 .... 1010 01.0 .... \
             vm=%vm_sp vd=%vd_sp dp=0
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index b5f3feaf8d..2cf85e73cf 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -322,79 +322,6 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
     return true;
 }
 
-static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a)
-{
-    uint32_t rd, rn, rm;
-    bool dp = a->dp;
-    bool vmin = a->op;
-    TCGv_ptr fpst;
-
-    if (!dc_isar_feature(aa32_vminmaxnm, s)) {
-        return false;
-    }
-
-    if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
-        return false;
-    }
-
-    /* UNDEF accesses to D16-D31 if they don't exist */
-    if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
-        ((a->vm | a->vn | a->vd) & 0x10)) {
-        return false;
-    }
-
-    rd = a->vd;
-    rn = a->vn;
-    rm = a->vm;
-
-    if (!vfp_access_check(s)) {
-        return true;
-    }
-
-    fpst = get_fpstatus_ptr(0);
-
-    if (dp) {
-        TCGv_i64 frn, frm, dest;
-
-        frn = tcg_temp_new_i64();
-        frm = tcg_temp_new_i64();
-        dest = tcg_temp_new_i64();
-
-        neon_load_reg64(frn, rn);
-        neon_load_reg64(frm, rm);
-        if (vmin) {
-            gen_helper_vfp_minnumd(dest, frn, frm, fpst);
-        } else {
-            gen_helper_vfp_maxnumd(dest, frn, frm, fpst);
-        }
-        neon_store_reg64(dest, rd);
-        tcg_temp_free_i64(frn);
-        tcg_temp_free_i64(frm);
-        tcg_temp_free_i64(dest);
-    } else {
-        TCGv_i32 frn, frm, dest;
-
-        frn = tcg_temp_new_i32();
-        frm = tcg_temp_new_i32();
-        dest = tcg_temp_new_i32();
-
-        neon_load_reg32(frn, rn);
-        neon_load_reg32(frm, rm);
-        if (vmin) {
-            gen_helper_vfp_minnums(dest, frn, frm, fpst);
-        } else {
-            gen_helper_vfp_maxnums(dest, frn, frm, fpst);
-        }
-        neon_store_reg32(dest, rd);
-        tcg_temp_free_i32(frn);
-        tcg_temp_free_i32(frm);
-        tcg_temp_free_i32(dest);
-    }
-
-    tcg_temp_free_ptr(fpst);
-    return true;
-}
-
 /*
  * Table for converting the most common AArch32 encoding of
  * rounding mode to arm_fprounding order (which matches the
@@ -1784,6 +1711,42 @@ static bool trans_VDIV_dp(DisasContext *s, arg_VDIV_dp *a)
     return do_vfp_3op_dp(s, gen_helper_vfp_divd, a->vd, a->vn, a->vm, false);
 }
 
+static bool trans_VMINNM_sp(DisasContext *s, arg_VMINNM_sp *a)
+{
+    if (!dc_isar_feature(aa32_vminmaxnm, s)) {
+        return false;
+    }
+    return do_vfp_3op_sp(s, gen_helper_vfp_minnums,
+                         a->vd, a->vn, a->vm, false);
+}
+
+static bool trans_VMAXNM_sp(DisasContext *s, arg_VMAXNM_sp *a)
+{
+    if (!dc_isar_feature(aa32_vminmaxnm, s)) {
+        return false;
+    }
+    return do_vfp_3op_sp(s, gen_helper_vfp_maxnums,
+                         a->vd, a->vn, a->vm, false);
+}
+
+static bool trans_VMINNM_dp(DisasContext *s, arg_VMINNM_dp *a)
+{
+    if (!dc_isar_feature(aa32_vminmaxnm, s)) {
+        return false;
+    }
+    return do_vfp_3op_dp(s, gen_helper_vfp_minnumd,
+                         a->vd, a->vn, a->vm, false);
+}
+
+static bool trans_VMAXNM_dp(DisasContext *s, arg_VMAXNM_dp *a)
+{
+    if (!dc_isar_feature(aa32_vminmaxnm, s)) {
+        return false;
+    }
+    return do_vfp_3op_dp(s, gen_helper_vfp_maxnumd,
+                         a->vd, a->vn, a->vm, false);
+}
+
 static bool do_vfm_sp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool neg_d)
 {
     /*
-- 
2.20.1



  parent reply	other threads:[~2020-02-14 18:27 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-14 18:15 [PATCH 00/19] target/arm: vfp feature and decodetree cleanup Richard Henderson
2020-02-14 18:15 ` [PATCH 01/19] target/arm: Fix field extract from MVFR[0-2] Richard Henderson
2020-02-14 18:29   ` Philippe Mathieu-Daudé
2020-02-14 18:35   ` Peter Maydell
2020-02-14 18:15 ` [PATCH 02/19] target/arm: Rename isar_feature_aa32_simd_r32 Richard Henderson
2020-02-14 18:50   ` Philippe Mathieu-Daudé
2020-02-21 15:58   ` Peter Maydell
2020-02-14 18:15 ` [PATCH 03/19] target/arm: Use isar_feature_aa32_simd_r32 more places Richard Henderson
2020-02-21 16:02   ` Peter Maydell
2020-02-14 18:15 ` [PATCH 04/19] target/arm: Set MVFR0.FPSP for ARMv5 cpus Richard Henderson
2020-02-21 16:02   ` Peter Maydell
2020-02-14 18:15 ` [PATCH 05/19] target/arm: Add isar_feature_aa32_simd_r16 Richard Henderson
2020-02-21 16:01   ` Peter Maydell
2020-02-14 18:15 ` [PATCH 06/19] target/arm: Rename isar_feature_aa32_fpdp_v2 Richard Henderson
2020-02-14 18:51   ` Philippe Mathieu-Daudé
2020-02-14 18:15 ` [PATCH 07/19] target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3} Richard Henderson
2020-02-21 16:03   ` Peter Maydell
2020-02-14 18:15 ` [PATCH 08/19] target/arm: Perform fpdp_v2 check first Richard Henderson
2020-02-21 16:04   ` Peter Maydell
2020-02-14 18:15 ` [PATCH 09/19] target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3 Richard Henderson
2020-02-21 16:05   ` Peter Maydell
2020-02-14 18:15 ` [PATCH 10/19] target/arm: Add missing checks for fpsp_v2 Richard Henderson
2020-02-21 16:05   ` Peter Maydell
2020-02-14 18:15 ` [PATCH 11/19] target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac Richard Henderson
2020-02-20 16:37   ` Peter Maydell
2020-02-20 16:41     ` Peter Maydell
2020-02-20 17:55     ` Richard Henderson
2020-02-14 18:15 ` [PATCH 12/19] target/arm: Remove ARM_FEATURE_VFP check from disas_vfp_insn Richard Henderson
2020-02-20 17:19   ` Peter Maydell
2020-02-14 18:15 ` [PATCH 13/19] target/arm: Move VLLDM and VLSTM to vfp.decode Richard Henderson
2020-02-20 17:02   ` Peter Maydell
2020-02-14 18:15 ` [PATCH 14/19] target/arm: Move the vfp decodetree calls next to the base isa Richard Henderson
2020-02-20 17:16   ` Peter Maydell
2020-02-14 18:15 ` [PATCH 15/19] linux-user/arm: Replace ARM_FEATURE_VFP* tests for HWCAP Richard Henderson
2020-02-20 17:32   ` Peter Maydell
2020-02-14 18:15 ` [PATCH 16/19] target/arm: Remove ARM_FEATURE_VFP* Richard Henderson
2020-02-20 17:33   ` Peter Maydell
2020-02-14 18:15 ` [PATCH 17/19] target/arm: Add formats for some vfp 2 and 3-register insns Richard Henderson
2020-02-20 17:40   ` Peter Maydell
2020-02-14 18:15 ` [PATCH 18/19] target/arm: Split VFM decode Richard Henderson
2020-02-20 17:45   ` Peter Maydell
2020-02-14 18:15 ` Richard Henderson [this message]
2020-02-20 17:49   ` [PATCH 19/19] target/arm: Split VMINMAXNM decode Peter Maydell
2020-02-14 20:11 ` [PATCH 00/19] target/arm: vfp feature and decodetree cleanup no-reply
2020-02-20 17:52 ` Peter Maydell

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