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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org
Subject: [PATCH 2/4] target/arm: Flush high bits of sve register after AdvSIMD TBL/TBX
Date: Fri, 14 Feb 2020 11:46:41 -0800
Message-ID: <20200214194643.23317-3-richard.henderson@linaro.org> (raw)
In-Reply-To: <20200214194643.23317-1-richard.henderson@linaro.org>

Writes to AdvSIMD registers flush the bits above 128.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 target/arm/translate-a64.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 620a429067..096a854aed 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -6964,6 +6964,7 @@ static void disas_simd_tb(DisasContext *s, uint32_t insn)
     write_vec_element(s, tcg_resh, rd, 1, MO_64);
+    clear_vec_high(s, true, rd);

  parent reply index

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-14 19:46 [PATCH 0/4] target/arm: fix some simd writes vs sve Richard Henderson
2020-02-14 19:46 ` [PATCH 1/4] target/arm: Flush high bits of sve register after AdvSIMD EXT Richard Henderson
2020-02-14 19:46 ` Richard Henderson [this message]
2020-02-14 19:46 ` [PATCH 3/4] target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN Richard Henderson
2020-02-14 19:46 ` [PATCH 4/4] target/arm: Flush high bits of sve register after AdvSIMD INS Richard Henderson
2020-02-18 17:28 ` [PATCH 0/4] target/arm: fix some simd writes vs sve Peter Maydell

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