* [PULL 01/33] hw/arm: Use TYPE_PL011 to create serial port
2020-02-28 16:38 [PULL 00/33] target-arm queue Peter Maydell
@ 2020-02-28 16:38 ` Peter Maydell
2020-02-28 16:38 ` [PULL 02/33] target/arm: Set ID_MMFR4.HPDS for aarch64_max_initfn Peter Maydell
` (32 subsequent siblings)
33 siblings, 0 replies; 57+ messages in thread
From: Peter Maydell @ 2020-02-28 16:38 UTC (permalink / raw)
To: qemu-devel
From: Gavin Shan <gshan@redhat.com>
This uses TYPE_PL011 when creating the serial port so that the code
looks cleaner.
Signed-off-by: Gavin Shan <gshan@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200224222223.4128-1-gshan@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/sbsa-ref.c | 3 ++-
hw/arm/virt.c | 3 ++-
hw/arm/xlnx-versal.c | 3 ++-
3 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 1cba9fc3021..8409ba853de 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -39,6 +39,7 @@
#include "hw/pci-host/gpex.h"
#include "hw/qdev-properties.h"
#include "hw/usb.h"
+#include "hw/char/pl011.h"
#include "net/net.h"
#define RAMLIMIT_GB 8192
@@ -409,7 +410,7 @@ static void create_uart(const SBSAMachineState *sms, int uart,
{
hwaddr base = sbsa_ref_memmap[uart].base;
int irq = sbsa_ref_irqmap[uart];
- DeviceState *dev = qdev_create(NULL, "pl011");
+ DeviceState *dev = qdev_create(NULL, TYPE_PL011);
SysBusDevice *s = SYS_BUS_DEVICE(dev);
qdev_prop_set_chr(dev, "chardev", chr);
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index a8191a3e75e..856808599d2 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -74,6 +74,7 @@
#include "hw/mem/nvdimm.h"
#include "hw/acpi/generic_event_device.h"
#include "hw/virtio/virtio-iommu.h"
+#include "hw/char/pl011.h"
#define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
@@ -727,7 +728,7 @@ static void create_uart(const VirtMachineState *vms, int uart,
int irq = vms->irqmap[uart];
const char compat[] = "arm,pl011\0arm,primecell";
const char clocknames[] = "uartclk\0apb_pclk";
- DeviceState *dev = qdev_create(NULL, "pl011");
+ DeviceState *dev = qdev_create(NULL, TYPE_PL011);
SysBusDevice *s = SYS_BUS_DEVICE(dev);
qdev_prop_set_chr(dev, "chardev", chr);
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index 1cf3daaf4f4..403fc7b8814 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -22,6 +22,7 @@
#include "hw/misc/unimp.h"
#include "hw/intc/arm_gicv3_common.h"
#include "hw/arm/xlnx-versal.h"
+#include "hw/char/pl011.h"
#define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")
#define GEM_REVISION 0x40070106
@@ -144,7 +145,7 @@ static void versal_create_uarts(Versal *s, qemu_irq *pic)
DeviceState *dev;
MemoryRegion *mr;
- dev = qdev_create(NULL, "pl011");
+ dev = qdev_create(NULL, TYPE_PL011);
s->lpd.iou.uart[i] = SYS_BUS_DEVICE(dev);
qdev_prop_set_chr(dev, "chardev", serial_hd(i));
object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal);
--
2.20.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 02/33] target/arm: Set ID_MMFR4.HPDS for aarch64_max_initfn
2020-02-28 16:38 [PULL 00/33] target-arm queue Peter Maydell
2020-02-28 16:38 ` [PULL 01/33] hw/arm: Use TYPE_PL011 to create serial port Peter Maydell
@ 2020-02-28 16:38 ` Peter Maydell
2020-02-28 16:38 ` [PULL 03/33] hw/arm/integratorcp: Map the audio codec controller Peter Maydell
` (31 subsequent siblings)
33 siblings, 0 replies; 57+ messages in thread
From: Peter Maydell @ 2020-02-28 16:38 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
We had set this for aarch32-only in arm_max_initfn, but
failed to set the same bit for aarch64.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200218190958.745-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu64.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 0929401a4dd..db695384ebc 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -704,6 +704,7 @@ static void aarch64_max_initfn(Object *obj)
cpu->isar.id_mmfr3 = u;
u = cpu->isar.id_mmfr4;
+ u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */
u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
cpu->isar.id_mmfr4 = u;
--
2.20.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 03/33] hw/arm/integratorcp: Map the audio codec controller
2020-02-28 16:38 [PULL 00/33] target-arm queue Peter Maydell
2020-02-28 16:38 ` [PULL 01/33] hw/arm: Use TYPE_PL011 to create serial port Peter Maydell
2020-02-28 16:38 ` [PULL 02/33] target/arm: Set ID_MMFR4.HPDS for aarch64_max_initfn Peter Maydell
@ 2020-02-28 16:38 ` Peter Maydell
2020-02-28 16:38 ` [PULL 04/33] arm_gic: Mask the un-supported priority bits Peter Maydell
` (30 subsequent siblings)
33 siblings, 0 replies; 57+ messages in thread
From: Peter Maydell @ 2020-02-28 16:38 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
The Linux kernel displays errors why trying to detect the PL041
audio interface:
Linux version 4.16.0 (linus@genomnajs) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #142 PREEMPT Wed May 9 13:24:55 CEST 2018
CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00093177
CPU: VIVT data cache, VIVT instruction cache
OF: fdt: Machine model: ARM Integrator/CP
...
OF: amba_device_add() failed (-19) for /fpga/aaci@1d000000
Since we have it already modelled, simply plug it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200223233033.15371-2-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/integratorcp.c | 1 +
hw/arm/Kconfig | 1 +
2 files changed, 2 insertions(+)
diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
index cc845b85340..6d69010d06b 100644
--- a/hw/arm/integratorcp.c
+++ b/hw/arm/integratorcp.c
@@ -642,6 +642,7 @@ static void integratorcp_init(MachineState *machine)
qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_WPROT, 0));
qdev_connect_gpio_out(dev, 1,
qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_CARDIN, 0));
+ sysbus_create_varargs("pl041", 0x1d000000, pic[25], NULL);
if (nd_table[0].used)
smc91c111_init(&nd_table[0], 0xc8000000, pic[27]);
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 3d86691ae0c..61635f52c42 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -69,6 +69,7 @@ config INTEGRATOR
select INTEGRATOR_DEBUG
select PL011 # UART
select PL031 # RTC
+ select PL041 # audio
select PL050 # keyboard/mouse
select PL110 # pl111 LCD controller
select PL181 # display
--
2.20.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 04/33] arm_gic: Mask the un-supported priority bits
2020-02-28 16:38 [PULL 00/33] target-arm queue Peter Maydell
` (2 preceding siblings ...)
2020-02-28 16:38 ` [PULL 03/33] hw/arm/integratorcp: Map the audio codec controller Peter Maydell
@ 2020-02-28 16:38 ` Peter Maydell
2020-02-28 16:38 ` [PULL 05/33] cpu/a9mpcore: Set number of GIC priority bits to 5 Peter Maydell
` (29 subsequent siblings)
33 siblings, 0 replies; 57+ messages in thread
From: Peter Maydell @ 2020-02-28 16:38 UTC (permalink / raw)
To: qemu-devel
From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
The GICv2 allows the implementation to implement a variable number
of priority bits; unimplemented bits in the priority registers
are read as zeros, writes ignored. We were previously always
implementing a full 8 bits of priority, which is allowed but not
what the real hardware typically does (which is usually to have
4 or 5 bits of priority).
Add a new device property to allow the number of implemented
property bits to be specified.
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Message-id: 1582537164-764-2-git-send-email-sai.pavan.boddu@xilinx.com
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: improved commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/intc/arm_gic.h | 2 ++
include/hw/intc/arm_gic_common.h | 1 +
hw/intc/arm_gic.c | 33 ++++++++++++++++++++++++++++++--
hw/intc/arm_gic_common.c | 1 +
4 files changed, 35 insertions(+), 2 deletions(-)
diff --git a/include/hw/intc/arm_gic.h b/include/hw/intc/arm_gic.h
index ed703a17203..303b9748cbb 100644
--- a/include/hw/intc/arm_gic.h
+++ b/include/hw/intc/arm_gic.h
@@ -68,6 +68,8 @@
/* Number of SGI target-list bits */
#define GIC_TARGETLIST_BITS 8
+#define GIC_MAX_PRIORITY_BITS 8
+#define GIC_MIN_PRIORITY_BITS 4
#define TYPE_ARM_GIC "arm_gic"
#define ARM_GIC(obj) \
diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h
index b5585fec451..6e0d6b8a889 100644
--- a/include/hw/intc/arm_gic_common.h
+++ b/include/hw/intc/arm_gic_common.h
@@ -96,6 +96,7 @@ typedef struct GICState {
uint16_t priority_mask[GIC_NCPU_VCPU];
uint16_t running_priority[GIC_NCPU_VCPU];
uint16_t current_pending[GIC_NCPU_VCPU];
+ uint32_t n_prio_bits;
/* If we present the GICv2 without security extensions to a guest,
* the guest can configure the GICC_CTLR to configure group 1 binary point
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 1d7da7baa20..c60dc6b5e6e 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -641,6 +641,23 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs)
return ret;
}
+static uint32_t gic_fullprio_mask(GICState *s, int cpu)
+{
+ /*
+ * Return a mask word which clears the unimplemented priority
+ * bits from a priority value for an interrupt. (Not to be
+ * confused with the group priority, whose mask depends on BPR.)
+ */
+ int priBits;
+
+ if (gic_is_vcpu(cpu)) {
+ priBits = GIC_VIRT_MAX_GROUP_PRIO_BITS;
+ } else {
+ priBits = s->n_prio_bits;
+ }
+ return ~0U << (8 - priBits);
+}
+
void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val,
MemTxAttrs attrs)
{
@@ -651,6 +668,8 @@ void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val,
val = 0x80 | (val >> 1); /* Non-secure view */
}
+ val &= gic_fullprio_mask(s, cpu);
+
if (irq < GIC_INTERNAL) {
s->priority1[irq][cpu] = val;
} else {
@@ -669,7 +688,7 @@ static uint32_t gic_dist_get_priority(GICState *s, int cpu, int irq,
}
prio = (prio << 1) & 0xff; /* Non-secure view */
}
- return prio;
+ return prio & gic_fullprio_mask(s, cpu);
}
static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask,
@@ -684,7 +703,7 @@ static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask,
return;
}
}
- s->priority_mask[cpu] = pmask;
+ s->priority_mask[cpu] = pmask & gic_fullprio_mask(s, cpu);
}
static uint32_t gic_get_priority_mask(GICState *s, int cpu, MemTxAttrs attrs)
@@ -2055,6 +2074,16 @@ static void arm_gic_realize(DeviceState *dev, Error **errp)
return;
}
+ if (s->n_prio_bits > GIC_MAX_PRIORITY_BITS ||
+ (s->virt_extn ? s->n_prio_bits < GIC_VIRT_MAX_GROUP_PRIO_BITS :
+ s->n_prio_bits < GIC_MIN_PRIORITY_BITS)) {
+ error_setg(errp, "num-priority-bits cannot be greater than %d"
+ " or less than %d", GIC_MAX_PRIORITY_BITS,
+ s->virt_extn ? GIC_VIRT_MAX_GROUP_PRIO_BITS :
+ GIC_MIN_PRIORITY_BITS);
+ return;
+ }
+
/* This creates distributor, main CPU interface (s->cpuiomem[0]) and if
* enabled, virtualization extensions related interfaces (main virtual
* interface (s->vifaceiomem[0]) and virtual CPU interface).
diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c
index e6c4fe7a5a4..7b44d5625b6 100644
--- a/hw/intc/arm_gic_common.c
+++ b/hw/intc/arm_gic_common.c
@@ -357,6 +357,7 @@ static Property arm_gic_common_properties[] = {
DEFINE_PROP_BOOL("has-security-extensions", GICState, security_extn, 0),
/* True if the GIC should implement the virtualization extensions */
DEFINE_PROP_BOOL("has-virtualization-extensions", GICState, virt_extn, 0),
+ DEFINE_PROP_UINT32("num-priority-bits", GICState, n_prio_bits, 8),
DEFINE_PROP_END_OF_LIST(),
};
--
2.20.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 05/33] cpu/a9mpcore: Set number of GIC priority bits to 5
2020-02-28 16:38 [PULL 00/33] target-arm queue Peter Maydell
` (3 preceding siblings ...)
2020-02-28 16:38 ` [PULL 04/33] arm_gic: Mask the un-supported priority bits Peter Maydell
@ 2020-02-28 16:38 ` Peter Maydell
2020-02-28 16:38 ` [PULL 06/33] cpu/arm11mpcore: Set number of GIC priority bits to 4 Peter Maydell
` (28 subsequent siblings)
33 siblings, 0 replies; 57+ messages in thread
From: Peter Maydell @ 2020-02-28 16:38 UTC (permalink / raw)
To: qemu-devel
From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
All A9 CPUs have a GIC with 5 bits of priority.
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1582537164-764-3-git-send-email-sai.pavan.boddu@xilinx.com
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/cpu/a9mpcore.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c
index 1f8bc8a196f..b4f6a7e8a54 100644
--- a/hw/cpu/a9mpcore.c
+++ b/hw/cpu/a9mpcore.c
@@ -16,6 +16,8 @@
#include "hw/qdev-properties.h"
#include "hw/core/cpu.h"
+#define A9_GIC_NUM_PRIORITY_BITS 5
+
static void a9mp_priv_set_irq(void *opaque, int irq, int level)
{
A9MPPrivState *s = (A9MPPrivState *)opaque;
@@ -68,6 +70,8 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp)
gicdev = DEVICE(&s->gic);
qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
+ qdev_prop_set_uint32(gicdev, "num-priority-bits",
+ A9_GIC_NUM_PRIORITY_BITS);
/* Make the GIC's TZ support match the CPUs. We assume that
* either all the CPUs have TZ, or none do.
--
2.20.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 06/33] cpu/arm11mpcore: Set number of GIC priority bits to 4
2020-02-28 16:38 [PULL 00/33] target-arm queue Peter Maydell
` (4 preceding siblings ...)
2020-02-28 16:38 ` [PULL 05/33] cpu/a9mpcore: Set number of GIC priority bits to 5 Peter Maydell
@ 2020-02-28 16:38 ` Peter Maydell
2020-02-28 16:38 ` [PULL 07/33] target/arm: Add isar_feature_aa32_vfp_simd Peter Maydell
` (27 subsequent siblings)
33 siblings, 0 replies; 57+ messages in thread
From: Peter Maydell @ 2020-02-28 16:38 UTC (permalink / raw)
To: qemu-devel
From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
The GIC built into the ARM11MPCore is always implemented with 4
priority bits; set the GIC property accordingly.
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1582537164-764-4-git-send-email-sai.pavan.boddu@xilinx.com
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: tweaked commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/cpu/arm11mpcore.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/hw/cpu/arm11mpcore.c b/hw/cpu/arm11mpcore.c
index 2e3e87cc1b3..ab9fadb67cb 100644
--- a/hw/cpu/arm11mpcore.c
+++ b/hw/cpu/arm11mpcore.c
@@ -15,6 +15,7 @@
#include "hw/irq.h"
#include "hw/qdev-properties.h"
+#define ARM11MPCORE_NUM_GIC_PRIORITY_BITS 4
static void mpcore_priv_set_irq(void *opaque, int irq, int level)
{
@@ -86,6 +87,10 @@ static void mpcore_priv_realize(DeviceState *dev, Error **errp)
qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
+ qdev_prop_set_uint32(gicdev, "num-priority-bits",
+ ARM11MPCORE_NUM_GIC_PRIORITY_BITS);
+
+
object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
--
2.20.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 07/33] target/arm: Add isar_feature_aa32_vfp_simd
2020-02-28 16:38 [PULL 00/33] target-arm queue Peter Maydell
` (5 preceding siblings ...)
2020-02-28 16:38 ` [PULL 06/33] cpu/arm11mpcore: Set number of GIC priority bits to 4 Peter Maydell
@ 2020-02-28 16:38 ` Peter Maydell
2020-02-28 16:38 ` [PULL 08/33] target/arm: Rename isar_feature_aa32_fpdp_v2 Peter Maydell
` (26 subsequent siblings)
33 siblings, 0 replies; 57+ messages in thread
From: Peter Maydell @ 2020-02-28 16:38 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Use this in the places that were checking ARM_FEATURE_VFP, and
are obviously testing for the existance of the register set
as opposed to testing for some particular instruction extension.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200224222232.13807-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 9 +++++++++
hw/intc/armv7m_nvic.c | 20 ++++++++++----------
linux-user/arm/signal.c | 4 ++--
target/arm/arch_dump.c | 11 ++++++-----
target/arm/cpu.c | 4 ++--
target/arm/helper.c | 4 ++--
target/arm/m_helper.c | 11 ++++++-----
7 files changed, 37 insertions(+), 26 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 65171cb30ee..a128d48d405 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3450,6 +3450,15 @@ static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
}
+static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id)
+{
+ /*
+ * Return true if either VFP or SIMD is implemented.
+ * In this case, a minimum of VFP w/ D0-D15.
+ */
+ return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0;
+}
+
static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id)
{
/* Return true if D16-D31 are implemented */
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 22a43e49847..a62587eb3f0 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -1262,12 +1262,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
case 0xd84: /* CSSELR */
return cpu->env.v7m.csselr[attrs.secure];
case 0xd88: /* CPACR */
- if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
+ if (!cpu_isar_feature(aa32_vfp_simd, cpu)) {
return 0;
}
return cpu->env.v7m.cpacr[attrs.secure];
case 0xd8c: /* NSACR */
- if (!attrs.secure || !arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
+ if (!attrs.secure || !cpu_isar_feature(aa32_vfp_simd, cpu)) {
return 0;
}
return cpu->env.v7m.nsacr;
@@ -1417,7 +1417,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
}
return cpu->env.v7m.sfar;
case 0xf34: /* FPCCR */
- if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
+ if (!cpu_isar_feature(aa32_vfp_simd, cpu)) {
return 0;
}
if (attrs.secure) {
@@ -1444,12 +1444,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
return value;
}
case 0xf38: /* FPCAR */
- if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
+ if (!cpu_isar_feature(aa32_vfp_simd, cpu)) {
return 0;
}
return cpu->env.v7m.fpcar[attrs.secure];
case 0xf3c: /* FPDSCR */
- if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
+ if (!cpu_isar_feature(aa32_vfp_simd, cpu)) {
return 0;
}
return cpu->env.v7m.fpdscr[attrs.secure];
@@ -1711,13 +1711,13 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
}
break;
case 0xd88: /* CPACR */
- if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
+ if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
/* We implement only the Floating Point extension's CP10/CP11 */
cpu->env.v7m.cpacr[attrs.secure] = value & (0xf << 20);
}
break;
case 0xd8c: /* NSACR */
- if (attrs.secure && arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
+ if (attrs.secure && cpu_isar_feature(aa32_vfp_simd, cpu)) {
/* We implement only the Floating Point extension's CP10/CP11 */
cpu->env.v7m.nsacr = value & (3 << 10);
}
@@ -1951,7 +1951,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
break;
}
case 0xf34: /* FPCCR */
- if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
+ if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
/* Not all bits here are banked. */
uint32_t fpccr_s;
@@ -2005,13 +2005,13 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
}
break;
case 0xf38: /* FPCAR */
- if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
+ if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
value &= ~7;
cpu->env.v7m.fpcar[attrs.secure] = value;
}
break;
case 0xf3c: /* FPDSCR */
- if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
+ if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
value &= 0x07c00000;
cpu->env.v7m.fpdscr[attrs.secure] = value;
}
diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c
index b0e753801b6..d96fc27ce11 100644
--- a/linux-user/arm/signal.c
+++ b/linux-user/arm/signal.c
@@ -346,7 +346,7 @@ static void setup_sigframe_v2(struct target_ucontext_v2 *uc,
setup_sigcontext(&uc->tuc_mcontext, env, set->sig[0]);
/* Save coprocessor signal frame. */
regspace = uc->tuc_regspace;
- if (arm_feature(env, ARM_FEATURE_VFP)) {
+ if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) {
regspace = setup_sigframe_v2_vfp(regspace, env);
}
if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
@@ -671,7 +671,7 @@ static int do_sigframe_return_v2(CPUARMState *env,
/* Restore coprocessor signal frame */
regspace = uc->tuc_regspace;
- if (arm_feature(env, ARM_FEATURE_VFP)) {
+ if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) {
regspace = restore_sigframe_v2_vfp(env, regspace);
if (!regspace) {
return 1;
diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c
index 2345dec3c2c..7693e17e964 100644
--- a/target/arm/arch_dump.c
+++ b/target/arm/arch_dump.c
@@ -363,9 +363,11 @@ int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
int cpuid, void *opaque)
{
struct arm_note note;
- CPUARMState *env = &ARM_CPU(cs)->env;
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
DumpState *s = opaque;
- int ret, i, fpvalid = !!arm_feature(env, ARM_FEATURE_VFP);
+ int ret, i;
+ bool fpvalid = cpu_isar_feature(aa32_vfp_simd, cpu);
arm_note_init(¬e, s, "CORE", 5, NT_PRSTATUS, sizeof(note.prstatus));
@@ -444,7 +446,6 @@ int cpu_get_dump_info(ArchDumpInfo *info,
ssize_t cpu_get_note_size(int class, int machine, int nr_cpus)
{
ARMCPU *cpu = ARM_CPU(first_cpu);
- CPUARMState *env = &cpu->env;
size_t note_size;
if (class == ELFCLASS64) {
@@ -452,12 +453,12 @@ ssize_t cpu_get_note_size(int class, int machine, int nr_cpus)
note_size += AARCH64_PRFPREG_NOTE_SIZE;
#ifdef TARGET_AARCH64
if (cpu_isar_feature(aa64_sve, cpu)) {
- note_size += AARCH64_SVE_NOTE_SIZE(env);
+ note_size += AARCH64_SVE_NOTE_SIZE(&cpu->env);
}
#endif
} else {
note_size = ARM_PRSTATUS_NOTE_SIZE;
- if (arm_feature(env, ARM_FEATURE_VFP)) {
+ if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
note_size += ARM_VFP_NOTE_SIZE;
}
}
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 2eadf4dcb8b..be4c2a1253d 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -293,7 +293,7 @@ static void arm_cpu_reset(CPUState *s)
env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK;
}
- if (arm_feature(env, ARM_FEATURE_VFP)) {
+ if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK;
env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK |
R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK;
@@ -1011,7 +1011,7 @@ static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
int numvfpregs = 0;
if (cpu_isar_feature(aa32_simd_r32, cpu)) {
numvfpregs = 32;
- } else if (arm_feature(env, ARM_FEATURE_VFP)) {
+ } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
numvfpregs = 16;
}
for (i = 0; i < numvfpregs; i++) {
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 79db169e046..8841cc7fde8 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -894,7 +894,7 @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
* ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
* TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
*/
- if (arm_feature(env, ARM_FEATURE_VFP)) {
+ if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) {
/* VFP coprocessor: cp10 & cp11 [23:20] */
mask |= (1 << 31) | (1 << 30) | (0xf << 20);
@@ -7814,7 +7814,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
} else if (cpu_isar_feature(aa32_simd_r32, cpu)) {
gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
35, "arm-vfp3.xml", 0);
- } else if (arm_feature(env, ARM_FEATURE_VFP)) {
+ } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
19, "arm-vfp.xml", 0);
}
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index 33d414a684b..5e8a795d202 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -738,7 +738,8 @@ static uint32_t v7m_integrity_sig(CPUARMState *env, uint32_t lr)
*/
uint32_t sig = 0xfefa125a;
- if (!arm_feature(env, ARM_FEATURE_VFP) || (lr & R_V7M_EXCRET_FTYPE_MASK)) {
+ if (!cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))
+ || (lr & R_V7M_EXCRET_FTYPE_MASK)) {
sig |= 1;
}
return sig;
@@ -841,7 +842,7 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain,
if (dotailchain) {
/* Sanitize LR FType and PREFIX bits */
- if (!arm_feature(env, ARM_FEATURE_VFP)) {
+ if (!cpu_isar_feature(aa32_vfp_simd, cpu)) {
lr |= R_V7M_EXCRET_FTYPE_MASK;
}
lr = deposit32(lr, 24, 8, 0xff);
@@ -1373,7 +1374,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu)
ftype = excret & R_V7M_EXCRET_FTYPE_MASK;
- if (!arm_feature(env, ARM_FEATURE_VFP) && !ftype) {
+ if (!ftype && !cpu_isar_feature(aa32_vfp_simd, cpu)) {
qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero FTYPE in exception "
"exit PC value 0x%" PRIx32 " is UNPREDICTABLE "
"if FPU not present\n",
@@ -2450,7 +2451,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
* SFPA is RAZ/WI from NS. FPCA is RO if NSACR.CP10 == 0,
* RES0 if the FPU is not present, and is stored in the S bank
*/
- if (arm_feature(env, ARM_FEATURE_VFP) &&
+ if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env)) &&
extract32(env->v7m.nsacr, 10, 1)) {
env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_FPCA_MASK;
env->v7m.control[M_REG_S] |= val & R_V7M_CONTROL_FPCA_MASK;
@@ -2565,7 +2566,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
env->v7m.control[env->v7m.secure] &= ~R_V7M_CONTROL_NPRIV_MASK;
env->v7m.control[env->v7m.secure] |= val & R_V7M_CONTROL_NPRIV_MASK;
}
- if (arm_feature(env, ARM_FEATURE_VFP)) {
+ if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) {
/*
* SFPA is RAZ/WI from NS or if no FPU.
* FPCA is RO if NSACR.CP10 == 0, RES0 if the FPU is not present.
--
2.20.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 08/33] target/arm: Rename isar_feature_aa32_fpdp_v2
2020-02-28 16:38 [PULL 00/33] target-arm queue Peter Maydell
` (6 preceding siblings ...)
2020-02-28 16:38 ` [PULL 07/33] target/arm: Add isar_feature_aa32_vfp_simd Peter Maydell
@ 2020-02-28 16:38 ` Peter Maydell
2020-02-28 16:38 ` [PULL 09/33] target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3} Peter Maydell
` (25 subsequent siblings)
33 siblings, 0 replies; 57+ messages in thread
From: Peter Maydell @ 2020-02-28 16:38 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
The old name, isar_feature_aa32_fpdp, does not reflect
that the test includes VFPv2. We will introduce another
feature tests for VFPv3.
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200224222232.13807-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 4 ++--
target/arm/translate-vfp.inc.c | 40 +++++++++++++++++-----------------
2 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a128d48d405..1e6eac0cd2a 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3470,9 +3470,9 @@ static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id)
return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0;
}
-static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id)
+static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id)
{
- /* Return true if CPU supports double precision floating point */
+ /* Return true if CPU supports double precision floating point, VFPv2 */
return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0;
}
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index ba46e2557a1..e94876c30ca 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -206,7 +206,7 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
return false;
}
- if (dp && !dc_isar_feature(aa32_fpdp, s)) {
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -339,7 +339,7 @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a)
return false;
}
- if (dp && !dc_isar_feature(aa32_fpdp, s)) {
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -425,7 +425,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
return false;
}
- if (dp && !dc_isar_feature(aa32_fpdp, s)) {
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -488,7 +488,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
return false;
}
- if (dp && !dc_isar_feature(aa32_fpdp, s)) {
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -1313,7 +1313,7 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn,
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -1462,7 +1462,7 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -1827,7 +1827,7 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -1926,7 +1926,7 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2070,7 +2070,7 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2143,7 +2143,7 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2209,7 +2209,7 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2269,7 +2269,7 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2330,7 +2330,7 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2389,7 +2389,7 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2417,7 +2417,7 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2445,7 +2445,7 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2499,7 +2499,7 @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2539,7 +2539,7 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2632,7 +2632,7 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2728,7 +2728,7 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
--
2.20.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 09/33] target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3}
2020-02-28 16:38 [PULL 00/33] target-arm queue Peter Maydell
` (7 preceding siblings ...)
2020-02-28 16:38 ` [PULL 08/33] target/arm: Rename isar_feature_aa32_fpdp_v2 Peter Maydell
@ 2020-02-28 16:38 ` Peter Maydell
2020-02-28 16:38 ` [PULL 10/33] target/arm: Add isar_feature_aa64_fp_simd, isar_feature_aa32_vfp Peter Maydell
` (24 subsequent siblings)
33 siblings, 0 replies; 57+ messages in thread
From: Peter Maydell @ 2020-02-28 16:38 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
We will shortly use these to test for VFPv2 and VFPv3
in different situations.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200224222232.13807-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 1e6eac0cd2a..f7a90f512e3 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3470,12 +3470,30 @@ static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id)
return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0;
}
+static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id)
+{
+ /* Return true if CPU supports single precision floating point, VFPv2 */
+ return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0;
+}
+
+static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id)
+{
+ /* Return true if CPU supports single precision floating point, VFPv3 */
+ return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2;
+}
+
static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id)
{
/* Return true if CPU supports double precision floating point, VFPv2 */
return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0;
}
+static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id)
+{
+ /* Return true if CPU supports double precision floating point, VFPv3 */
+ return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2;
+}
+
/*
* We always set the FP and SIMD FP16 fields to indicate identical
* levels of support (assuming SIMD is implemented at all), so
--
2.20.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 10/33] target/arm: Add isar_feature_aa64_fp_simd, isar_feature_aa32_vfp
2020-02-28 16:38 [PULL 00/33] target-arm queue Peter Maydell
` (8 preceding siblings ...)
2020-02-28 16:38 ` [PULL 09/33] target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3} Peter Maydell
@ 2020-02-28 16:38 ` Peter Maydell
2020-02-28 16:38 ` [PULL 11/33] target/arm: Perform fpdp_v2 check first Peter Maydell
` (23 subsequent siblings)
33 siblings, 0 replies; 57+ messages in thread
From: Peter Maydell @ 2020-02-28 16:38 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
We cannot easily create "any" functions for these, because the
ID_AA64PFR0 fields for FP and SIMD signal "enabled" with zero.
Which means that an aarch32-only cpu will return incorrect results
when testing the aarch64 registers.
To use these, we must either have context or additionally test
vs ARM_FEATURE_AARCH64.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200224222232.13807-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 11 +++++++++++
target/arm/cpu.c | 9 ++++++---
target/arm/machine.c | 5 +++--
3 files changed, 20 insertions(+), 5 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index f7a90f512e3..b94d2a5ace4 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3494,6 +3494,11 @@ static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id)
return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2;
}
+static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id)
+{
+ return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id);
+}
+
/*
* We always set the FP and SIMD FP16 fields to indicate identical
* levels of support (assuming SIMD is implemented at all), so
@@ -3696,6 +3701,12 @@ static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id)
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2;
}
+static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id)
+{
+ /* We always set the AdvSIMD and FP fields identically. */
+ return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf;
+}
+
static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)
{
/* We always set the AdvSIMD and FP fields identically wrt FP16. */
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index be4c2a1253d..5be4c258096 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1260,7 +1260,9 @@ void arm_cpu_post_init(Object *obj)
* KVM does not currently allow us to lie to the guest about its
* ID/feature registers, so the guest always sees what the host has.
*/
- if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
+ if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)
+ ? cpu_isar_feature(aa64_fp_simd, cpu)
+ : cpu_isar_feature(aa32_vfp, cpu)) {
cpu->has_vfp = true;
if (!kvm_enabled()) {
qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property);
@@ -1636,8 +1638,9 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
* We rely on no XScale CPU having VFP so we can use the same bits in the
* TB flags field for VECSTRIDE and XSCALE_CPAR.
*/
- assert(!(arm_feature(env, ARM_FEATURE_VFP) &&
- arm_feature(env, ARM_FEATURE_XSCALE)));
+ assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) ||
+ !cpu_isar_feature(aa32_vfp_simd, cpu) ||
+ !arm_feature(env, ARM_FEATURE_XSCALE));
if (arm_feature(env, ARM_FEATURE_V7) &&
!arm_feature(env, ARM_FEATURE_M) &&
diff --git a/target/arm/machine.c b/target/arm/machine.c
index 241890ac8cf..c5a2114f51c 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -9,9 +9,10 @@
static bool vfp_needed(void *opaque)
{
ARMCPU *cpu = opaque;
- CPUARMState *env = &cpu->env;
- return arm_feature(env, ARM_FEATURE_VFP);
+ return (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)
+ ? cpu_isar_feature(aa64_fp_simd, cpu)
+ : cpu_isar_feature(aa32_vfp_simd, cpu));
}
static int get_fpscr(QEMUFile *f, void *opaque, size_t size,
--
2.20.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 11/33] target/arm: Perform fpdp_v2 check first
2020-02-28 16:38 [PULL 00/33] target-arm queue Peter Maydell
` (9 preceding siblings ...)
2020-02-28 16:38 ` [PULL 10/33] target/arm: Add isar_feature_aa64_fp_simd, isar_feature_aa32_vfp Peter Maydell
@ 2020-02-28 16:38 ` Peter Maydell
2020-02-28 16:38 ` [PULL 12/33] target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3 Peter Maydell
` (22 subsequent siblings)
33 siblings, 0 replies; 57+ messages in thread
From: Peter Maydell @ 2020-02-28 16:38 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Shuffle the order of the checks so that we test the ISA
before we test anything else, such as the register arguments.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200224222232.13807-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate-vfp.inc.c | 140 +++++++++++++++++----------------
1 file changed, 71 insertions(+), 69 deletions(-)
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index e94876c30ca..ff301650455 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -200,13 +200,13 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
return false;
}
- /* UNDEF accesses to D16-D31 if they don't exist */
- if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vm | a->vn | a->vd) & 0x10)) {
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
- if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
+ /* UNDEF accesses to D16-D31 if they don't exist */
+ if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vm | a->vn | a->vd) & 0x10)) {
return false;
}
@@ -333,13 +333,13 @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a)
return false;
}
- /* UNDEF accesses to D16-D31 if they don't exist */
- if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vm | a->vn | a->vd) & 0x10)) {
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
- if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
+ /* UNDEF accesses to D16-D31 if they don't exist */
+ if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vm | a->vn | a->vd) & 0x10)) {
return false;
}
@@ -419,13 +419,13 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
return false;
}
- /* UNDEF accesses to D16-D31 if they don't exist */
- if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vm | a->vd) & 0x10)) {
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
- if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
+ /* UNDEF accesses to D16-D31 if they don't exist */
+ if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vm | a->vd) & 0x10)) {
return false;
}
@@ -483,12 +483,12 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
return false;
}
- /* UNDEF accesses to D16-D31 if they don't exist */
- if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
- if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
+ /* UNDEF accesses to D16-D31 if they don't exist */
+ if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
return false;
}
@@ -1308,12 +1308,12 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn,
TCGv_i64 f0, f1, fd;
TCGv_ptr fpst;
- /* UNDEF accesses to D16-D31 if they don't exist */
- if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ /* UNDEF accesses to D16-D31 if they don't exist */
+ if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) {
return false;
}
@@ -1457,12 +1457,12 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm)
int veclen = s->vec_len;
TCGv_i64 f0, fd;
- /* UNDEF accesses to D16-D31 if they don't exist */
- if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ /* UNDEF accesses to D16-D31 if they don't exist */
+ if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) {
return false;
}
@@ -1827,7 +1827,9 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vn | a->vm) & 0x10)) {
return false;
}
@@ -1921,12 +1923,12 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
vd = a->vd;
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) && (vd & 0x10)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) && (vd & 0x10)) {
return false;
}
@@ -2060,6 +2062,10 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a)
{
TCGv_i64 vd, vm;
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+
/* Vm/M bits must be zero for the Z variant */
if (a->z && a->vm != 0) {
return false;
@@ -2070,10 +2076,6 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
if (!vfp_access_check(s)) {
return true;
}
@@ -2134,6 +2136,10 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a)
TCGv_i32 tmp;
TCGv_i64 vd;
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+
if (!dc_isar_feature(aa32_fp16_dpconv, s)) {
return false;
}
@@ -2143,10 +2149,6 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
if (!vfp_access_check(s)) {
return true;
}
@@ -2200,6 +2202,10 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a)
TCGv_i32 tmp;
TCGv_i64 vm;
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+
if (!dc_isar_feature(aa32_fp16_dpconv, s)) {
return false;
}
@@ -2209,10 +2215,6 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
if (!vfp_access_check(s)) {
return true;
}
@@ -2260,6 +2262,10 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a)
TCGv_ptr fpst;
TCGv_i64 tmp;
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+
if (!dc_isar_feature(aa32_vrint, s)) {
return false;
}
@@ -2269,10 +2275,6 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
if (!vfp_access_check(s)) {
return true;
}
@@ -2321,6 +2323,10 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
TCGv_i64 tmp;
TCGv_i32 tcg_rmode;
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+
if (!dc_isar_feature(aa32_vrint, s)) {
return false;
}
@@ -2330,10 +2336,6 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
if (!vfp_access_check(s)) {
return true;
}
@@ -2380,6 +2382,10 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a)
TCGv_ptr fpst;
TCGv_i64 tmp;
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+
if (!dc_isar_feature(aa32_vrint, s)) {
return false;
}
@@ -2389,10 +2395,6 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
if (!vfp_access_check(s)) {
return true;
}
@@ -2412,12 +2414,12 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
TCGv_i64 vd;
TCGv_i32 vm;
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
return false;
}
@@ -2440,12 +2442,12 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
TCGv_i64 vm;
TCGv_i32 vd;
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
return false;
}
@@ -2494,12 +2496,12 @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a)
TCGv_i64 vd;
TCGv_ptr fpst;
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
return false;
}
@@ -2530,6 +2532,10 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
TCGv_i32 vd;
TCGv_i64 vm;
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+
if (!dc_isar_feature(aa32_jscvt, s)) {
return false;
}
@@ -2539,10 +2545,6 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
if (!vfp_access_check(s)) {
return true;
}
@@ -2623,6 +2625,10 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
TCGv_ptr fpst;
int frac_bits;
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+
if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
return false;
}
@@ -2632,10 +2638,6 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
if (!vfp_access_check(s)) {
return true;
}
@@ -2723,12 +2725,12 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a)
TCGv_i64 vm;
TCGv_ptr fpst;
- /* UNDEF accesses to D16-D31 if they don't exist. */
- if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
return false;
}
--
2.20.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 12/33] target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3
2020-02-28 16:38 [PULL 00/33] target-arm queue Peter Maydell
` (10 preceding siblings ...)
2020-02-28 16:38 ` [PULL 11/33] target/arm: Perform fpdp_v2 check first Peter Maydell
@ 2020-02-28 16:38 ` Peter Maydell
2020-02-28 16:38 ` [PULL 13/33] target/arm: Add missing checks for fpsp_v2 Peter Maydell
` (21 subsequent siblings)
33 siblings, 0 replies; 57+ messages in thread
From: Peter Maydell @ 2020-02-28 16:38 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Sort this check to the start of a trans_* function.
Merge this with any existing test for fpdp_v2.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200224222232.13807-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate-vfp.inc.c | 24 ++++++++----------------
1 file changed, 8 insertions(+), 16 deletions(-)
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index ff301650455..51d46f43027 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -717,7 +717,7 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
* VFPv2 allows access to FPSID from userspace; VFPv3 restricts
* all ID registers to privileged access only.
*/
- if (IS_USER(s) && arm_dc_feature(s, ARM_FEATURE_VFP3)) {
+ if (IS_USER(s) && dc_isar_feature(aa32_fpsp_v3, s)) {
return false;
}
ignore_vfp_enabled = true;
@@ -746,7 +746,7 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
case ARM_VFP_FPINST:
case ARM_VFP_FPINST2:
/* Not present in VFPv3 */
- if (IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_VFP3)) {
+ if (IS_USER(s) || dc_isar_feature(aa32_fpsp_v3, s)) {
return false;
}
break;
@@ -1873,12 +1873,12 @@ static bool trans_VMOV_imm_sp(DisasContext *s, arg_VMOV_imm_sp *a)
vd = a->vd;
- if (!dc_isar_feature(aa32_fpshvec, s) &&
- (veclen != 0 || s->vec_stride != 0)) {
+ if (!dc_isar_feature(aa32_fpsp_v3, s)) {
return false;
}
- if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
+ if (!dc_isar_feature(aa32_fpshvec, s) &&
+ (veclen != 0 || s->vec_stride != 0)) {
return false;
}
@@ -1923,7 +1923,7 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
vd = a->vd;
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v3, s)) {
return false;
}
@@ -1937,10 +1937,6 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
return false;
}
- if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
- return false;
- }
-
if (!vfp_access_check(s)) {
return true;
}
@@ -2565,7 +2561,7 @@ static bool trans_VCVT_fix_sp(DisasContext *s, arg_VCVT_fix_sp *a)
TCGv_ptr fpst;
int frac_bits;
- if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
+ if (!dc_isar_feature(aa32_fpsp_v3, s)) {
return false;
}
@@ -2625,11 +2621,7 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
TCGv_ptr fpst;
int frac_bits;
- if (!dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
- if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) {
+ if (!dc_isar_feature(aa32_fpdp_v3, s)) {
return false;
}
--
2.20.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 13/33] target/arm: Add missing checks for fpsp_v2
2020-02-28 16:38 [PULL 00/33] target-arm queue Peter Maydell
` (11 preceding siblings ...)
2020-02-28 16:38 ` [PULL 12/33] target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3 Peter Maydell
@ 2020-02-28 16:38 ` Peter Maydell
2020-02-28 16:38 ` [PULL 14/33] target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac Peter Maydell
` (20 subsequent siblings)
33 siblings, 0 replies; 57+ messages in thread
From: Peter Maydell @ 2020-02-28 16:38 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
We will eventually remove the early ARM_FEATURE_VFP test,
so add a proper test for each trans_* that does not already
have another ISA test.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200224222232.13807-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate-vfp.inc.c | 78 ++++++++++++++++++++++++++++++----
1 file changed, 69 insertions(+), 9 deletions(-)
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index 51d46f43027..f88a95438fc 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -555,6 +555,13 @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a)
int pass;
uint32_t offset;
+ /* SIZE == 2 is a VFP instruction; otherwise NEON. */
+ if (a->size == 2
+ ? !dc_isar_feature(aa32_fpsp_v2, s)
+ : !arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
/* UNDEF accesses to D16-D31 if they don't exist */
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) {
return false;
@@ -564,10 +571,6 @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a)
pass = extract32(offset, 2, 1);
offset = extract32(offset, 0, 2) * 8;
- if (a->size != 2 && !arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
if (!vfp_access_check(s)) {
return true;
}
@@ -614,6 +617,13 @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a)
int pass;
uint32_t offset;
+ /* SIZE == 2 is a VFP instruction; otherwise NEON. */
+ if (a->size == 2
+ ? !dc_isar_feature(aa32_fpsp_v2, s)
+ : !arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
/* UNDEF accesses to D16-D31 if they don't exist */
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) {
return false;
@@ -623,10 +633,6 @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a)
pass = extract32(offset, 2, 1);
offset = extract32(offset, 0, 2) * 8;
- if (a->size != 2 && !arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
- }
-
if (!vfp_access_check(s)) {
return true;
}
@@ -700,6 +706,10 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
TCGv_i32 tmp;
bool ignore_vfp_enabled = false;
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
+
if (arm_dc_feature(s, ARM_FEATURE_M)) {
/*
* The only M-profile VFP vmrs/vmsr sysreg is FPSCR.
@@ -844,6 +854,10 @@ static bool trans_VMOV_single(DisasContext *s, arg_VMOV_single *a)
{
TCGv_i32 tmp;
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
+
if (!vfp_access_check(s)) {
return true;
}
@@ -873,6 +887,10 @@ static bool trans_VMOV_64_sp(DisasContext *s, arg_VMOV_64_sp *a)
{
TCGv_i32 tmp;
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
+
/*
* VMOV between two general-purpose registers and two single precision
* floating point registers
@@ -908,8 +926,12 @@ static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV_64_dp *a)
/*
* VMOV between two general-purpose registers and one double precision
- * floating point register
+ * floating point register. Note that this does not require support
+ * for double precision arithmetic.
*/
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
/* UNDEF accesses to D16-D31 if they don't exist */
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
@@ -946,6 +968,10 @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a)
uint32_t offset;
TCGv_i32 addr, tmp;
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
+
if (!vfp_access_check(s)) {
return true;
}
@@ -977,6 +1003,11 @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_dp *a)
TCGv_i32 addr;
TCGv_i64 tmp;
+ /* Note that this does not require support for double arithmetic. */
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
+
/* UNDEF accesses to D16-D31 if they don't exist */
if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
return false;
@@ -1013,6 +1044,10 @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_VLDM_VSTM_sp *a)
TCGv_i32 addr, tmp;
int i, n;
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
+
n = a->imm;
if (n == 0 || (a->vd + n) > 32) {
@@ -1086,6 +1121,11 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a)
TCGv_i64 tmp;
int i, n;
+ /* Note that this does not require support for double arithmetic. */
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
+
n = a->imm >> 1;
if (n == 0 || (a->vd + n) > 32 || n > 16) {
@@ -1234,6 +1274,10 @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3OpSPFn *fn,
TCGv_i32 f0, f1, fd;
TCGv_ptr fpst;
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
+
if (!dc_isar_feature(aa32_fpshvec, s) &&
(veclen != 0 || s->vec_stride != 0)) {
return false;
@@ -1388,6 +1432,10 @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm)
int veclen = s->vec_len;
TCGv_i32 f0, fd;
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
+
if (!dc_isar_feature(aa32_fpshvec, s) &&
(veclen != 0 || s->vec_stride != 0)) {
return false;
@@ -2023,6 +2071,10 @@ static bool trans_VCMP_sp(DisasContext *s, arg_VCMP_sp *a)
{
TCGv_i32 vd, vm;
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
+
/* Vm/M bits must be zero for the Z variant */
if (a->z && a->vm != 0) {
return false;
@@ -2466,6 +2518,10 @@ static bool trans_VCVT_int_sp(DisasContext *s, arg_VCVT_int_sp *a)
TCGv_i32 vm;
TCGv_ptr fpst;
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
+
if (!vfp_access_check(s)) {
return true;
}
@@ -2684,6 +2740,10 @@ static bool trans_VCVT_sp_int(DisasContext *s, arg_VCVT_sp_int *a)
TCGv_i32 vm;
TCGv_ptr fpst;
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
+
if (!vfp_access_check(s)) {
return true;
}
--
2.20.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 14/33] target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac
2020-02-28 16:38 [PULL 00/33] target-arm queue Peter Maydell
` (12 preceding siblings ...)
2020-02-28 16:38 ` [PULL 13/33] target/arm: Add missing checks for fpsp_v2 Peter Maydell
@ 2020-02-28 16:38 ` Peter Maydell
2020-02-28 16:38 ` [PULL 15/33] target/arm: Remove ARM_FEATURE_VFP check from disas_vfp_insn Peter Maydell
` (19 subsequent siblings)
33 siblings, 0 replies; 57+ messages in thread
From: Peter Maydell @ 2020-02-28 16:38 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
All remaining tests for VFP4 are for fused multiply-add insns.
Since the MVFR1 field is used for both VFP and NEON, move its adjustment
from the !has_neon block to the (!has_vfp && !has_neon) block.
Test for vfp of the appropraite width alongside the test for simdfmac
within translate-vfp.inc.c. Within disas_neon_data_insn, we have
already tested for ARM_FEATURE_NEON.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200224222232.13807-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 12 ++++++++++++
target/arm/cpu.c | 6 +++++-
target/arm/translate-vfp.inc.c | 22 ++++++++++++++++++----
target/arm/translate.c | 2 +-
4 files changed, 36 insertions(+), 6 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index b94d2a5ace4..b29b0eddfc3 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3514,6 +3514,18 @@ static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id)
return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1;
}
+/*
+ * Note that this ID register field covers both VFP and Neon FMAC,
+ * so should usually be tested in combination with some other
+ * check that confirms the presence of whichever of VFP or Neon is
+ * relevant, to avoid accidentally enabling a Neon feature on
+ * a VFP-no-Neon core or vice-versa.
+ */
+static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id)
+{
+ return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0;
+}
+
static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id)
{
return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 5be4c258096..dc45865c7a7 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1512,7 +1512,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
u = FIELD_DP32(u, MVFR1, SIMDINT, 0);
u = FIELD_DP32(u, MVFR1, SIMDSP, 0);
u = FIELD_DP32(u, MVFR1, SIMDHP, 0);
- u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0);
cpu->isar.mvfr1 = u;
u = cpu->isar.mvfr2;
@@ -1535,6 +1534,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
u = cpu->isar.mvfr0;
u = FIELD_DP32(u, MVFR0, SIMDREG, 0);
cpu->isar.mvfr0 = u;
+
+ /* Despite the name, this field covers both VFP and Neon */
+ u = cpu->isar.mvfr1;
+ u = FIELD_DP32(u, MVFR1, SIMDFMAC, 0);
+ cpu->isar.mvfr1 = u;
}
if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) {
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index f88a95438fc..03ba8d7aac0 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -1803,11 +1803,18 @@ static bool trans_VFM_sp(DisasContext *s, arg_VFM_sp *a)
/*
* Present in VFPv4 only.
+ * Note that we can't rely on the SIMDFMAC check alone, because
+ * in a Neon-no-VFP core that ID register field will be non-zero.
+ */
+ if (!dc_isar_feature(aa32_simdfmac, s) ||
+ !dc_isar_feature(aa32_fpsp_v2, s)) {
+ return false;
+ }
+ /*
* In v7A, UNPREDICTABLE with non-zero vector length/stride; from
* v8A, must UNDEF. We choose to UNDEF for both v7A and v8A.
*/
- if (!arm_dc_feature(s, ARM_FEATURE_VFP4) ||
- (s->vec_len != 0 || s->vec_stride != 0)) {
+ if (s->vec_len != 0 || s->vec_stride != 0) {
return false;
}
@@ -1861,11 +1868,18 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a)
/*
* Present in VFPv4 only.
+ * Note that we can't rely on the SIMDFMAC check alone, because
+ * in a Neon-no-VFP core that ID register field will be non-zero.
+ */
+ if (!dc_isar_feature(aa32_simdfmac, s) ||
+ !dc_isar_feature(aa32_fpdp_v2, s)) {
+ return false;
+ }
+ /*
* In v7A, UNPREDICTABLE with non-zero vector length/stride; from
* v8A, must UNDEF. We choose to UNDEF for both v7A and v8A.
*/
- if (!arm_dc_feature(s, ARM_FEATURE_VFP4) ||
- (s->vec_len != 0 || s->vec_stride != 0)) {
+ if (s->vec_len != 0 || s->vec_stride != 0) {
return false;
}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 79880adaad2..0489e0cdaa6 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -5150,7 +5150,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
}
break;
case NEON_3R_VFM_VQRDMLSH:
- if (!arm_dc_feature(s, ARM_FEATURE_VFP4)) {
+ if (!dc_isar_feature(aa32_simdfmac, s)) {
return 1;
}
break;
--
2.20.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 15/33] target/arm: Remove ARM_FEATURE_VFP check from disas_vfp_insn
2020-02-28 16:38 [PULL 00/33] target-arm queue Peter Maydell
` (13 preceding siblings ...)
2020-02-28 16:38 ` [PULL 14/33] target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac Peter Maydell
@ 2020-02-28 16:38 ` Peter Maydell
2020-02-28 16:38 ` [PULL 16/33] target/arm: Move VLLDM and VLSTM to vfp.decode Peter Maydell
` (18 subsequent siblings)
33 siblings, 0 replies; 57+ messages in thread
From: Peter Maydell @ 2020-02-28 16:38 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
We now have proper ISA checks within each trans_* function.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200224222232.13807-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 0489e0cdaa6..893911fca70 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -2652,10 +2652,6 @@ static void gen_neon_dup_high16(TCGv_i32 var)
*/
static int disas_vfp_insn(DisasContext *s, uint32_t insn)
{
- if (!arm_dc_feature(s, ARM_FEATURE_VFP)) {
- return 1;
- }
-
/*
* If the decodetree decoder handles this insn it will always
* emit code to either execute the insn or generate an appropriate
--
2.20.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 16/33] target/arm: Move VLLDM and VLSTM to vfp.decode
2020-02-28 16:38 [PULL 00/33] target-arm queue Peter Maydell
` (14 preceding siblings ...)
2020-02-28 16:38 ` [PULL 15/33] target/arm: Remove ARM_FEATURE_VFP check from disas_vfp_insn Peter Maydell
@ 2020-02-28 16:38 ` Peter Maydell
2020-02-28 16:38 ` [PULL 17/33] target/arm: Move the vfp decodetree calls next to the base isa Peter Maydell
` (17 subsequent siblings)
33 siblings, 0 replies; 57+ messages in thread
From: Peter Maydell @ 2020-02-28 16:38 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Now that we no longer have an early check for ARM_FEATURE_VFP,
we can use the proper ISA check in trans_VLLDM_VLSTM.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200224222232.13807-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate-vfp.inc.c | 39 +++++++++++++++++++++++++
target/arm/translate.c | 53 ++++++----------------------------
target/arm/vfp.decode | 2 ++
3 files changed, 50 insertions(+), 44 deletions(-)
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index 03ba8d7aac0..1964af3ea5e 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -2828,3 +2828,42 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a)
tcg_temp_free_ptr(fpst);
return true;
}
+
+/*
+ * Decode VLLDM and VLSTM are nonstandard because:
+ * * if there is no FPU then these insns must NOP in
+ * Secure state and UNDEF in Nonsecure state
+ * * if there is an FPU then these insns do not have
+ * the usual behaviour that vfp_access_check() provides of
+ * being controlled by CPACR/NSACR enable bits or the
+ * lazy-stacking logic.
+ */
+static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a)
+{
+ TCGv_i32 fptr;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_M) ||
+ !arm_dc_feature(s, ARM_FEATURE_V8)) {
+ return false;
+ }
+ /* If not secure, UNDEF. */
+ if (!s->v8m_secure) {
+ return false;
+ }
+ /* If no fpu, NOP. */
+ if (!dc_isar_feature(aa32_vfp, s)) {
+ return true;
+ }
+
+ fptr = load_reg(s, a->rn);
+ if (a->l) {
+ gen_helper_v7m_vlldm(cpu_env, fptr);
+ } else {
+ gen_helper_v7m_vlstm(cpu_env, fptr);
+ }
+ tcg_temp_free_i32(fptr);
+
+ /* End the TB, because we have updated FP control bits */
+ s->base.is_jmp = DISAS_UPDATE;
+ return true;
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 893911fca70..5b7cad1ea2d 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10962,53 +10962,18 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
goto illegal_op; /* op0 = 0b11 : unallocated */
}
- /*
- * Decode VLLDM and VLSTM first: these are nonstandard because:
- * * if there is no FPU then these insns must NOP in
- * Secure state and UNDEF in Nonsecure state
- * * if there is an FPU then these insns do not have
- * the usual behaviour that disas_vfp_insn() provides of
- * being controlled by CPACR/NSACR enable bits or the
- * lazy-stacking logic.
- */
- if (arm_dc_feature(s, ARM_FEATURE_V8) &&
- (insn & 0xffa00f00) == 0xec200a00) {
- /* 0b1110_1100_0x1x_xxxx_xxxx_1010_xxxx_xxxx
- * - VLLDM, VLSTM
- * We choose to UNDEF if the RAZ bits are non-zero.
- */
- if (!s->v8m_secure || (insn & 0x0040f0ff)) {
+ if (disas_vfp_insn(s, insn)) {
+ if (((insn >> 8) & 0xe) == 10 &&
+ dc_isar_feature(aa32_fpsp_v2, s)) {
+ /* FP, and the CPU supports it */
goto illegal_op;
+ } else {
+ /* All other insns: NOCP */
+ gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
+ syn_uncategorized(),
+ default_exception_el(s));
}
-
- if (arm_dc_feature(s, ARM_FEATURE_VFP)) {
- uint32_t rn = (insn >> 16) & 0xf;
- TCGv_i32 fptr = load_reg(s, rn);
-
- if (extract32(insn, 20, 1)) {
- gen_helper_v7m_vlldm(cpu_env, fptr);
- } else {
- gen_helper_v7m_vlstm(cpu_env, fptr);
- }
- tcg_temp_free_i32(fptr);
-
- /* End the TB, because we have updated FP control bits */
- s->base.is_jmp = DISAS_UPDATE;
- }
- break;
}
- if (arm_dc_feature(s, ARM_FEATURE_VFP) &&
- ((insn >> 8) & 0xe) == 10) {
- /* FP, and the CPU supports it */
- if (disas_vfp_insn(s, insn)) {
- goto illegal_op;
- }
- break;
- }
-
- /* All other insns: NOCP */
- gen_exception_insn(s, s->pc_curr, EXCP_NOCP, syn_uncategorized(),
- default_exception_el(s));
break;
}
if ((insn & 0xfe000a00) == 0xfc000800
diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode
index a67b3f29ee5..592fe9e1e42 100644
--- a/target/arm/vfp.decode
+++ b/target/arm/vfp.decode
@@ -242,3 +242,5 @@ VCVT_sp_int ---- 1110 1.11 110 s:1 .... 1010 rz:1 1.0 .... \
vd=%vd_sp vm=%vm_sp
VCVT_dp_int ---- 1110 1.11 110 s:1 .... 1011 rz:1 1.0 .... \
vd=%vd_sp vm=%vm_dp
+
+VLLDM_VLSTM 1110 1100 001 l:1 rn:4 0000 1010 0000 0000
--
2.20.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 17/33] target/arm: Move the vfp decodetree calls next to the base isa
2020-02-28 16:38 [PULL 00/33] target-arm queue Peter Maydell
` (15 preceding siblings ...)
2020-02-28 16:38 ` [PULL 16/33] target/arm: Move VLLDM and VLSTM to vfp.decode Peter Maydell
@ 2020-02-28 16:38 ` Peter Maydell
2020-02-28 16:38 ` [PULL 18/33] linux-user/arm: Replace ARM_FEATURE_VFP* tests for HWCAP Peter Maydell
` (16 subsequent siblings)
33 siblings, 0 replies; 57+ messages in thread
From: Peter Maydell @ 2020-02-28 16:38 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Have the calls adjacent as an intermediate step toward
actually merging the decodes.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200224222232.13807-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate.c | 83 +++++++++++++++---------------------------
1 file changed, 29 insertions(+), 54 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 5b7cad1ea2d..6259064ea7c 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -2646,31 +2646,6 @@ static void gen_neon_dup_high16(TCGv_i32 var)
tcg_temp_free_i32(tmp);
}
-/*
- * Disassemble a VFP instruction. Returns nonzero if an error occurred
- * (ie. an undefined instruction).
- */
-static int disas_vfp_insn(DisasContext *s, uint32_t insn)
-{
- /*
- * If the decodetree decoder handles this insn it will always
- * emit code to either execute the insn or generate an appropriate
- * exception; so we don't need to ever return non-zero to tell
- * the calling code to emit an UNDEF exception.
- */
- if (extract32(insn, 28, 4) == 0xf) {
- if (disas_vfp_uncond(s, insn)) {
- return 0;
- }
- } else {
- if (disas_vfp(s, insn)) {
- return 0;
- }
- }
- /* If the decodetree decoder didn't handle this insn, it must be UNDEF */
- return 1;
-}
-
static inline bool use_goto_tb(DisasContext *s, target_ulong dest)
{
#ifndef CONFIG_USER_ONLY
@@ -10778,7 +10753,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
ARCH(5);
/* Unconditional instructions. */
- if (disas_a32_uncond(s, insn)) {
+ /* TODO: Perhaps merge these into one decodetree output file. */
+ if (disas_a32_uncond(s, insn) ||
+ disas_vfp_uncond(s, insn)) {
return;
}
/* fall back to legacy decoder */
@@ -10805,13 +10782,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
}
return;
}
- if ((insn & 0x0f000e10) == 0x0e000a00) {
- /* VFP. */
- if (disas_vfp_insn(s, insn)) {
- goto illegal_op;
- }
- return;
- }
if ((insn & 0x0e000f00) == 0x0c000100) {
if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) {
/* iWMMXt register transfer. */
@@ -10842,7 +10812,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
arm_skip_unless(s, cond);
}
- if (disas_a32(s, insn)) {
+ /* TODO: Perhaps merge these into one decodetree output file. */
+ if (disas_a32(s, insn) ||
+ disas_vfp(s, insn)) {
return;
}
/* fall back to legacy decoder */
@@ -10852,11 +10824,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
case 0xd:
case 0xe:
if (((insn >> 8) & 0xe) == 10) {
- /* VFP. */
- if (disas_vfp_insn(s, insn)) {
- goto illegal_op;
- }
- } else if (disas_coproc_insn(s, insn)) {
+ /* VFP, but failed disas_vfp. */
+ goto illegal_op;
+ }
+ if (disas_coproc_insn(s, insn)) {
/* Coprocessor. */
goto illegal_op;
}
@@ -10945,7 +10916,14 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
ARCH(6T2);
}
- if (disas_t32(s, insn)) {
+ /*
+ * TODO: Perhaps merge these into one decodetree output file.
+ * Note disas_vfp is written for a32 with cond field in the
+ * top nibble. The t32 encoding requires 0xe in the top nibble.
+ */
+ if (disas_t32(s, insn) ||
+ disas_vfp_uncond(s, insn) ||
+ ((insn >> 28) == 0xe && disas_vfp(s, insn))) {
return;
}
/* fall back to legacy decoder */
@@ -10962,17 +10940,15 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
goto illegal_op; /* op0 = 0b11 : unallocated */
}
- if (disas_vfp_insn(s, insn)) {
- if (((insn >> 8) & 0xe) == 10 &&
- dc_isar_feature(aa32_fpsp_v2, s)) {
- /* FP, and the CPU supports it */
- goto illegal_op;
- } else {
- /* All other insns: NOCP */
- gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
- syn_uncategorized(),
- default_exception_el(s));
- }
+ if (((insn >> 8) & 0xe) == 10 &&
+ dc_isar_feature(aa32_fpsp_v2, s)) {
+ /* FP, and the CPU supports it */
+ goto illegal_op;
+ } else {
+ /* All other insns: NOCP */
+ gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
+ syn_uncategorized(),
+ default_exception_el(s));
}
break;
}
@@ -10995,9 +10971,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
goto illegal_op;
}
} else if (((insn >> 8) & 0xe) == 10) {
- if (disas_vfp_insn(s, insn)) {
- goto illegal_op;
- }
+ /* VFP, but failed disas_vfp. */
+ goto illegal_op;
} else {
if (insn & (1 << 28))
goto illegal_op;
--
2.20.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 18/33] linux-user/arm: Replace ARM_FEATURE_VFP* tests for HWCAP
2020-02-28 16:38 [PULL 00/33] target-arm queue Peter Maydell
` (16 preceding siblings ...)
2020-02-28 16:38 ` [PULL 17/33] target/arm: Move the vfp decodetree calls next to the base isa Peter Maydell
@ 2020-02-28 16:38 ` Peter Maydell
2020-02-28 16:38 ` [PULL 19/33] target/arm: Remove ARM_FEATURE_VFP* Peter Maydell
` (15 subsequent siblings)
33 siblings, 0 replies; 57+ messages in thread
From: Peter Maydell @ 2020-02-28 16:38 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Use isar feature tests instead of feature bit tests.
Although none of QEMUs current cpus have VFPv3 without D32,
replace the large comment explaining why with one line that
sets ARM_HWCAP_ARM_VFPv3D16 under the correct conditions.
Mirror the test sequence used in the linux kernel.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200224222232.13807-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
linux-user/elfload.c | 23 +++++++++++++----------
1 file changed, 13 insertions(+), 10 deletions(-)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index b1a895f24ce..86cda127b78 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -468,22 +468,25 @@ static uint32_t get_elf_hwcap(void)
/* EDSP is in v5TE and above, but all our v5 CPUs are v5TE */
GET_FEATURE(ARM_FEATURE_V5, ARM_HWCAP_ARM_EDSP);
- GET_FEATURE(ARM_FEATURE_VFP, ARM_HWCAP_ARM_VFP);
GET_FEATURE(ARM_FEATURE_IWMMXT, ARM_HWCAP_ARM_IWMMXT);
GET_FEATURE(ARM_FEATURE_THUMB2EE, ARM_HWCAP_ARM_THUMBEE);
GET_FEATURE(ARM_FEATURE_NEON, ARM_HWCAP_ARM_NEON);
- GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPv3);
GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS);
- GET_FEATURE(ARM_FEATURE_VFP4, ARM_HWCAP_ARM_VFPv4);
+ GET_FEATURE(ARM_FEATURE_LPAE, ARM_HWCAP_ARM_LPAE);
GET_FEATURE_ID(aa32_arm_div, ARM_HWCAP_ARM_IDIVA);
GET_FEATURE_ID(aa32_thumb_div, ARM_HWCAP_ARM_IDIVT);
- /* All QEMU's VFPv3 CPUs have 32 registers, see VFP_DREG in translate.c.
- * Note that the ARM_HWCAP_ARM_VFPv3D16 bit is always the inverse of
- * ARM_HWCAP_ARM_VFPD32 (and so always clear for QEMU); it is unrelated
- * to our VFP_FP16 feature bit.
- */
- GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPD32);
- GET_FEATURE(ARM_FEATURE_LPAE, ARM_HWCAP_ARM_LPAE);
+ GET_FEATURE_ID(aa32_vfp, ARM_HWCAP_ARM_VFP);
+
+ if (cpu_isar_feature(aa32_fpsp_v3, cpu) ||
+ cpu_isar_feature(aa32_fpdp_v3, cpu)) {
+ hwcaps |= ARM_HWCAP_ARM_VFPv3;
+ if (cpu_isar_feature(aa32_simd_r32, cpu)) {
+ hwcaps |= ARM_HWCAP_ARM_VFPD32;
+ } else {
+ hwcaps |= ARM_HWCAP_ARM_VFPv3D16;
+ }
+ }
+ GET_FEATURE_ID(aa32_simdfmac, ARM_HWCAP_ARM_VFPv4);
return hwcaps;
}
--
2.20.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 19/33] target/arm: Remove ARM_FEATURE_VFP*
2020-02-28 16:38 [PULL 00/33] target-arm queue Peter Maydell
` (17 preceding siblings ...)
2020-02-28 16:38 ` [PULL 18/33] linux-user/arm: Replace ARM_FEATURE_VFP* tests for HWCAP Peter Maydell
@ 2020-02-28 16:38 ` Peter Maydell
2020-02-28 16:38 ` [PULL 20/33] target/arm: Add formats for some vfp 2 and 3-register insns Peter Maydell
` (14 subsequent siblings)
33 siblings, 0 replies; 57+ messages in thread
From: Peter Maydell @ 2020-02-28 16:38 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
We have converted all tests against these features
to ISAR tests.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200224222232.13807-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 3 ---
target/arm/cpu.c | 25 -------------------------
target/arm/cpu64.c | 3 ---
target/arm/kvm32.c | 5 -----
target/arm/kvm64.c | 1 -
5 files changed, 37 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index b29b0eddfc3..05aa9711cd8 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1880,7 +1880,6 @@ QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
* mapping in linux-user/elfload.c:get_elf_hwcap().
*/
enum arm_features {
- ARM_FEATURE_VFP,
ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
@@ -1889,7 +1888,6 @@ enum arm_features {
ARM_FEATURE_V7,
ARM_FEATURE_THUMB2,
ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */
- ARM_FEATURE_VFP3,
ARM_FEATURE_NEON,
ARM_FEATURE_M, /* Microcontroller profile. */
ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */
@@ -1900,7 +1898,6 @@ enum arm_features {
ARM_FEATURE_V5,
ARM_FEATURE_STRONGARM,
ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
- ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */
ARM_FEATURE_GENERIC_TIMER,
ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index dc45865c7a7..e6016e33cec 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1208,13 +1208,6 @@ void arm_cpu_post_init(Object *obj)
if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
set_feature(&cpu->env, ARM_FEATURE_PMSA);
}
- /* Similarly for the VFP feature bits */
- if (arm_feature(&cpu->env, ARM_FEATURE_VFP4)) {
- set_feature(&cpu->env, ARM_FEATURE_VFP3);
- }
- if (arm_feature(&cpu->env, ARM_FEATURE_VFP3)) {
- set_feature(&cpu->env, ARM_FEATURE_VFP);
- }
if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
@@ -1442,10 +1435,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
uint64_t t;
uint32_t u;
- unset_feature(env, ARM_FEATURE_VFP);
- unset_feature(env, ARM_FEATURE_VFP3);
- unset_feature(env, ARM_FEATURE_VFP4);
-
t = cpu->isar.id_aa64isar1;
t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0);
cpu->isar.id_aa64isar1 = t;
@@ -1865,7 +1854,6 @@ static void arm926_initfn(Object *obj)
cpu->dtb_compatible = "arm,arm926";
set_feature(&cpu->env, ARM_FEATURE_V5);
- set_feature(&cpu->env, ARM_FEATURE_VFP);
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
cpu->midr = 0x41069265;
@@ -1906,7 +1894,6 @@ static void arm1026_initfn(Object *obj)
cpu->dtb_compatible = "arm,arm1026";
set_feature(&cpu->env, ARM_FEATURE_V5);
- set_feature(&cpu->env, ARM_FEATURE_VFP);
set_feature(&cpu->env, ARM_FEATURE_AUXCR);
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
@@ -1954,7 +1941,6 @@ static void arm1136_r2_initfn(Object *obj)
cpu->dtb_compatible = "arm,arm1136";
set_feature(&cpu->env, ARM_FEATURE_V6);
- set_feature(&cpu->env, ARM_FEATURE_VFP);
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
@@ -1986,7 +1972,6 @@ static void arm1136_initfn(Object *obj)
cpu->dtb_compatible = "arm,arm1136";
set_feature(&cpu->env, ARM_FEATURE_V6K);
set_feature(&cpu->env, ARM_FEATURE_V6);
- set_feature(&cpu->env, ARM_FEATURE_VFP);
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
@@ -2017,7 +2002,6 @@ static void arm1176_initfn(Object *obj)
cpu->dtb_compatible = "arm,arm1176";
set_feature(&cpu->env, ARM_FEATURE_V6K);
- set_feature(&cpu->env, ARM_FEATURE_VFP);
set_feature(&cpu->env, ARM_FEATURE_VAPA);
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
@@ -2050,7 +2034,6 @@ static void arm11mpcore_initfn(Object *obj)
cpu->dtb_compatible = "arm,arm11mpcore";
set_feature(&cpu->env, ARM_FEATURE_V6K);
- set_feature(&cpu->env, ARM_FEATURE_VFP);
set_feature(&cpu->env, ARM_FEATURE_VAPA);
set_feature(&cpu->env, ARM_FEATURE_MPIDR);
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
@@ -2116,7 +2099,6 @@ static void cortex_m4_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_M);
set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
- set_feature(&cpu->env, ARM_FEATURE_VFP4);
cpu->midr = 0x410fc240; /* r0p0 */
cpu->pmsav7_dregion = 8;
cpu->isar.mvfr0 = 0x10110021;
@@ -2147,7 +2129,6 @@ static void cortex_m7_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_M);
set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
- set_feature(&cpu->env, ARM_FEATURE_VFP4);
cpu->midr = 0x411fc272; /* r1p2 */
cpu->pmsav7_dregion = 8;
cpu->isar.mvfr0 = 0x10110221;
@@ -2179,7 +2160,6 @@ static void cortex_m33_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
- set_feature(&cpu->env, ARM_FEATURE_VFP4);
cpu->midr = 0x410fd213; /* r0p3 */
cpu->pmsav7_dregion = 16;
cpu->sau_sregion = 8;
@@ -2263,7 +2243,6 @@ static void cortex_r5f_initfn(Object *obj)
ARMCPU *cpu = ARM_CPU(obj);
cortex_r5_initfn(obj);
- set_feature(&cpu->env, ARM_FEATURE_VFP3);
cpu->isar.mvfr0 = 0x10110221;
cpu->isar.mvfr1 = 0x00000011;
}
@@ -2282,7 +2261,6 @@ static void cortex_a8_initfn(Object *obj)
cpu->dtb_compatible = "arm,cortex-a8";
set_feature(&cpu->env, ARM_FEATURE_V7);
- set_feature(&cpu->env, ARM_FEATURE_VFP3);
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
@@ -2350,7 +2328,6 @@ static void cortex_a9_initfn(Object *obj)
cpu->dtb_compatible = "arm,cortex-a9";
set_feature(&cpu->env, ARM_FEATURE_V7);
- set_feature(&cpu->env, ARM_FEATURE_VFP3);
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
set_feature(&cpu->env, ARM_FEATURE_EL3);
@@ -2415,7 +2392,6 @@ static void cortex_a7_initfn(Object *obj)
cpu->dtb_compatible = "arm,cortex-a7";
set_feature(&cpu->env, ARM_FEATURE_V7VE);
- set_feature(&cpu->env, ARM_FEATURE_VFP4);
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
@@ -2461,7 +2437,6 @@ static void cortex_a15_initfn(Object *obj)
cpu->dtb_compatible = "arm,cortex-a15";
set_feature(&cpu->env, ARM_FEATURE_V7VE);
- set_feature(&cpu->env, ARM_FEATURE_VFP4);
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index db695384ebc..8f2a43c938a 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -102,7 +102,6 @@ static void aarch64_a57_initfn(Object *obj)
cpu->dtb_compatible = "arm,cortex-a57";
set_feature(&cpu->env, ARM_FEATURE_V8);
- set_feature(&cpu->env, ARM_FEATURE_VFP4);
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
@@ -156,7 +155,6 @@ static void aarch64_a53_initfn(Object *obj)
cpu->dtb_compatible = "arm,cortex-a53";
set_feature(&cpu->env, ARM_FEATURE_V8);
- set_feature(&cpu->env, ARM_FEATURE_VFP4);
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
@@ -210,7 +208,6 @@ static void aarch64_a72_initfn(Object *obj)
cpu->dtb_compatible = "arm,cortex-a72";
set_feature(&cpu->env, ARM_FEATURE_V8);
- set_feature(&cpu->env, ARM_FEATURE_VFP4);
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
index 7981ae3bc4e..f703c4fcad8 100644
--- a/target/arm/kvm32.c
+++ b/target/arm/kvm32.c
@@ -147,7 +147,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
* bits, but a few must be tested.
*/
set_feature(&features, ARM_FEATURE_V7VE);
- set_feature(&features, ARM_FEATURE_VFP3);
set_feature(&features, ARM_FEATURE_GENERIC_TIMER);
if (extract32(id_pfr0, 12, 4) == 1) {
@@ -156,10 +155,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
if (extract32(ahcf->isar.mvfr1, 12, 4) == 1) {
set_feature(&features, ARM_FEATURE_NEON);
}
- if (extract32(ahcf->isar.mvfr1, 28, 4) == 1) {
- /* FMAC support implies VFPv4 */
- set_feature(&features, ARM_FEATURE_VFP4);
- }
ahcf->features = features;
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index 0ad96c3500a..93ba1448daf 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -649,7 +649,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
* feature bits.
*/
set_feature(&features, ARM_FEATURE_V8);
- set_feature(&features, ARM_FEATURE_VFP4);
set_feature(&features, ARM_FEATURE_NEON);
set_feature(&features, ARM_FEATURE_AARCH64);
set_feature(&features, ARM_FEATURE_PMU);
--
2.20.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 20/33] target/arm: Add formats for some vfp 2 and 3-register insns
2020-02-28 16:38 [PULL 00/33] target-arm queue Peter Maydell
` (18 preceding siblings ...)
2020-02-28 16:38 ` [PULL 19/33] target/arm: Remove ARM_FEATURE_VFP* Peter Maydell
@ 2020-02-28 16:38 ` Peter Maydell
2020-02-28 16:38 ` [PULL 21/33] target/arm: Split VFM decode Peter Maydell
` (13 subsequent siblings)
33 siblings, 0 replies; 57+ messages in thread
From: Peter Maydell @ 2020-02-28 16:38 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Those vfp instructions without extra opcode fields can
share a common @format for brevity.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200224222232.13807-16-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/vfp.decode | 134 ++++++++++++++++--------------------------
1 file changed, 52 insertions(+), 82 deletions(-)
diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode
index 592fe9e1e42..4f294f88be5 100644
--- a/target/arm/vfp.decode
+++ b/target/arm/vfp.decode
@@ -46,6 +46,14 @@
%vmov_imm 16:4 0:4
+@vfp_dnm_s ................................ vm=%vm_sp vn=%vn_sp vd=%vd_sp
+@vfp_dnm_d ................................ vm=%vm_dp vn=%vn_dp vd=%vd_dp
+
+@vfp_dm_ss ................................ vm=%vm_sp vd=%vd_sp
+@vfp_dm_dd ................................ vm=%vm_dp vd=%vd_dp
+@vfp_dm_ds ................................ vm=%vm_sp vd=%vd_dp
+@vfp_dm_sd ................................ vm=%vm_dp vd=%vd_sp
+
# VMOV scalar to general-purpose register; note that this does
# include some Neon cases.
VMOV_to_gp ---- 1110 u:1 1. 1 .... rt:4 1011 ... 1 0000 \
@@ -66,20 +74,15 @@ VDUP ---- 1110 1 b:1 q:1 0 .... rt:4 1011 . 0 e:1 1 0000 \
vn=%vn_dp
VMSR_VMRS ---- 1110 111 l:1 reg:4 rt:4 1010 0001 0000
-VMOV_single ---- 1110 000 l:1 .... rt:4 1010 . 001 0000 \
- vn=%vn_sp
+VMOV_single ---- 1110 000 l:1 .... rt:4 1010 . 001 0000 vn=%vn_sp
-VMOV_64_sp ---- 1100 010 op:1 rt2:4 rt:4 1010 00.1 .... \
- vm=%vm_sp
-VMOV_64_dp ---- 1100 010 op:1 rt2:4 rt:4 1011 00.1 .... \
- vm=%vm_dp
+VMOV_64_sp ---- 1100 010 op:1 rt2:4 rt:4 1010 00.1 .... vm=%vm_sp
+VMOV_64_dp ---- 1100 010 op:1 rt2:4 rt:4 1011 00.1 .... vm=%vm_dp
# Note that the half-precision variants of VLDR and VSTR are
# not part of this decodetree at all because they have bits [9:8] == 0b01
-VLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8 \
- vd=%vd_sp
-VLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8 \
- vd=%vd_dp
+VLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8 vd=%vd_sp
+VLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8 vd=%vd_dp
# We split the load/store multiple up into two patterns to avoid
# overlap with other insns in the "Advanced SIMD load/store and 64-bit move"
@@ -100,50 +103,32 @@ VLDM_VSTM_dp ---- 1101 0.1 l:1 rn:4 .... 1011 imm:8 \
vd=%vd_dp p=1 u=0 w=1
# 3-register VFP data-processing; bits [23,21:20,6] identify the operation.
-VMLA_sp ---- 1110 0.00 .... .... 1010 .0.0 .... \
- vm=%vm_sp vn=%vn_sp vd=%vd_sp
-VMLA_dp ---- 1110 0.00 .... .... 1011 .0.0 .... \
- vm=%vm_dp vn=%vn_dp vd=%vd_dp
+VMLA_sp ---- 1110 0.00 .... .... 1010 .0.0 .... @vfp_dnm_s
+VMLA_dp ---- 1110 0.00 .... .... 1011 .0.0 .... @vfp_dnm_d
-VMLS_sp ---- 1110 0.00 .... .... 1010 .1.0 .... \
- vm=%vm_sp vn=%vn_sp vd=%vd_sp
-VMLS_dp ---- 1110 0.00 .... .... 1011 .1.0 .... \
- vm=%vm_dp vn=%vn_dp vd=%vd_dp
+VMLS_sp ---- 1110 0.00 .... .... 1010 .1.0 .... @vfp_dnm_s
+VMLS_dp ---- 1110 0.00 .... .... 1011 .1.0 .... @vfp_dnm_d
-VNMLS_sp ---- 1110 0.01 .... .... 1010 .0.0 .... \
- vm=%vm_sp vn=%vn_sp vd=%vd_sp
-VNMLS_dp ---- 1110 0.01 .... .... 1011 .0.0 .... \
- vm=%vm_dp vn=%vn_dp vd=%vd_dp
+VNMLS_sp ---- 1110 0.01 .... .... 1010 .0.0 .... @vfp_dnm_s
+VNMLS_dp ---- 1110 0.01 .... .... 1011 .0.0 .... @vfp_dnm_d
-VNMLA_sp ---- 1110 0.01 .... .... 1010 .1.0 .... \
- vm=%vm_sp vn=%vn_sp vd=%vd_sp
-VNMLA_dp ---- 1110 0.01 .... .... 1011 .1.0 .... \
- vm=%vm_dp vn=%vn_dp vd=%vd_dp
+VNMLA_sp ---- 1110 0.01 .... .... 1010 .1.0 .... @vfp_dnm_s
+VNMLA_dp ---- 1110 0.01 .... .... 1011 .1.0 .... @vfp_dnm_d
-VMUL_sp ---- 1110 0.10 .... .... 1010 .0.0 .... \
- vm=%vm_sp vn=%vn_sp vd=%vd_sp
-VMUL_dp ---- 1110 0.10 .... .... 1011 .0.0 .... \
- vm=%vm_dp vn=%vn_dp vd=%vd_dp
+VMUL_sp ---- 1110 0.10 .... .... 1010 .0.0 .... @vfp_dnm_s
+VMUL_dp ---- 1110 0.10 .... .... 1011 .0.0 .... @vfp_dnm_d
-VNMUL_sp ---- 1110 0.10 .... .... 1010 .1.0 .... \
- vm=%vm_sp vn=%vn_sp vd=%vd_sp
-VNMUL_dp ---- 1110 0.10 .... .... 1011 .1.0 .... \
- vm=%vm_dp vn=%vn_dp vd=%vd_dp
+VNMUL_sp ---- 1110 0.10 .... .... 1010 .1.0 .... @vfp_dnm_s
+VNMUL_dp ---- 1110 0.10 .... .... 1011 .1.0 .... @vfp_dnm_d
-VADD_sp ---- 1110 0.11 .... .... 1010 .0.0 .... \
- vm=%vm_sp vn=%vn_sp vd=%vd_sp
-VADD_dp ---- 1110 0.11 .... .... 1011 .0.0 .... \
- vm=%vm_dp vn=%vn_dp vd=%vd_dp
+VADD_sp ---- 1110 0.11 .... .... 1010 .0.0 .... @vfp_dnm_s
+VADD_dp ---- 1110 0.11 .... .... 1011 .0.0 .... @vfp_dnm_d
-VSUB_sp ---- 1110 0.11 .... .... 1010 .1.0 .... \
- vm=%vm_sp vn=%vn_sp vd=%vd_sp
-VSUB_dp ---- 1110 0.11 .... .... 1011 .1.0 .... \
- vm=%vm_dp vn=%vn_dp vd=%vd_dp
+VSUB_sp ---- 1110 0.11 .... .... 1010 .1.0 .... @vfp_dnm_s
+VSUB_dp ---- 1110 0.11 .... .... 1011 .1.0 .... @vfp_dnm_d
-VDIV_sp ---- 1110 1.00 .... .... 1010 .0.0 .... \
- vm=%vm_sp vn=%vn_sp vd=%vd_sp
-VDIV_dp ---- 1110 1.00 .... .... 1011 .0.0 .... \
- vm=%vm_dp vn=%vn_dp vd=%vd_dp
+VDIV_sp ---- 1110 1.00 .... .... 1010 .0.0 .... @vfp_dnm_s
+VDIV_dp ---- 1110 1.00 .... .... 1011 .0.0 .... @vfp_dnm_d
VFM_sp ---- 1110 1.01 .... .... 1010 . o2:1 . 0 .... \
vm=%vm_sp vn=%vn_sp vd=%vd_sp o1=1
@@ -159,25 +144,17 @@ VMOV_imm_sp ---- 1110 1.11 .... .... 1010 0000 .... \
VMOV_imm_dp ---- 1110 1.11 .... .... 1011 0000 .... \
vd=%vd_dp imm=%vmov_imm
-VMOV_reg_sp ---- 1110 1.11 0000 .... 1010 01.0 .... \
- vd=%vd_sp vm=%vm_sp
-VMOV_reg_dp ---- 1110 1.11 0000 .... 1011 01.0 .... \
- vd=%vd_dp vm=%vm_dp
+VMOV_reg_sp ---- 1110 1.11 0000 .... 1010 01.0 .... @vfp_dm_ss
+VMOV_reg_dp ---- 1110 1.11 0000 .... 1011 01.0 .... @vfp_dm_dd
-VABS_sp ---- 1110 1.11 0000 .... 1010 11.0 .... \
- vd=%vd_sp vm=%vm_sp
-VABS_dp ---- 1110 1.11 0000 .... 1011 11.0 .... \
- vd=%vd_dp vm=%vm_dp
+VABS_sp ---- 1110 1.11 0000 .... 1010 11.0 .... @vfp_dm_ss
+VABS_dp ---- 1110 1.11 0000 .... 1011 11.0 .... @vfp_dm_dd
-VNEG_sp ---- 1110 1.11 0001 .... 1010 01.0 .... \
- vd=%vd_sp vm=%vm_sp
-VNEG_dp ---- 1110 1.11 0001 .... 1011 01.0 .... \
- vd=%vd_dp vm=%vm_dp
+VNEG_sp ---- 1110 1.11 0001 .... 1010 01.0 .... @vfp_dm_ss
+VNEG_dp ---- 1110 1.11 0001 .... 1011 01.0 .... @vfp_dm_dd
-VSQRT_sp ---- 1110 1.11 0001 .... 1010 11.0 .... \
- vd=%vd_sp vm=%vm_sp
-VSQRT_dp ---- 1110 1.11 0001 .... 1011 11.0 .... \
- vd=%vd_dp vm=%vm_dp
+VSQRT_sp ---- 1110 1.11 0001 .... 1010 11.0 .... @vfp_dm_ss
+VSQRT_dp ---- 1110 1.11 0001 .... 1011 11.0 .... @vfp_dm_dd
VCMP_sp ---- 1110 1.11 010 z:1 .... 1010 e:1 1.0 .... \
vd=%vd_sp vm=%vm_sp
@@ -190,32 +167,26 @@ VCVT_f32_f16 ---- 1110 1.11 0010 .... 1010 t:1 1.0 .... \
VCVT_f64_f16 ---- 1110 1.11 0010 .... 1011 t:1 1.0 .... \
vd=%vd_dp vm=%vm_sp
-# VCVTB and VCVTT to f16: Vd format is always vd_sp; Vm format depends on size bit
+# VCVTB and VCVTT to f16: Vd format is always vd_sp;
+# Vm format depends on size bit
VCVT_f16_f32 ---- 1110 1.11 0011 .... 1010 t:1 1.0 .... \
vd=%vd_sp vm=%vm_sp
VCVT_f16_f64 ---- 1110 1.11 0011 .... 1011 t:1 1.0 .... \
vd=%vd_sp vm=%vm_dp
-VRINTR_sp ---- 1110 1.11 0110 .... 1010 01.0 .... \
- vd=%vd_sp vm=%vm_sp
-VRINTR_dp ---- 1110 1.11 0110 .... 1011 01.0 .... \
- vd=%vd_dp vm=%vm_dp
+VRINTR_sp ---- 1110 1.11 0110 .... 1010 01.0 .... @vfp_dm_ss
+VRINTR_dp ---- 1110 1.11 0110 .... 1011 01.0 .... @vfp_dm_dd
-VRINTZ_sp ---- 1110 1.11 0110 .... 1010 11.0 .... \
- vd=%vd_sp vm=%vm_sp
-VRINTZ_dp ---- 1110 1.11 0110 .... 1011 11.0 .... \
- vd=%vd_dp vm=%vm_dp
+VRINTZ_sp ---- 1110 1.11 0110 .... 1010 11.0 .... @vfp_dm_ss
+VRINTZ_dp ---- 1110 1.11 0110 .... 1011 11.0 .... @vfp_dm_dd
-VRINTX_sp ---- 1110 1.11 0111 .... 1010 01.0 .... \
- vd=%vd_sp vm=%vm_sp
-VRINTX_dp ---- 1110 1.11 0111 .... 1011 01.0 .... \
- vd=%vd_dp vm=%vm_dp
+VRINTX_sp ---- 1110 1.11 0111 .... 1010 01.0 .... @vfp_dm_ss
+VRINTX_dp ---- 1110 1.11 0111 .... 1011 01.0 .... @vfp_dm_dd
-# VCVT between single and double: Vm precision depends on size; Vd is its reverse
-VCVT_sp ---- 1110 1.11 0111 .... 1010 11.0 .... \
- vd=%vd_dp vm=%vm_sp
-VCVT_dp ---- 1110 1.11 0111 .... 1011 11.0 .... \
- vd=%vd_sp vm=%vm_dp
+# VCVT between single and double:
+# Vm precision depends on size; Vd is its reverse
+VCVT_sp ---- 1110 1.11 0111 .... 1010 11.0 .... @vfp_dm_ds
+VCVT_dp ---- 1110 1.11 0111 .... 1011 11.0 .... @vfp_dm_sd
# VCVT from integer to floating point: Vm always single; Vd depends on size
VCVT_int_sp ---- 1110 1.11 1000 .... 1010 s:1 1.0 .... \
@@ -224,8 +195,7 @@ VCVT_int_dp ---- 1110 1.11 1000 .... 1011 s:1 1.0 .... \
vd=%vd_dp vm=%vm_sp
# VJCVT is always dp to sp
-VJCVT ---- 1110 1.11 1001 .... 1011 11.0 .... \
- vd=%vd_sp vm=%vm_dp
+VJCVT ---- 1110 1.11 1001 .... 1011 11.0 .... @vfp_dm_sd
# VCVT between floating-point and fixed-point. The immediate value
# is in the same format as a Vm single-precision register number.
--
2.20.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 21/33] target/arm: Split VFM decode
2020-02-28 16:38 [PULL 00/33] target-arm queue Peter Maydell
` (19 preceding siblings ...)
2020-02-28 16:38 ` [PULL 20/33] target/arm: Add formats for some vfp 2 and 3-register insns Peter Maydell
@ 2020-02-28 16:38 ` Peter Maydell
2020-02-28 16:38 ` [PULL 22/33] target/arm: Split VMINMAXNM decode Peter Maydell
` (12 subsequent siblings)
33 siblings, 0 replies; 57+ messages in thread
From: Peter Maydell @ 2020-02-28 16:38 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Passing the raw o1 and o2 fields from the manual is less
instructive than it might be. Do the full decode and let
the trans_* functions pass in booleans to a helper.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200224222232.13807-17-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate-vfp.inc.c | 52 ++++++++++++++++++++++++++++++----
target/arm/vfp.decode | 17 +++++------
2 files changed, 55 insertions(+), 14 deletions(-)
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index 1964af3ea5e..41aa67c133a 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -1784,7 +1784,7 @@ static bool trans_VDIV_dp(DisasContext *s, arg_VDIV_dp *a)
return do_vfp_3op_dp(s, gen_helper_vfp_divd, a->vd, a->vn, a->vm, false);
}
-static bool trans_VFM_sp(DisasContext *s, arg_VFM_sp *a)
+static bool do_vfm_sp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool neg_d)
{
/*
* VFNMA : fd = muladd(-fd, fn, fm)
@@ -1828,12 +1828,12 @@ static bool trans_VFM_sp(DisasContext *s, arg_VFM_sp *a)
neon_load_reg32(vn, a->vn);
neon_load_reg32(vm, a->vm);
- if (a->o2) {
+ if (neg_n) {
/* VFNMS, VFMS */
gen_helper_vfp_negs(vn, vn);
}
neon_load_reg32(vd, a->vd);
- if (a->o1 & 1) {
+ if (neg_d) {
/* VFNMA, VFNMS */
gen_helper_vfp_negs(vd, vd);
}
@@ -1849,7 +1849,27 @@ static bool trans_VFM_sp(DisasContext *s, arg_VFM_sp *a)
return true;
}
-static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a)
+static bool trans_VFMA_sp(DisasContext *s, arg_VFMA_sp *a)
+{
+ return do_vfm_sp(s, a, false, false);
+}
+
+static bool trans_VFMS_sp(DisasContext *s, arg_VFMS_sp *a)
+{
+ return do_vfm_sp(s, a, true, false);
+}
+
+static bool trans_VFNMA_sp(DisasContext *s, arg_VFNMA_sp *a)
+{
+ return do_vfm_sp(s, a, false, true);
+}
+
+static bool trans_VFNMS_sp(DisasContext *s, arg_VFNMS_sp *a)
+{
+ return do_vfm_sp(s, a, true, true);
+}
+
+static bool do_vfm_dp(DisasContext *s, arg_VFMA_dp *a, bool neg_n, bool neg_d)
{
/*
* VFNMA : fd = muladd(-fd, fn, fm)
@@ -1905,12 +1925,12 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a)
neon_load_reg64(vn, a->vn);
neon_load_reg64(vm, a->vm);
- if (a->o2) {
+ if (neg_n) {
/* VFNMS, VFMS */
gen_helper_vfp_negd(vn, vn);
}
neon_load_reg64(vd, a->vd);
- if (a->o1 & 1) {
+ if (neg_d) {
/* VFNMA, VFNMS */
gen_helper_vfp_negd(vd, vd);
}
@@ -1926,6 +1946,26 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a)
return true;
}
+static bool trans_VFMA_dp(DisasContext *s, arg_VFMA_dp *a)
+{
+ return do_vfm_dp(s, a, false, false);
+}
+
+static bool trans_VFMS_dp(DisasContext *s, arg_VFMS_dp *a)
+{
+ return do_vfm_dp(s, a, true, false);
+}
+
+static bool trans_VFNMA_dp(DisasContext *s, arg_VFNMA_dp *a)
+{
+ return do_vfm_dp(s, a, false, true);
+}
+
+static bool trans_VFNMS_dp(DisasContext *s, arg_VFNMS_dp *a)
+{
+ return do_vfm_dp(s, a, true, true);
+}
+
static bool trans_VMOV_imm_sp(DisasContext *s, arg_VMOV_imm_sp *a)
{
uint32_t delta_d = 0;
diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode
index 4f294f88be5..5fd70f975ae 100644
--- a/target/arm/vfp.decode
+++ b/target/arm/vfp.decode
@@ -130,14 +130,15 @@ VSUB_dp ---- 1110 0.11 .... .... 1011 .1.0 .... @vfp_dnm_d
VDIV_sp ---- 1110 1.00 .... .... 1010 .0.0 .... @vfp_dnm_s
VDIV_dp ---- 1110 1.00 .... .... 1011 .0.0 .... @vfp_dnm_d
-VFM_sp ---- 1110 1.01 .... .... 1010 . o2:1 . 0 .... \
- vm=%vm_sp vn=%vn_sp vd=%vd_sp o1=1
-VFM_dp ---- 1110 1.01 .... .... 1011 . o2:1 . 0 .... \
- vm=%vm_dp vn=%vn_dp vd=%vd_dp o1=1
-VFM_sp ---- 1110 1.10 .... .... 1010 . o2:1 . 0 .... \
- vm=%vm_sp vn=%vn_sp vd=%vd_sp o1=2
-VFM_dp ---- 1110 1.10 .... .... 1011 . o2:1 . 0 .... \
- vm=%vm_dp vn=%vn_dp vd=%vd_dp o1=2
+VFMA_sp ---- 1110 1.10 .... .... 1010 .0. 0 .... @vfp_dnm_s
+VFMS_sp ---- 1110 1.10 .... .... 1010 .1. 0 .... @vfp_dnm_s
+VFNMA_sp ---- 1110 1.01 .... .... 1010 .0. 0 .... @vfp_dnm_s
+VFNMS_sp ---- 1110 1.01 .... .... 1010 .1. 0 .... @vfp_dnm_s
+
+VFMA_dp ---- 1110 1.10 .... .... 1011 .0.0 .... @vfp_dnm_d
+VFMS_dp ---- 1110 1.10 .... .... 1011 .1.0 .... @vfp_dnm_d
+VFNMA_dp ---- 1110 1.01 .... .... 1011 .0.0 .... @vfp_dnm_d
+VFNMS_dp ---- 1110 1.01 .... .... 1011 .1.0 .... @vfp_dnm_d
VMOV_imm_sp ---- 1110 1.11 .... .... 1010 0000 .... \
vd=%vd_sp imm=%vmov_imm
--
2.20.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 22/33] target/arm: Split VMINMAXNM decode
2020-02-28 16:38 [PULL 00/33] target-arm queue Peter Maydell
` (20 preceding siblings ...)
2020-02-28 16:38 ` [PULL 21/33] target/arm: Split VFM decode Peter Maydell
@ 2020-02-28 16:38 ` Peter Maydell
2020-02-28 16:38 ` [PULL 23/33] hw/arm/xilinx_zynq: Fix USB port instantiation Peter Maydell
` (11 subsequent siblings)
33 siblings, 0 replies; 57+ messages in thread
From: Peter Maydell @ 2020-02-28 16:38 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Passing the raw op field from the manual is less instructive
than it might be. Do the full decode and use the existing
helpers to perform the expansion.
Since these are v8 insns, VECLEN+VECSTRIDE are already RES0.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200224222232.13807-18-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate-vfp.inc.c | 109 +++++++++++----------------------
target/arm/vfp-uncond.decode | 12 ++--
2 files changed, 44 insertions(+), 77 deletions(-)
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index 41aa67c133a..b087bbd812e 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -322,79 +322,6 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
return true;
}
-static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a)
-{
- uint32_t rd, rn, rm;
- bool dp = a->dp;
- bool vmin = a->op;
- TCGv_ptr fpst;
-
- if (!dc_isar_feature(aa32_vminmaxnm, s)) {
- return false;
- }
-
- if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
- return false;
- }
-
- /* UNDEF accesses to D16-D31 if they don't exist */
- if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
- ((a->vm | a->vn | a->vd) & 0x10)) {
- return false;
- }
-
- rd = a->vd;
- rn = a->vn;
- rm = a->vm;
-
- if (!vfp_access_check(s)) {
- return true;
- }
-
- fpst = get_fpstatus_ptr(0);
-
- if (dp) {
- TCGv_i64 frn, frm, dest;
-
- frn = tcg_temp_new_i64();
- frm = tcg_temp_new_i64();
- dest = tcg_temp_new_i64();
-
- neon_load_reg64(frn, rn);
- neon_load_reg64(frm, rm);
- if (vmin) {
- gen_helper_vfp_minnumd(dest, frn, frm, fpst);
- } else {
- gen_helper_vfp_maxnumd(dest, frn, frm, fpst);
- }
- neon_store_reg64(dest, rd);
- tcg_temp_free_i64(frn);
- tcg_temp_free_i64(frm);
- tcg_temp_free_i64(dest);
- } else {
- TCGv_i32 frn, frm, dest;
-
- frn = tcg_temp_new_i32();
- frm = tcg_temp_new_i32();
- dest = tcg_temp_new_i32();
-
- neon_load_reg32(frn, rn);
- neon_load_reg32(frm, rm);
- if (vmin) {
- gen_helper_vfp_minnums(dest, frn, frm, fpst);
- } else {
- gen_helper_vfp_maxnums(dest, frn, frm, fpst);
- }
- neon_store_reg32(dest, rd);
- tcg_temp_free_i32(frn);
- tcg_temp_free_i32(frm);
- tcg_temp_free_i32(dest);
- }
-
- tcg_temp_free_ptr(fpst);
- return true;
-}
-
/*
* Table for converting the most common AArch32 encoding of
* rounding mode to arm_fprounding order (which matches the
@@ -1784,6 +1711,42 @@ static bool trans_VDIV_dp(DisasContext *s, arg_VDIV_dp *a)
return do_vfp_3op_dp(s, gen_helper_vfp_divd, a->vd, a->vn, a->vm, false);
}
+static bool trans_VMINNM_sp(DisasContext *s, arg_VMINNM_sp *a)
+{
+ if (!dc_isar_feature(aa32_vminmaxnm, s)) {
+ return false;
+ }
+ return do_vfp_3op_sp(s, gen_helper_vfp_minnums,
+ a->vd, a->vn, a->vm, false);
+}
+
+static bool trans_VMAXNM_sp(DisasContext *s, arg_VMAXNM_sp *a)
+{
+ if (!dc_isar_feature(aa32_vminmaxnm, s)) {
+ return false;
+ }
+ return do_vfp_3op_sp(s, gen_helper_vfp_maxnums,
+ a->vd, a->vn, a->vm, false);
+}
+
+static bool trans_VMINNM_dp(DisasContext *s, arg_VMINNM_dp *a)
+{
+ if (!dc_isar_feature(aa32_vminmaxnm, s)) {
+ return false;
+ }
+ return do_vfp_3op_dp(s, gen_helper_vfp_minnumd,
+ a->vd, a->vn, a->vm, false);
+}
+
+static bool trans_VMAXNM_dp(DisasContext *s, arg_VMAXNM_dp *a)
+{
+ if (!dc_isar_feature(aa32_vminmaxnm, s)) {
+ return false;
+ }
+ return do_vfp_3op_dp(s, gen_helper_vfp_maxnumd,
+ a->vd, a->vn, a->vm, false);
+}
+
static bool do_vfm_sp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool neg_d)
{
/*
diff --git a/target/arm/vfp-uncond.decode b/target/arm/vfp-uncond.decode
index 5af1f2ee664..34ca164266f 100644
--- a/target/arm/vfp-uncond.decode
+++ b/target/arm/vfp-uncond.decode
@@ -41,15 +41,19 @@
%vd_dp 22:1 12:4
%vd_sp 12:4 22:1
+@vfp_dnm_s ................................ vm=%vm_sp vn=%vn_sp vd=%vd_sp
+@vfp_dnm_d ................................ vm=%vm_dp vn=%vn_dp vd=%vd_dp
+
VSEL 1111 1110 0. cc:2 .... .... 1010 .0.0 .... \
vm=%vm_sp vn=%vn_sp vd=%vd_sp dp=0
VSEL 1111 1110 0. cc:2 .... .... 1011 .0.0 .... \
vm=%vm_dp vn=%vn_dp vd=%vd_dp dp=1
-VMINMAXNM 1111 1110 1.00 .... .... 1010 . op:1 .0 .... \
- vm=%vm_sp vn=%vn_sp vd=%vd_sp dp=0
-VMINMAXNM 1111 1110 1.00 .... .... 1011 . op:1 .0 .... \
- vm=%vm_dp vn=%vn_dp vd=%vd_dp dp=1
+VMAXNM_sp 1111 1110 1.00 .... .... 1010 .0.0 .... @vfp_dnm_s
+VMINNM_sp 1111 1110 1.00 .... .... 1010 .1.0 .... @vfp_dnm_s
+
+VMAXNM_dp 1111 1110 1.00 .... .... 1011 .0.0 .... @vfp_dnm_d
+VMINNM_dp 1111 1110 1.00 .... .... 1011 .1.0 .... @vfp_dnm_d
VRINT 1111 1110 1.11 10 rm:2 .... 1010 01.0 .... \
vm=%vm_sp vd=%vd_sp dp=0
--
2.20.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 23/33] hw/arm/xilinx_zynq: Fix USB port instantiation
2020-02-28 16:38 [PULL 00/33] target-arm queue Peter Maydell
` (21 preceding siblings ...)
2020-02-28 16:38 ` [PULL 22/33] target/arm: Split VMINMAXNM decode Peter Maydell
@ 2020-02-28 16:38 ` Peter Maydell
2021-05-19 17:50 ` Philippe Mathieu-Daudé
2020-02-28 16:38 ` [PULL 24/33] hw/usb/hcd-ehci-sysbus: Remove obsolete xlnx, ps7-usb class Peter Maydell
` (10 subsequent siblings)
33 siblings, 1 reply; 57+ messages in thread
From: Peter Maydell @ 2020-02-28 16:38 UTC (permalink / raw)
To: qemu-devel
From: Guenter Roeck <linux@roeck-us.net>
USB ports on Xilinx Zync must be instantiated as TYPE_CHIPIDEA to work.
Linux expects and checks various chipidea registers, which do not exist
with the basic ehci emulation. This patch series fixes the problem.
Without this patch, USB ports fail to instantiate under Linux.
ci_hdrc ci_hdrc.0: doesn't support host
ci_hdrc ci_hdrc.0: no supported roles
With this patch, USB ports are instantiated, and it is possible
to boot from USB drive.
ci_hdrc ci_hdrc.0: EHCI Host Controller
ci_hdrc ci_hdrc.0: new USB bus registered, assigned bus number 1
ci_hdrc ci_hdrc.0: USB 2.0 started, EHCI 1.00
usb 1-1: new full-speed USB device number 2 using ci_hdrc
usb 1-1: not running at top speed; connect to a high speed hub
usb 1-1: config 1 interface 0 altsetting 0 endpoint 0x81 has invalid maxpacket 512, setting to 64
usb 1-1: config 1 interface 0 altsetting 0 endpoint 0x2 has invalid maxpacket 512, setting to 64
usb-storage 1-1:1.0: USB Mass Storage device detected
scsi host0: usb-storage 1-1:1.0
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id: 20200215122354.13706-2-linux@roeck-us.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/xilinx_zynq.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index 3d439a45d57..571cdcd599e 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -29,6 +29,7 @@
#include "hw/loader.h"
#include "hw/misc/zynq-xadc.h"
#include "hw/ssi/ssi.h"
+#include "hw/usb/chipidea.h"
#include "qemu/error-report.h"
#include "hw/sd/sdhci.h"
#include "hw/char/cadence_uart.h"
@@ -225,8 +226,8 @@ static void zynq_init(MachineState *machine)
zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false);
zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true);
- sysbus_create_simple("xlnx,ps7-usb", 0xE0002000, pic[53-IRQ_OFFSET]);
- sysbus_create_simple("xlnx,ps7-usb", 0xE0003000, pic[76-IRQ_OFFSET]);
+ sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - IRQ_OFFSET]);
+ sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - IRQ_OFFSET]);
cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hd(0));
cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hd(1));
--
2.20.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* Re: [PULL 23/33] hw/arm/xilinx_zynq: Fix USB port instantiation
2020-02-28 16:38 ` [PULL 23/33] hw/arm/xilinx_zynq: Fix USB port instantiation Peter Maydell
@ 2021-05-19 17:50 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 57+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-05-19 17:50 UTC (permalink / raw)
To: qemu-devel, Guenter Roeck; +Cc: Peter Maydell, Gerd Hoffmann
On 2/28/20 5:38 PM, Peter Maydell wrote:
> From: Guenter Roeck <linux@roeck-us.net>
>
> USB ports on Xilinx Zync must be instantiated as TYPE_CHIPIDEA to work.
> Linux expects and checks various chipidea registers, which do not exist
> with the basic ehci emulation. This patch series fixes the problem.
>
> Without this patch, USB ports fail to instantiate under Linux.
>
> ci_hdrc ci_hdrc.0: doesn't support host
> ci_hdrc ci_hdrc.0: no supported roles
>
> With this patch, USB ports are instantiated, and it is possible
> to boot from USB drive.
>
> ci_hdrc ci_hdrc.0: EHCI Host Controller
> ci_hdrc ci_hdrc.0: new USB bus registered, assigned bus number 1
> ci_hdrc ci_hdrc.0: USB 2.0 started, EHCI 1.00
> usb 1-1: new full-speed USB device number 2 using ci_hdrc
> usb 1-1: not running at top speed; connect to a high speed hub
> usb 1-1: config 1 interface 0 altsetting 0 endpoint 0x81 has invalid maxpacket 512, setting to 64
> usb 1-1: config 1 interface 0 altsetting 0 endpoint 0x2 has invalid maxpacket 512, setting to 64
> usb-storage 1-1:1.0: USB Mass Storage device detected
> scsi host0: usb-storage 1-1:1.0
>
> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
> Message-id: 20200215122354.13706-2-linux@roeck-us.net
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> hw/arm/xilinx_zynq.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
> index 3d439a45d57..571cdcd599e 100644
> --- a/hw/arm/xilinx_zynq.c
> +++ b/hw/arm/xilinx_zynq.c
> @@ -29,6 +29,7 @@
> #include "hw/loader.h"
> #include "hw/misc/zynq-xadc.h"
> #include "hw/ssi/ssi.h"
> +#include "hw/usb/chipidea.h"
> #include "qemu/error-report.h"
> #include "hw/sd/sdhci.h"
> #include "hw/char/cadence_uart.h"
> @@ -225,8 +226,8 @@ static void zynq_init(MachineState *machine)
> zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false);
> zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true);
>
> - sysbus_create_simple("xlnx,ps7-usb", 0xE0002000, pic[53-IRQ_OFFSET]);
> - sysbus_create_simple("xlnx,ps7-usb", 0xE0003000, pic[76-IRQ_OFFSET]);
> + sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - IRQ_OFFSET]);
> + sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - IRQ_OFFSET]);
FYI this patch makes the xilinx-zynq-a9 crash when built with
--without-default-devices:
./qemu-system-arm -M xilinx-zynq-a9
**
ERROR:qom/object.c:714:object_new_with_type: assertion failed: (type !=
NULL)
Bail out! ERROR:qom/object.c:714:object_new_with_type: assertion failed:
(type != NULL)
(gdb) bt
#0 0x00007ffff52dd7d5 in raise () at /lib64/libc.so.6
#1 0x00007ffff52c6895 in abort () at /lib64/libc.so.6
#2 0x00007ffff6dc4b6c in g_assertion_message_expr.cold () at
/lib64/libglib-2.0.so.0
#3 0x00007ffff6e229ff in g_assertion_message_expr () at
/lib64/libglib-2.0.so.0
#4 0x00005555558d3f01 in object_new_with_type (type=<optimized out>) at
qom/object.c:714
#5 0x00005555558d3f59 in object_new
(typename=typename@entry=0x555555ad4545 "usb-chipidea") at qom/object.c:747
#6 0x00005555558cd526 in qdev_new (name=name@entry=0x555555ad4545
"usb-chipidea") at hw/core/qdev.c:153
#7 0x0000555555739fc6 in sysbus_create_varargs
(name=name@entry=0x555555ad4545 "usb-chipidea",
addr=addr@entry=3758104576) at hw/core/sysbus.c:234
#8 0x0000555555796b57 in sysbus_create_simple (irq=<optimized out>,
addr=3758104576, name=0x555555ad4545 "usb-chipidea") at
/home/phil/source/qemu/include/hw/sysbus.h:104
#9 zynq_init (machine=0x555555de07a0) at hw/arm/xilinx_zynq.c:254
#10 0x000055555573707c in machine_run_board_init
(machine=machine@entry=0x555555de07a0) at hw/core/machine.c:1238
#11 0x0000555555838cff in qemu_init_board () at softmmu/vl.c:2513
#12 qmp_x_exit_preconfig (errp=<optimized out>) at softmmu/vl.c:2587
#13 0x000055555583cbfb in qmp_x_exit_preconfig (errp=<optimized out>) at
softmmu/vl.c:3609
#14 qemu_init (argc=<optimized out>, argv=<optimized out>,
envp=<optimized out>) at softmmu/vl.c:3609
#15 0x0000555555684749 in main (argc=<optimized out>, argv=<optimized
out>, envp=<optimized out>) at softmmu/main.c:49
This is because TYPE_CHIPIDEA is only built when an IMX machine is
selected:
softmmu_ss.add(when: 'CONFIG_IMX', if_true: files('chipidea.c'))
I'll send a fix later.
^ permalink raw reply [flat|nested] 57+ messages in thread
* [PULL 24/33] hw/usb/hcd-ehci-sysbus: Remove obsolete xlnx, ps7-usb class
2020-02-28 16:38 [PULL 00/33] target-arm queue Peter Maydell
` (22 preceding siblings ...)
2020-02-28 16:38 ` [PULL 23/33] hw/arm/xilinx_zynq: Fix USB port instantiation Peter Maydell
@ 2020-02-28 16:38 ` Peter Maydell
2020-02-28 16:38 ` [PULL 25/33] tests/acceptance: Add a test for the N800 and N810 arm machines Peter Maydell
` (9 subsequent siblings)
33 siblings, 0 replies; 57+ messages in thread
From: Peter Maydell @ 2020-02-28 16:38 UTC (permalink / raw)
To: qemu-devel
From: Guenter Roeck <linux@roeck-us.net>
Xilinx USB devices are now instantiated through TYPE_CHIPIDEA,
and xlnx support in the EHCI code is no longer needed.
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id: 20200215122354.13706-3-linux@roeck-us.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/usb/hcd-ehci-sysbus.c | 17 -----------------
1 file changed, 17 deletions(-)
diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c
index b22fb258be7..5b7991cffe4 100644
--- a/hw/usb/hcd-ehci-sysbus.c
+++ b/hw/usb/hcd-ehci-sysbus.c
@@ -115,22 +115,6 @@ static const TypeInfo ehci_platform_type_info = {
.class_init = ehci_platform_class_init,
};
-static void ehci_xlnx_class_init(ObjectClass *oc, void *data)
-{
- SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
- DeviceClass *dc = DEVICE_CLASS(oc);
-
- set_bit(DEVICE_CATEGORY_USB, dc->categories);
- sec->capsbase = 0x100;
- sec->opregbase = 0x140;
-}
-
-static const TypeInfo ehci_xlnx_type_info = {
- .name = "xlnx,ps7-usb",
- .parent = TYPE_SYS_BUS_EHCI,
- .class_init = ehci_xlnx_class_init,
-};
-
static void ehci_exynos4210_class_init(ObjectClass *oc, void *data)
{
SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
@@ -267,7 +251,6 @@ static void ehci_sysbus_register_types(void)
{
type_register_static(&ehci_type_info);
type_register_static(&ehci_platform_type_info);
- type_register_static(&ehci_xlnx_type_info);
type_register_static(&ehci_exynos4210_type_info);
type_register_static(&ehci_tegra2_type_info);
type_register_static(&ehci_ppc4xx_type_info);
--
2.20.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 25/33] tests/acceptance: Add a test for the N800 and N810 arm machines
2020-02-28 16:38 [PULL 00/33] target-arm queue Peter Maydell
` (23 preceding siblings ...)
2020-02-28 16:38 ` [PULL 24/33] hw/usb/hcd-ehci-sysbus: Remove obsolete xlnx, ps7-usb class Peter Maydell
@ 2020-02-28 16:38 ` Peter Maydell
2020-10-17 17:51 ` Philippe Mathieu-Daudé
2020-02-28 16:38 ` [PULL 26/33] tests/acceptance: Add a test for the integratorcp arm machine Peter Maydell
` (8 subsequent siblings)
33 siblings, 1 reply; 57+ messages in thread
From: Peter Maydell @ 2020-02-28 16:38 UTC (permalink / raw)
To: qemu-devel
From: Thomas Huth <thuth@redhat.com>
Old kernels from the Meego project can be used to check that Linux
is at least starting on these machines.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200225172501.29609-2-philmd@redhat.com
Message-Id: <20200129131920.22302-1-thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
MAINTAINERS | 1 +
tests/acceptance/machine_arm_n8x0.py | 49 ++++++++++++++++++++++++++++
2 files changed, 50 insertions(+)
create mode 100644 tests/acceptance/machine_arm_n8x0.py
diff --git a/MAINTAINERS b/MAINTAINERS
index b66c46dcb9f..264374adbe8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -686,6 +686,7 @@ F: hw/rtc/twl92230.c
F: include/hw/display/blizzard.h
F: include/hw/input/tsc2xxx.h
F: include/hw/misc/cbus.h
+F: tests/acceptance/machine_arm_n8x0.py
Palm
M: Andrzej Zaborowski <balrogg@gmail.com>
diff --git a/tests/acceptance/machine_arm_n8x0.py b/tests/acceptance/machine_arm_n8x0.py
new file mode 100644
index 00000000000..e5741f2d8d1
--- /dev/null
+++ b/tests/acceptance/machine_arm_n8x0.py
@@ -0,0 +1,49 @@
+# Functional test that boots a Linux kernel and checks the console
+#
+# Copyright (c) 2020 Red Hat, Inc.
+#
+# Author:
+# Thomas Huth <thuth@redhat.com>
+#
+# This work is licensed under the terms of the GNU GPL, version 2 or
+# later. See the COPYING file in the top-level directory.
+
+import os
+
+from avocado import skipUnless
+from avocado_qemu import Test
+from avocado_qemu import wait_for_console_pattern
+
+class N8x0Machine(Test):
+ """Boots the Linux kernel and checks that the console is operational"""
+
+ timeout = 90
+
+ def __do_test_n8x0(self):
+ kernel_url = ('http://stskeeps.subnetmask.net/meego-n8x0/'
+ 'meego-arm-n8x0-1.0.80.20100712.1431-'
+ 'vmlinuz-2.6.35~rc4-129.1-n8x0')
+ kernel_hash = 'e9d5ab8d7548923a0061b6fbf601465e479ed269'
+ kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
+
+ self.vm.set_console(console_index=1)
+ self.vm.add_args('-kernel', kernel_path,
+ '-append', 'printk.time=0 console=ttyS1')
+ self.vm.launch()
+ wait_for_console_pattern(self, 'TSC2005 driver initializing')
+
+ @skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'), 'untrusted code')
+ def test_n800(self):
+ """
+ :avocado: tags=arch:arm
+ :avocado: tags=machine:n800
+ """
+ self.__do_test_n8x0()
+
+ @skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'), 'untrusted code')
+ def test_n810(self):
+ """
+ :avocado: tags=arch:arm
+ :avocado: tags=machine:n810
+ """
+ self.__do_test_n8x0()
--
2.20.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* Re: [PULL 25/33] tests/acceptance: Add a test for the N800 and N810 arm machines
2020-02-28 16:38 ` [PULL 25/33] tests/acceptance: Add a test for the N800 and N810 arm machines Peter Maydell
@ 2020-10-17 17:51 ` Philippe Mathieu-Daudé
2020-10-19 6:31 ` Thomas Huth
0 siblings, 1 reply; 57+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-10-17 17:51 UTC (permalink / raw)
To: Peter Maydell, qemu-devel, Thomas Huth, Igor Mammedov, Alex Bennée
Hi Peter, Igor, Thomas,
On 2/28/20 5:38 PM, Peter Maydell wrote:
> From: Thomas Huth <thuth@redhat.com>
>
> Old kernels from the Meego project can be used to check that Linux
> is at least starting on these machines.
>
> Signed-off-by: Thomas Huth <thuth@redhat.com>
> Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Message-id: 20200225172501.29609-2-philmd@redhat.com
> Message-Id: <20200129131920.22302-1-thuth@redhat.com>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> MAINTAINERS | 1 +
> tests/acceptance/machine_arm_n8x0.py | 49 ++++++++++++++++++++++++++++
> 2 files changed, 50 insertions(+)
> create mode 100644 tests/acceptance/machine_arm_n8x0.py
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index b66c46dcb9f..264374adbe8 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -686,6 +686,7 @@ F: hw/rtc/twl92230.c
> F: include/hw/display/blizzard.h
> F: include/hw/input/tsc2xxx.h
> F: include/hw/misc/cbus.h
> +F: tests/acceptance/machine_arm_n8x0.py
>
> Palm
> M: Andrzej Zaborowski <balrogg@gmail.com>
> diff --git a/tests/acceptance/machine_arm_n8x0.py b/tests/acceptance/machine_arm_n8x0.py
> new file mode 100644
> index 00000000000..e5741f2d8d1
> --- /dev/null
> +++ b/tests/acceptance/machine_arm_n8x0.py
> @@ -0,0 +1,49 @@
> +# Functional test that boots a Linux kernel and checks the console
> +#
> +# Copyright (c) 2020 Red Hat, Inc.
> +#
> +# Author:
> +# Thomas Huth <thuth@redhat.com>
> +#
> +# This work is licensed under the terms of the GNU GPL, version 2 or
> +# later. See the COPYING file in the top-level directory.
> +
> +import os
> +
> +from avocado import skipUnless
> +from avocado_qemu import Test
> +from avocado_qemu import wait_for_console_pattern
> +
> +class N8x0Machine(Test):
> + """Boots the Linux kernel and checks that the console is operational"""
> +
> + timeout = 90
> +
> + def __do_test_n8x0(self):
> + kernel_url = ('http://stskeeps.subnetmask.net/meego-n8x0/'
> + 'meego-arm-n8x0-1.0.80.20100712.1431-'
> + 'vmlinuz-2.6.35~rc4-129.1-n8x0')
> + kernel_hash = 'e9d5ab8d7548923a0061b6fbf601465e479ed269'
> + kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
> +
> + self.vm.set_console(console_index=1)
> + self.vm.add_args('-kernel', kernel_path,
> + '-append', 'printk.time=0 console=ttyS1')
> + self.vm.launch()
> + wait_for_console_pattern(self, 'TSC2005 driver initializing')
> +
> + @skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'), 'untrusted code')
> + def test_n800(self):
> + """
> + :avocado: tags=arch:arm
> + :avocado: tags=machine:n800
> + """
> + self.__do_test_n8x0()
> +
> + @skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'), 'untrusted code')
> + def test_n810(self):
> + """
> + :avocado: tags=arch:arm
> + :avocado: tags=machine:n810
> + """
> + self.__do_test_n8x0()
>
FYI this test is failing:
qemu-system-arm: kernel 'meego-arm-n8x0-1.0.80.20100712.1431-vml
inuz-2.6.35~rc4-129.1-n8x0' is too large to fit in RAM (kernel size
1964608, RAM size 0)
Alex, Thomas, can we enable AVOCADO_ALLOW_UNTRUSTED_CODE on GitLab
to avoid such regressions?
Regards,
Phil.
^ permalink raw reply [flat|nested] 57+ messages in thread* Re: [PULL 25/33] tests/acceptance: Add a test for the N800 and N810 arm machines
2020-10-17 17:51 ` Philippe Mathieu-Daudé
@ 2020-10-19 6:31 ` Thomas Huth
2020-10-19 9:30 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 57+ messages in thread
From: Thomas Huth @ 2020-10-19 6:31 UTC (permalink / raw)
To: Philippe Mathieu-Daudé,
Peter Maydell, qemu-devel, Igor Mammedov, Alex Bennée
On 17/10/2020 19.51, Philippe Mathieu-Daudé wrote:
> Hi Peter, Igor, Thomas,
>
> On 2/28/20 5:38 PM, Peter Maydell wrote:
>> From: Thomas Huth <thuth@redhat.com>
>>
>> Old kernels from the Meego project can be used to check that Linux
>> is at least starting on these machines.
>>
>> Signed-off-by: Thomas Huth <thuth@redhat.com>
>> Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
>> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>> Message-id: 20200225172501.29609-2-philmd@redhat.com
>> Message-Id: <20200129131920.22302-1-thuth@redhat.com>
>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
>> ---
>> MAINTAINERS | 1 +
>> tests/acceptance/machine_arm_n8x0.py | 49 ++++++++++++++++++++++++++++
>> 2 files changed, 50 insertions(+)
>> create mode 100644 tests/acceptance/machine_arm_n8x0.py
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index b66c46dcb9f..264374adbe8 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -686,6 +686,7 @@ F: hw/rtc/twl92230.c
>> F: include/hw/display/blizzard.h
>> F: include/hw/input/tsc2xxx.h
>> F: include/hw/misc/cbus.h
>> +F: tests/acceptance/machine_arm_n8x0.py
>> Palm
>> M: Andrzej Zaborowski <balrogg@gmail.com>
>> diff --git a/tests/acceptance/machine_arm_n8x0.py
>> b/tests/acceptance/machine_arm_n8x0.py
>> new file mode 100644
>> index 00000000000..e5741f2d8d1
>> --- /dev/null
>> +++ b/tests/acceptance/machine_arm_n8x0.py
>> @@ -0,0 +1,49 @@
>> +# Functional test that boots a Linux kernel and checks the console
>> +#
>> +# Copyright (c) 2020 Red Hat, Inc.
>> +#
>> +# Author:
>> +# Thomas Huth <thuth@redhat.com>
>> +#
>> +# This work is licensed under the terms of the GNU GPL, version 2 or
>> +# later. See the COPYING file in the top-level directory.
>> +
>> +import os
>> +
>> +from avocado import skipUnless
>> +from avocado_qemu import Test
>> +from avocado_qemu import wait_for_console_pattern
>> +
>> +class N8x0Machine(Test):
>> + """Boots the Linux kernel and checks that the console is operational"""
>> +
>> + timeout = 90
>> +
>> + def __do_test_n8x0(self):
>> + kernel_url = ('http://stskeeps.subnetmask.net/meego-n8x0/'
>> + 'meego-arm-n8x0-1.0.80.20100712.1431-'
>> + 'vmlinuz-2.6.35~rc4-129.1-n8x0')
>> + kernel_hash = 'e9d5ab8d7548923a0061b6fbf601465e479ed269'
>> + kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
>> +
>> + self.vm.set_console(console_index=1)
>> + self.vm.add_args('-kernel', kernel_path,
>> + '-append', 'printk.time=0 console=ttyS1')
>> + self.vm.launch()
>> + wait_for_console_pattern(self, 'TSC2005 driver initializing')
>> +
>> + @skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'), 'untrusted code')
>> + def test_n800(self):
>> + """
>> + :avocado: tags=arch:arm
>> + :avocado: tags=machine:n800
>> + """
>> + self.__do_test_n8x0()
>> +
>> + @skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'), 'untrusted code')
>> + def test_n810(self):
>> + """
>> + :avocado: tags=arch:arm
>> + :avocado: tags=machine:n810
>> + """
>> + self.__do_test_n8x0()
>>
>
> FYI this test is failing:
>
> qemu-system-arm: kernel 'meego-arm-n8x0-1.0.80.20100712.1431-vml
> inuz-2.6.35~rc4-129.1-n8x0' is too large to fit in RAM (kernel size 1964608,
> RAM size 0)
>
> Alex, Thomas, can we enable AVOCADO_ALLOW_UNTRUSTED_CODE on GitLab
> to avoid such regressions?
Yes, please, if you've got some spare minutes to work on such a patch, that
would be great! ... I once already wanted to send such a patch, but IIRC
there were some other ALLOW_UNTRUSTED_CODE tests failing at that poing in
time, and I never got around to fix them...
Thomas
^ permalink raw reply [flat|nested] 57+ messages in thread* Re: [PULL 25/33] tests/acceptance: Add a test for the N800 and N810 arm machines
2020-10-19 6:31 ` Thomas Huth
@ 2020-10-19 9:30 ` Philippe Mathieu-Daudé
2020-10-19 9:43 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 57+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-10-19 9:30 UTC (permalink / raw)
To: Thomas Huth, Peter Maydell, qemu-devel, Igor Mammedov, Alex Bennée
On 10/19/20 8:31 AM, Thomas Huth wrote:
> On 17/10/2020 19.51, Philippe Mathieu-Daudé wrote:
>> Hi Peter, Igor, Thomas,
>>
>> On 2/28/20 5:38 PM, Peter Maydell wrote:
>>> From: Thomas Huth <thuth@redhat.com>
>>>
>>> Old kernels from the Meego project can be used to check that Linux
>>> is at least starting on these machines.
>>>
>>> Signed-off-by: Thomas Huth <thuth@redhat.com>
>>> Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
>>> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>>> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>>> Message-id: 20200225172501.29609-2-philmd@redhat.com
>>> Message-Id: <20200129131920.22302-1-thuth@redhat.com>
>>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>>> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
>>> ---
>>> MAINTAINERS | 1 +
>>> tests/acceptance/machine_arm_n8x0.py | 49 ++++++++++++++++++++++++++++
>>> 2 files changed, 50 insertions(+)
>>> create mode 100644 tests/acceptance/machine_arm_n8x0.py
>>>
>>> diff --git a/MAINTAINERS b/MAINTAINERS
>>> index b66c46dcb9f..264374adbe8 100644
>>> --- a/MAINTAINERS
>>> +++ b/MAINTAINERS
>>> @@ -686,6 +686,7 @@ F: hw/rtc/twl92230.c
>>> F: include/hw/display/blizzard.h
>>> F: include/hw/input/tsc2xxx.h
>>> F: include/hw/misc/cbus.h
>>> +F: tests/acceptance/machine_arm_n8x0.py
>>> Palm
>>> M: Andrzej Zaborowski <balrogg@gmail.com>
>>> diff --git a/tests/acceptance/machine_arm_n8x0.py
>>> b/tests/acceptance/machine_arm_n8x0.py
>>> new file mode 100644
>>> index 00000000000..e5741f2d8d1
>>> --- /dev/null
>>> +++ b/tests/acceptance/machine_arm_n8x0.py
>>> @@ -0,0 +1,49 @@
>>> +# Functional test that boots a Linux kernel and checks the console
>>> +#
>>> +# Copyright (c) 2020 Red Hat, Inc.
>>> +#
>>> +# Author:
>>> +# Thomas Huth <thuth@redhat.com>
>>> +#
>>> +# This work is licensed under the terms of the GNU GPL, version 2 or
>>> +# later. See the COPYING file in the top-level directory.
>>> +
>>> +import os
>>> +
>>> +from avocado import skipUnless
>>> +from avocado_qemu import Test
>>> +from avocado_qemu import wait_for_console_pattern
>>> +
>>> +class N8x0Machine(Test):
>>> + """Boots the Linux kernel and checks that the console is operational"""
>>> +
>>> + timeout = 90
>>> +
>>> + def __do_test_n8x0(self):
>>> + kernel_url = ('http://stskeeps.subnetmask.net/meego-n8x0/'
>>> + 'meego-arm-n8x0-1.0.80.20100712.1431-'
>>> + 'vmlinuz-2.6.35~rc4-129.1-n8x0')
>>> + kernel_hash = 'e9d5ab8d7548923a0061b6fbf601465e479ed269'
>>> + kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
>>> +
>>> + self.vm.set_console(console_index=1)
>>> + self.vm.add_args('-kernel', kernel_path,
>>> + '-append', 'printk.time=0 console=ttyS1')
>>> + self.vm.launch()
>>> + wait_for_console_pattern(self, 'TSC2005 driver initializing')
>>> +
>>> + @skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'), 'untrusted code')
>>> + def test_n800(self):
>>> + """
>>> + :avocado: tags=arch:arm
>>> + :avocado: tags=machine:n800
>>> + """
>>> + self.__do_test_n8x0()
>>> +
>>> + @skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'), 'untrusted code')
>>> + def test_n810(self):
>>> + """
>>> + :avocado: tags=arch:arm
>>> + :avocado: tags=machine:n810
>>> + """
>>> + self.__do_test_n8x0()
>>>
>>
>> FYI this test is failing:
>>
>> qemu-system-arm: kernel 'meego-arm-n8x0-1.0.80.20100712.1431-vml
>> inuz-2.6.35~rc4-129.1-n8x0' is too large to fit in RAM (kernel size 1964608,
>> RAM size 0)
FWIW:
7998beb9c2e280f0b7424223747941f106e2e854 is the first bad commit
commit 7998beb9c2e280f0b7424223747941f106e2e854
Author: Igor Mammedov <imammedo@redhat.com>
Date: Wed Feb 19 11:08:59 2020 -0500
arm/nseries: use memdev for RAM
memory_region_allocate_system_memory() API is going away, so
replace it with memdev allocated MemoryRegion. The later is
initialized by generic code, so board only needs to opt in
to memdev scheme by providing
MachineClass::default_ram_id
and using MachineState::ram instead of manually initializing
RAM memory region.
PS:
while at it add check for user supplied RAM size and error
out if it mismatches board expected value.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200219160953.13771-26-imammedo@redhat.com>
>>
>> Alex, Thomas, can we enable AVOCADO_ALLOW_UNTRUSTED_CODE on GitLab
>> to avoid such regressions?
>
> Yes, please, if you've got some spare minutes to work on such a patch, that
> would be great! ... I once already wanted to send such a patch, but IIRC
> there were some other ALLOW_UNTRUSTED_CODE tests failing at that poing in
> time, and I never got around to fix them...
>
> Thomas
>
>
^ permalink raw reply [flat|nested] 57+ messages in thread* Re: [PULL 25/33] tests/acceptance: Add a test for the N800 and N810 arm machines
2020-10-19 9:30 ` Philippe Mathieu-Daudé
@ 2020-10-19 9:43 ` Philippe Mathieu-Daudé
2020-10-23 15:43 ` Igor Mammedov
0 siblings, 1 reply; 57+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-10-19 9:43 UTC (permalink / raw)
To: Thomas Huth, Peter Maydell, qemu-devel, Igor Mammedov, Alex Bennée
On 10/19/20 11:30 AM, Philippe Mathieu-Daudé wrote:
> On 10/19/20 8:31 AM, Thomas Huth wrote:
>> On 17/10/2020 19.51, Philippe Mathieu-Daudé wrote:
>>> Hi Peter, Igor, Thomas,
>>>
>>> On 2/28/20 5:38 PM, Peter Maydell wrote:
>>>> From: Thomas Huth <thuth@redhat.com>
>>>>
>>>> Old kernels from the Meego project can be used to check that Linux
>>>> is at least starting on these machines.
>>>>
>>>> Signed-off-by: Thomas Huth <thuth@redhat.com>
>>>> Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
>>>> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>>>> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>>>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>>>> Message-id: 20200225172501.29609-2-philmd@redhat.com
>>>> Message-Id: <20200129131920.22302-1-thuth@redhat.com>
>>>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>>>> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
>>>> ---
>>>> MAINTAINERS | 1 +
>>>> tests/acceptance/machine_arm_n8x0.py | 49
>>>> ++++++++++++++++++++++++++++
>>>> 2 files changed, 50 insertions(+)
>>>> create mode 100644 tests/acceptance/machine_arm_n8x0.py
>>>>
>>>> diff --git a/MAINTAINERS b/MAINTAINERS
>>>> index b66c46dcb9f..264374adbe8 100644
>>>> --- a/MAINTAINERS
>>>> +++ b/MAINTAINERS
>>>> @@ -686,6 +686,7 @@ F: hw/rtc/twl92230.c
>>>> F: include/hw/display/blizzard.h
>>>> F: include/hw/input/tsc2xxx.h
>>>> F: include/hw/misc/cbus.h
>>>> +F: tests/acceptance/machine_arm_n8x0.py
>>>> Palm
>>>> M: Andrzej Zaborowski <balrogg@gmail.com>
>>>> diff --git a/tests/acceptance/machine_arm_n8x0.py
>>>> b/tests/acceptance/machine_arm_n8x0.py
>>>> new file mode 100644
>>>> index 00000000000..e5741f2d8d1
>>>> --- /dev/null
>>>> +++ b/tests/acceptance/machine_arm_n8x0.py
>>>> @@ -0,0 +1,49 @@
>>>> +# Functional test that boots a Linux kernel and checks the console
>>>> +#
>>>> +# Copyright (c) 2020 Red Hat, Inc.
>>>> +#
>>>> +# Author:
>>>> +# Thomas Huth <thuth@redhat.com>
>>>> +#
>>>> +# This work is licensed under the terms of the GNU GPL, version 2 or
>>>> +# later. See the COPYING file in the top-level directory.
>>>> +
>>>> +import os
>>>> +
>>>> +from avocado import skipUnless
>>>> +from avocado_qemu import Test
>>>> +from avocado_qemu import wait_for_console_pattern
>>>> +
>>>> +class N8x0Machine(Test):
>>>> + """Boots the Linux kernel and checks that the console is
>>>> operational"""
>>>> +
>>>> + timeout = 90
>>>> +
>>>> + def __do_test_n8x0(self):
>>>> + kernel_url = ('http://stskeeps.subnetmask.net/meego-n8x0/'
>>>> + 'meego-arm-n8x0-1.0.80.20100712.1431-'
>>>> + 'vmlinuz-2.6.35~rc4-129.1-n8x0')
>>>> + kernel_hash = 'e9d5ab8d7548923a0061b6fbf601465e479ed269'
>>>> + kernel_path = self.fetch_asset(kernel_url,
>>>> asset_hash=kernel_hash)
>>>> +
>>>> + self.vm.set_console(console_index=1)
>>>> + self.vm.add_args('-kernel', kernel_path,
>>>> + '-append', 'printk.time=0 console=ttyS1')
>>>> + self.vm.launch()
>>>> + wait_for_console_pattern(self, 'TSC2005 driver initializing')
>>>> +
>>>> + @skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'),
>>>> 'untrusted code')
>>>> + def test_n800(self):
>>>> + """
>>>> + :avocado: tags=arch:arm
>>>> + :avocado: tags=machine:n800
>>>> + """
>>>> + self.__do_test_n8x0()
>>>> +
>>>> + @skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'),
>>>> 'untrusted code')
>>>> + def test_n810(self):
>>>> + """
>>>> + :avocado: tags=arch:arm
>>>> + :avocado: tags=machine:n810
>>>> + """
>>>> + self.__do_test_n8x0()
>>>>
>>>
>>> FYI this test is failing:
>>>
>>> qemu-system-arm: kernel 'meego-arm-n8x0-1.0.80.20100712.1431-vml
>>> inuz-2.6.35~rc4-129.1-n8x0' is too large to fit in RAM (kernel size
>>> 1964608,
>>> RAM size 0)
>
> FWIW:
>
> 7998beb9c2e280f0b7424223747941f106e2e854 is the first bad commit
> commit 7998beb9c2e280f0b7424223747941f106e2e854
> Author: Igor Mammedov <imammedo@redhat.com>
> Date: Wed Feb 19 11:08:59 2020 -0500
>
> arm/nseries: use memdev for RAM
>
> memory_region_allocate_system_memory() API is going away, so
> replace it with memdev allocated MemoryRegion. The later is
> initialized by generic code, so board only needs to opt in
> to memdev scheme by providing
> MachineClass::default_ram_id
> and using MachineState::ram instead of manually initializing
> RAM memory region.
>
> PS:
> while at it add check for user supplied RAM size and error
> out if it mismatches board expected value.
>
> Signed-off-by: Igor Mammedov <imammedo@redhat.com>
> Reviewed-by: Andrew Jones <drjones@redhat.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Message-Id: <20200219160953.13771-26-imammedo@redhat.com>
This fixes the issue:
-- >8 --
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
index e48092ca047..76fd7fe9854 100644
--- a/hw/arm/nseries.c
+++ b/hw/arm/nseries.c
@@ -1318,6 +1318,7 @@ static void n8x0_init(MachineState *machine,
g_free(sz);
exit(EXIT_FAILURE);
}
+ binfo->ram_size = machine->ram_size;
memory_region_add_subregion(get_system_memory(), OMAP2_Q2_BASE,
machine->ram);
---
>
>>>
>>> Alex, Thomas, can we enable AVOCADO_ALLOW_UNTRUSTED_CODE on GitLab
>>> to avoid such regressions?
>>
>> Yes, please, if you've got some spare minutes to work on such a patch,
>> that
>> would be great! ... I once already wanted to send such a patch, but IIRC
>> there were some other ALLOW_UNTRUSTED_CODE tests failing at that poing in
>> time, and I never got around to fix them...
>>
>> Thomas
>>
>>
>
^ permalink raw reply related [flat|nested] 57+ messages in thread* Re: [PULL 25/33] tests/acceptance: Add a test for the N800 and N810 arm machines
2020-10-19 9:43 ` Philippe Mathieu-Daudé
@ 2020-10-23 15:43 ` Igor Mammedov
2020-10-23 17:39 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 57+ messages in thread
From: Igor Mammedov @ 2020-10-23 15:43 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Peter Maydell, Thomas Huth, Alex Bennée, qemu-devel
On Mon, 19 Oct 2020 11:43:13 +0200
Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> On 10/19/20 11:30 AM, Philippe Mathieu-Daudé wrote:
> > On 10/19/20 8:31 AM, Thomas Huth wrote:
> >> On 17/10/2020 19.51, Philippe Mathieu-Daudé wrote:
> >>> Hi Peter, Igor, Thomas,
> >>>
> >>> On 2/28/20 5:38 PM, Peter Maydell wrote:
> >>>> From: Thomas Huth <thuth@redhat.com>
> >>>>
> >>>> Old kernels from the Meego project can be used to check that Linux
> >>>> is at least starting on these machines.
> >>>>
> >>>> Signed-off-by: Thomas Huth <thuth@redhat.com>
> >>>> Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
> >>>> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> >>>> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> >>>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> >>>> Message-id: 20200225172501.29609-2-philmd@redhat.com
> >>>> Message-Id: <20200129131920.22302-1-thuth@redhat.com>
> >>>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> >>>> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> >>>> ---
> >>>> MAINTAINERS | 1 +
> >>>> tests/acceptance/machine_arm_n8x0.py | 49
> >>>> ++++++++++++++++++++++++++++
> >>>> 2 files changed, 50 insertions(+)
> >>>> create mode 100644 tests/acceptance/machine_arm_n8x0.py
> >>>>
> >>>> diff --git a/MAINTAINERS b/MAINTAINERS
> >>>> index b66c46dcb9f..264374adbe8 100644
> >>>> --- a/MAINTAINERS
> >>>> +++ b/MAINTAINERS
> >>>> @@ -686,6 +686,7 @@ F: hw/rtc/twl92230.c
> >>>> F: include/hw/display/blizzard.h
> >>>> F: include/hw/input/tsc2xxx.h
> >>>> F: include/hw/misc/cbus.h
> >>>> +F: tests/acceptance/machine_arm_n8x0.py
> >>>> Palm
> >>>> M: Andrzej Zaborowski <balrogg@gmail.com>
> >>>> diff --git a/tests/acceptance/machine_arm_n8x0.py
> >>>> b/tests/acceptance/machine_arm_n8x0.py
> >>>> new file mode 100644
> >>>> index 00000000000..e5741f2d8d1
> >>>> --- /dev/null
> >>>> +++ b/tests/acceptance/machine_arm_n8x0.py
> >>>> @@ -0,0 +1,49 @@
> >>>> +# Functional test that boots a Linux kernel and checks the console
> >>>> +#
> >>>> +# Copyright (c) 2020 Red Hat, Inc.
> >>>> +#
> >>>> +# Author:
> >>>> +# Thomas Huth <thuth@redhat.com>
> >>>> +#
> >>>> +# This work is licensed under the terms of the GNU GPL, version 2 or
> >>>> +# later. See the COPYING file in the top-level directory.
> >>>> +
> >>>> +import os
> >>>> +
> >>>> +from avocado import skipUnless
> >>>> +from avocado_qemu import Test
> >>>> +from avocado_qemu import wait_for_console_pattern
> >>>> +
> >>>> +class N8x0Machine(Test):
> >>>> + """Boots the Linux kernel and checks that the console is
> >>>> operational"""
> >>>> +
> >>>> + timeout = 90
> >>>> +
> >>>> + def __do_test_n8x0(self):
> >>>> + kernel_url = ('http://stskeeps.subnetmask.net/meego-n8x0/'
> >>>> + 'meego-arm-n8x0-1.0.80.20100712.1431-'
> >>>> + 'vmlinuz-2.6.35~rc4-129.1-n8x0')
> >>>> + kernel_hash = 'e9d5ab8d7548923a0061b6fbf601465e479ed269'
> >>>> + kernel_path = self.fetch_asset(kernel_url,
> >>>> asset_hash=kernel_hash)
> >>>> +
> >>>> + self.vm.set_console(console_index=1)
> >>>> + self.vm.add_args('-kernel', kernel_path,
> >>>> + '-append', 'printk.time=0 console=ttyS1')
> >>>> + self.vm.launch()
> >>>> + wait_for_console_pattern(self, 'TSC2005 driver initializing')
> >>>> +
> >>>> + @skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'),
> >>>> 'untrusted code')
> >>>> + def test_n800(self):
> >>>> + """
> >>>> + :avocado: tags=arch:arm
> >>>> + :avocado: tags=machine:n800
> >>>> + """
> >>>> + self.__do_test_n8x0()
> >>>> +
> >>>> + @skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'),
> >>>> 'untrusted code')
> >>>> + def test_n810(self):
> >>>> + """
> >>>> + :avocado: tags=arch:arm
> >>>> + :avocado: tags=machine:n810
> >>>> + """
> >>>> + self.__do_test_n8x0()
> >>>>
> >>>
> >>> FYI this test is failing:
> >>>
> >>> qemu-system-arm: kernel 'meego-arm-n8x0-1.0.80.20100712.1431-vml
> >>> inuz-2.6.35~rc4-129.1-n8x0' is too large to fit in RAM (kernel size
> >>> 1964608,
> >>> RAM size 0)
> >
> > FWIW:
> >
> > 7998beb9c2e280f0b7424223747941f106e2e854 is the first bad commit
> > commit 7998beb9c2e280f0b7424223747941f106e2e854
> > Author: Igor Mammedov <imammedo@redhat.com>
> > Date: Wed Feb 19 11:08:59 2020 -0500
> >
> > arm/nseries: use memdev for RAM
> >
> > memory_region_allocate_system_memory() API is going away, so
> > replace it with memdev allocated MemoryRegion. The later is
> > initialized by generic code, so board only needs to opt in
> > to memdev scheme by providing
> > MachineClass::default_ram_id
> > and using MachineState::ram instead of manually initializing
> > RAM memory region.
> >
> > PS:
> > while at it add check for user supplied RAM size and error
> > out if it mismatches board expected value.
> >
> > Signed-off-by: Igor Mammedov <imammedo@redhat.com>
> > Reviewed-by: Andrew Jones <drjones@redhat.com>
> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> > Message-Id: <20200219160953.13771-26-imammedo@redhat.com>
>
> This fixes the issue:
>
> -- >8 --
> diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
> index e48092ca047..76fd7fe9854 100644
> --- a/hw/arm/nseries.c
> +++ b/hw/arm/nseries.c
> @@ -1318,6 +1318,7 @@ static void n8x0_init(MachineState *machine,
> g_free(sz);
> exit(EXIT_FAILURE);
> }
> + binfo->ram_size = machine->ram_size;
>
> memory_region_add_subregion(get_system_memory(), OMAP2_Q2_BASE,
> machine->ram);
we really should replace binfo->ram_size with machine->ram_size to avoid
duplicating the same data, but as a quick fix this should fix issue.
Acked-by: Igor Mammedov <imammedo@redhat.com>
> ---
>
> >
> >>>
> >>> Alex, Thomas, can we enable AVOCADO_ALLOW_UNTRUSTED_CODE on GitLab
> >>> to avoid such regressions?
> >>
> >> Yes, please, if you've got some spare minutes to work on such a patch,
> >> that
> >> would be great! ... I once already wanted to send such a patch, but IIRC
> >> there were some other ALLOW_UNTRUSTED_CODE tests failing at that poing in
> >> time, and I never got around to fix them...
> >>
> >> Thomas
> >>
> >>
> >
>
^ permalink raw reply [flat|nested] 57+ messages in thread* Re: [PULL 25/33] tests/acceptance: Add a test for the N800 and N810 arm machines
2020-10-23 15:43 ` Igor Mammedov
@ 2020-10-23 17:39 ` Philippe Mathieu-Daudé
2020-10-23 19:04 ` Igor Mammedov
0 siblings, 1 reply; 57+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-10-23 17:39 UTC (permalink / raw)
To: Igor Mammedov; +Cc: Peter Maydell, Thomas Huth, Alex Bennée, qemu-devel
On 10/23/20 5:43 PM, Igor Mammedov wrote:
> On Mon, 19 Oct 2020 11:43:13 +0200
> Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>>>>> FYI this test is failing:
>>>>>
>>>>> qemu-system-arm: kernel 'meego-arm-n8x0-1.0.80.20100712.1431-vml
>>>>> inuz-2.6.35~rc4-129.1-n8x0' is too large to fit in RAM (kernel size
>>>>> 1964608,
>>>>> RAM size 0)
>>>
>>> FWIW:
>>>
>>> 7998beb9c2e280f0b7424223747941f106e2e854 is the first bad commit
>>> commit 7998beb9c2e280f0b7424223747941f106e2e854
>>> Author: Igor Mammedov <imammedo@redhat.com>
>>> Date: Wed Feb 19 11:08:59 2020 -0500
>>>
>>> arm/nseries: use memdev for RAM
>>>
>>> memory_region_allocate_system_memory() API is going away, so
>>> replace it with memdev allocated MemoryRegion. The later is
>>> initialized by generic code, so board only needs to opt in
>>> to memdev scheme by providing
>>> MachineClass::default_ram_id
>>> and using MachineState::ram instead of manually initializing
>>> RAM memory region.
>>>
>>> PS:
>>> while at it add check for user supplied RAM size and error
>>> out if it mismatches board expected value.
>>>
>>> Signed-off-by: Igor Mammedov <imammedo@redhat.com>
>>> Reviewed-by: Andrew Jones <drjones@redhat.com>
>>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>>> Message-Id: <20200219160953.13771-26-imammedo@redhat.com>
>>
>> This fixes the issue:
>>
>> -- >8 --
>> diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
>> index e48092ca047..76fd7fe9854 100644
>> --- a/hw/arm/nseries.c
>> +++ b/hw/arm/nseries.c
>> @@ -1318,6 +1318,7 @@ static void n8x0_init(MachineState *machine,
>> g_free(sz);
>> exit(EXIT_FAILURE);
>> }
>> + binfo->ram_size = machine->ram_size;
>>
>> memory_region_add_subregion(get_system_memory(), OMAP2_Q2_BASE,
>> machine->ram);
>
> we really should replace binfo->ram_size with machine->ram_size to avoid
> duplicating the same data, but as a quick fix this should fix issue.
Hmm this is the 'ARM kernel loader' API in "arm/boot.h":
struct arm_boot_info {
uint64_t ram_size;
const char *kernel_filename;
const char *kernel_cmdline;
const char *initrd_filename;
const char *dtb_filename;
and:
void (*write_secondary_boot)(ARMCPU *cpu,
const struct arm_boot_info *info);
void (*secondary_cpu_reset_hook)(ARMCPU *cpu,
const struct arm_boot_info *info);
Are you saying arm_boot_info should hold a pointer to MachineState*
instead of duplicating?
^ permalink raw reply [flat|nested] 57+ messages in thread* Re: [PULL 25/33] tests/acceptance: Add a test for the N800 and N810 arm machines
2020-10-23 17:39 ` Philippe Mathieu-Daudé
@ 2020-10-23 19:04 ` Igor Mammedov
2020-10-25 17:03 ` Peter Maydell
0 siblings, 1 reply; 57+ messages in thread
From: Igor Mammedov @ 2020-10-23 19:04 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Peter Maydell, Thomas Huth, Alex Bennée, qemu-devel
On Fri, 23 Oct 2020 19:39:16 +0200
Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> On 10/23/20 5:43 PM, Igor Mammedov wrote:
> > On Mon, 19 Oct 2020 11:43:13 +0200
> > Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> >>>>> FYI this test is failing:
> >>>>>
> >>>>> qemu-system-arm: kernel 'meego-arm-n8x0-1.0.80.20100712.1431-vml
> >>>>> inuz-2.6.35~rc4-129.1-n8x0' is too large to fit in RAM (kernel size
> >>>>> 1964608,
> >>>>> RAM size 0)
> >>>
> >>> FWIW:
> >>>
> >>> 7998beb9c2e280f0b7424223747941f106e2e854 is the first bad commit
> >>> commit 7998beb9c2e280f0b7424223747941f106e2e854
> >>> Author: Igor Mammedov <imammedo@redhat.com>
> >>> Date: Wed Feb 19 11:08:59 2020 -0500
> >>>
> >>> arm/nseries: use memdev for RAM
> >>>
> >>> memory_region_allocate_system_memory() API is going away, so
> >>> replace it with memdev allocated MemoryRegion. The later is
> >>> initialized by generic code, so board only needs to opt in
> >>> to memdev scheme by providing
> >>> MachineClass::default_ram_id
> >>> and using MachineState::ram instead of manually initializing
> >>> RAM memory region.
> >>>
> >>> PS:
> >>> while at it add check for user supplied RAM size and error
> >>> out if it mismatches board expected value.
> >>>
> >>> Signed-off-by: Igor Mammedov <imammedo@redhat.com>
> >>> Reviewed-by: Andrew Jones <drjones@redhat.com>
> >>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> >>> Message-Id: <20200219160953.13771-26-imammedo@redhat.com>
> >>
> >> This fixes the issue:
> >>
> >> -- >8 --
> >> diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
> >> index e48092ca047..76fd7fe9854 100644
> >> --- a/hw/arm/nseries.c
> >> +++ b/hw/arm/nseries.c
> >> @@ -1318,6 +1318,7 @@ static void n8x0_init(MachineState *machine,
> >> g_free(sz);
> >> exit(EXIT_FAILURE);
> >> }
> >> + binfo->ram_size = machine->ram_size;
> >>
> >> memory_region_add_subregion(get_system_memory(), OMAP2_Q2_BASE,
> >> machine->ram);
> >
> > we really should replace binfo->ram_size with machine->ram_size to avoid
> > duplicating the same data, but as a quick fix this should fix issue.
>
> Hmm this is the 'ARM kernel loader' API in "arm/boot.h":
>
> struct arm_boot_info {
> uint64_t ram_size;
> const char *kernel_filename;
> const char *kernel_cmdline;
> const char *initrd_filename;
> const char *dtb_filename;
>
> and:
>
> void (*write_secondary_boot)(ARMCPU *cpu,
> const struct arm_boot_info *info);
> void (*secondary_cpu_reset_hook)(ARMCPU *cpu,
> const struct arm_boot_info *info);
>
> Are you saying arm_boot_info should hold a pointer to MachineState*
> instead of duplicating?
yep, some parts of it (fdt related) already use MachineState* so it's
complete rewrite. The same probably applies to the fields you've just
quoted.
>
^ permalink raw reply [flat|nested] 57+ messages in thread* Re: [PULL 25/33] tests/acceptance: Add a test for the N800 and N810 arm machines
2020-10-23 19:04 ` Igor Mammedov
@ 2020-10-25 17:03 ` Peter Maydell
2020-10-26 13:36 ` Igor Mammedov
0 siblings, 1 reply; 57+ messages in thread
From: Peter Maydell @ 2020-10-25 17:03 UTC (permalink / raw)
To: Igor Mammedov
Cc: Thomas Huth, Alex Bennée, Philippe Mathieu-Daudé,
QEMU Developers
On Fri, 23 Oct 2020 at 20:04, Igor Mammedov <imammedo@redhat.com> wrote:
>
> On Fri, 23 Oct 2020 19:39:16 +0200
> Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> > Are you saying arm_boot_info should hold a pointer to MachineState*
> > instead of duplicating?
>
> yep, some parts of it (fdt related) already use MachineState* so it's
> complete rewrite. The same probably applies to the fields you've just
> quoted.
Hmm, maybe, maybe not. The original design idea here was that
the boot loader code took a structure defining only the things
that the bootloader needed to know. It doesn't really need to
know about all the stuff that's in MachineState, which is
the state structure for the machine.
thanks
-- PMM
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PULL 25/33] tests/acceptance: Add a test for the N800 and N810 arm machines
2020-10-25 17:03 ` Peter Maydell
@ 2020-10-26 13:36 ` Igor Mammedov
2020-10-26 14:26 ` Peter Maydell
0 siblings, 1 reply; 57+ messages in thread
From: Igor Mammedov @ 2020-10-26 13:36 UTC (permalink / raw)
To: Peter Maydell
Cc: Thomas Huth, Alex Bennée, Philippe Mathieu-Daudé,
QEMU Developers
On Sun, 25 Oct 2020 17:03:43 +0000
Peter Maydell <peter.maydell@linaro.org> wrote:
> On Fri, 23 Oct 2020 at 20:04, Igor Mammedov <imammedo@redhat.com> wrote:
> >
> > On Fri, 23 Oct 2020 19:39:16 +0200
> > Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> > > Are you saying arm_boot_info should hold a pointer to MachineState*
> > > instead of duplicating?
> >
> > yep, some parts of it (fdt related) already use MachineState* so it's
> > complete rewrite. The same probably applies to the fields you've just
> > quoted.
>
> Hmm, maybe, maybe not. The original design idea here was that
> the boot loader code took a structure defining only the things
> that the bootloader needed to know. It doesn't really need to
> know about all the stuff that's in MachineState, which is
> the state structure for the machine.
Yep It doesn't need all data the MachineState contains, but then we end up
with this kind of bugs which could be avoided if duplication were not there.
And some of the fields in MachineState are pure bootloader data.
>
> thanks
> -- PMM
>
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PULL 25/33] tests/acceptance: Add a test for the N800 and N810 arm machines
2020-10-26 13:36 ` Igor Mammedov
@ 2020-10-26 14:26 ` Peter Maydell
2020-10-27 10:54 ` Igor Mammedov
0 siblings, 1 reply; 57+ messages in thread
From: Peter Maydell @ 2020-10-26 14:26 UTC (permalink / raw)
To: Igor Mammedov
Cc: Thomas Huth, Alex Bennée, Philippe Mathieu-Daudé,
QEMU Developers
On Mon, 26 Oct 2020 at 13:37, Igor Mammedov <imammedo@redhat.com> wrote:
> Peter Maydell <peter.maydell@linaro.org> wrote:
> > Hmm, maybe, maybe not. The original design idea here was that
> > the boot loader code took a structure defining only the things
> > that the bootloader needed to know. It doesn't really need to
> > know about all the stuff that's in MachineState, which is
> > the state structure for the machine.
>
> Yep It doesn't need all data the MachineState contains, but then we end up
> with this kind of bugs which could be avoided if duplication were not there.
> And some of the fields in MachineState are pure bootloader data.
I notice we already have arm_load_kernel() take a MachineState*
and fill in the info->kernel_filename etc from the MachineState
fields. I suppose we could do the same for a few more fields.
I'm not very fond of the way that function takes the MachineState*,
though. I think it would be nicer if the MachineState had a
separate sub-struct which was "this is the stuff that's just
data for the bootloader" and passed that, rather than throwing
the entire state struct pointer around.
thanks
-- PMM
^ permalink raw reply [flat|nested] 57+ messages in thread
* Re: [PULL 25/33] tests/acceptance: Add a test for the N800 and N810 arm machines
2020-10-26 14:26 ` Peter Maydell
@ 2020-10-27 10:54 ` Igor Mammedov
0 siblings, 0 replies; 57+ messages in thread
From: Igor Mammedov @ 2020-10-27 10:54 UTC (permalink / raw)
To: Peter Maydell
Cc: Thomas Huth, Alex Bennée, Philippe Mathieu-Daudé,
QEMU Developers
On Mon, 26 Oct 2020 14:26:59 +0000
Peter Maydell <peter.maydell@linaro.org> wrote:
> On Mon, 26 Oct 2020 at 13:37, Igor Mammedov <imammedo@redhat.com> wrote:
> > Peter Maydell <peter.maydell@linaro.org> wrote:
> > > Hmm, maybe, maybe not. The original design idea here was that
> > > the boot loader code took a structure defining only the things
> > > that the bootloader needed to know. It doesn't really need to
> > > know about all the stuff that's in MachineState, which is
> > > the state structure for the machine.
> >
> > Yep It doesn't need all data the MachineState contains, but then we end up
> > with this kind of bugs which could be avoided if duplication were not there.
> > And some of the fields in MachineState are pure bootloader data.
>
> I notice we already have arm_load_kernel() take a MachineState*
> and fill in the info->kernel_filename etc from the MachineState
> fields. I suppose we could do the same for a few more fields.
> I'm not very fond of the way that function takes the MachineState*,
> though. I think it would be nicer if the MachineState had a
> separate sub-struct which was "this is the stuff that's just
> data for the bootloader" and passed that, rather than throwing
> the entire state struct pointer around.
this should work for the most of copied fields but not for all,
(ram_size in this case).
>
> thanks
> -- PMM
>
^ permalink raw reply [flat|nested] 57+ messages in thread
* [PULL 26/33] tests/acceptance: Add a test for the integratorcp arm machine
2020-02-28 16:38 [PULL 00/33] target-arm queue Peter Maydell
` (24 preceding siblings ...)
2020-02-28 16:38 ` [PULL 25/33] tests/acceptance: Add a test for the N800 and N810 arm machines Peter Maydell
@ 2020-02-28 16:38 ` Peter Maydell
2020-02-28 16:38 ` [PULL 27/33] tests/acceptance: Extract boot_integratorcp() from test_integratorcp() Peter Maydell
` (7 subsequent siblings)
33 siblings, 0 replies; 57+ messages in thread
From: Peter Maydell @ 2020-02-28 16:38 UTC (permalink / raw)
To: qemu-devel
From: Thomas Huth <thuth@redhat.com>
There is a kernel and initrd available on github which we can use
for testing this machine.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200225172501.29609-3-philmd@redhat.com
Message-Id: <20200131170233.14584-1-thuth@redhat.com>
[PMD: Renamed test method, moved description from class to method]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
MAINTAINERS | 1 +
tests/acceptance/machine_arm_integratorcp.py | 43 ++++++++++++++++++++
2 files changed, 44 insertions(+)
create mode 100644 tests/acceptance/machine_arm_integratorcp.py
diff --git a/MAINTAINERS b/MAINTAINERS
index 264374adbe8..c258391cad8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -613,6 +613,7 @@ S: Maintained
F: hw/arm/integratorcp.c
F: hw/misc/arm_integrator_debug.c
F: include/hw/misc/arm_integrator_debug.h
+F: tests/acceptance/machine_arm_integratorcp.py
MCIMX6UL EVK / i.MX6ul
M: Peter Maydell <peter.maydell@linaro.org>
diff --git a/tests/acceptance/machine_arm_integratorcp.py b/tests/acceptance/machine_arm_integratorcp.py
new file mode 100644
index 00000000000..d928ed79b4c
--- /dev/null
+++ b/tests/acceptance/machine_arm_integratorcp.py
@@ -0,0 +1,43 @@
+# Functional test that boots a Linux kernel and checks the console
+#
+# Copyright (c) 2020 Red Hat, Inc.
+#
+# Author:
+# Thomas Huth <thuth@redhat.com>
+#
+# This work is licensed under the terms of the GNU GPL, version 2 or
+# later. See the COPYING file in the top-level directory.
+
+import os
+
+from avocado import skipUnless
+from avocado_qemu import Test
+from avocado_qemu import wait_for_console_pattern
+
+class IntegratorMachine(Test):
+
+ timeout = 90
+
+ @skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'), 'untrusted code')
+ def test_integratorcp_console(self):
+ """
+ Boots the Linux kernel and checks that the console is operational
+ :avocado: tags=arch:arm
+ :avocado: tags=machine:integratorcp
+ """
+ kernel_url = ('https://github.com/zayac/qemu-arm/raw/master/'
+ 'arm-test/kernel/zImage.integrator')
+ kernel_hash = '0d7adba893c503267c946a3cbdc63b4b54f25468'
+ kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
+
+ initrd_url = ('https://github.com/zayac/qemu-arm/raw/master/'
+ 'arm-test/kernel/arm_root.img')
+ initrd_hash = 'b51e4154285bf784e017a37586428332d8c7bd8b'
+ initrd_path = self.fetch_asset(initrd_url, asset_hash=initrd_hash)
+
+ self.vm.set_console()
+ self.vm.add_args('-kernel', kernel_path,
+ '-initrd', initrd_path,
+ '-append', 'printk.time=0 console=ttyAMA0')
+ self.vm.launch()
+ wait_for_console_pattern(self, 'Log in as root')
--
2.20.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 27/33] tests/acceptance: Extract boot_integratorcp() from test_integratorcp()
2020-02-28 16:38 [PULL 00/33] target-arm queue Peter Maydell
` (25 preceding siblings ...)
2020-02-28 16:38 ` [PULL 26/33] tests/acceptance: Add a test for the integratorcp arm machine Peter Maydell
@ 2020-02-28 16:38 ` Peter Maydell
2020-02-28 16:38 ` [PULL 28/33] tests/acceptance/integratorcp: Verify Tux is displayed on framebuffer Peter Maydell
` (6 subsequent siblings)
33 siblings, 0 replies; 57+ messages in thread
From: Peter Maydell @ 2020-02-28 16:38 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
As we want to re-use this code, extract it as a new function.
Since we are using the PL011 serial console, add a Avocado tag
to ease filtering of tests.
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200225172501.29609-4-philmd@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
tests/acceptance/machine_arm_integratorcp.py | 18 +++++++++++-------
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/tests/acceptance/machine_arm_integratorcp.py b/tests/acceptance/machine_arm_integratorcp.py
index d928ed79b4c..22afd3b82a8 100644
--- a/tests/acceptance/machine_arm_integratorcp.py
+++ b/tests/acceptance/machine_arm_integratorcp.py
@@ -18,13 +18,7 @@ class IntegratorMachine(Test):
timeout = 90
- @skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'), 'untrusted code')
- def test_integratorcp_console(self):
- """
- Boots the Linux kernel and checks that the console is operational
- :avocado: tags=arch:arm
- :avocado: tags=machine:integratorcp
- """
+ def boot_integratorcp(self):
kernel_url = ('https://github.com/zayac/qemu-arm/raw/master/'
'arm-test/kernel/zImage.integrator')
kernel_hash = '0d7adba893c503267c946a3cbdc63b4b54f25468'
@@ -40,4 +34,14 @@ class IntegratorMachine(Test):
'-initrd', initrd_path,
'-append', 'printk.time=0 console=ttyAMA0')
self.vm.launch()
+
+ @skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'), 'untrusted code')
+ def test_integratorcp_console(self):
+ """
+ Boots the Linux kernel and checks that the console is operational
+ :avocado: tags=arch:arm
+ :avocado: tags=machine:integratorcp
+ :avocado: tags=device:pl011
+ """
+ self.boot_integratorcp()
wait_for_console_pattern(self, 'Log in as root')
--
2.20.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 28/33] tests/acceptance/integratorcp: Verify Tux is displayed on framebuffer
2020-02-28 16:38 [PULL 00/33] target-arm queue Peter Maydell
` (26 preceding siblings ...)
2020-02-28 16:38 ` [PULL 27/33] tests/acceptance: Extract boot_integratorcp() from test_integratorcp() Peter Maydell
@ 2020-02-28 16:38 ` Peter Maydell
2020-02-28 16:38 ` [PULL 29/33] target/arm: Fix wrong use of FIELD_EX32 on ID_AA64DFR0 Peter Maydell
` (5 subsequent siblings)
33 siblings, 0 replies; 57+ messages in thread
From: Peter Maydell @ 2020-02-28 16:38 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Add a test that verifies the Tux logo is displayed on the framebuffer.
We simply follow the OpenCV "Template Matching with Multiple Objects"
tutorial, replacing Lionel Messi by Tux:
https://docs.opencv.org/4.2.0/d4/dc6/tutorial_py_template_matching.html
When OpenCV and NumPy are installed, this test can be run using:
$ AVOCADO_ALLOW_UNTRUSTED_CODE=hmmm \
avocado --show=app,framebuffer run -t device:framebuffer \
tests/acceptance/machine_arm_integratorcp.py
JOB ID : 8c46b0f8269242e87d738247883ea2a470df949e
JOB LOG : avocado/job-results/job-2020-01-31T21.38-8c46b0f/job.log
(1/1) tests/acceptance/machine_arm_integratorcp.py:IntegratorMachine.test_framebuffer_tux_logo:
framebuffer: found Tux at position [x, y] = (0, 0)
PASS (3.96 s)
RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0
JOB TIME : 4.23 s
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
Message-id: 20200225172501.29609-5-philmd@redhat.com
Message-Id: <20200131211102.29612-3-f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
tests/acceptance/machine_arm_integratorcp.py | 52 ++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/tests/acceptance/machine_arm_integratorcp.py b/tests/acceptance/machine_arm_integratorcp.py
index 22afd3b82a8..49c8ebff78b 100644
--- a/tests/acceptance/machine_arm_integratorcp.py
+++ b/tests/acceptance/machine_arm_integratorcp.py
@@ -9,11 +9,26 @@
# later. See the COPYING file in the top-level directory.
import os
+import logging
from avocado import skipUnless
from avocado_qemu import Test
from avocado_qemu import wait_for_console_pattern
+
+NUMPY_AVAILABLE = True
+try:
+ import numpy as np
+except ImportError:
+ NUMPY_AVAILABLE = False
+
+CV2_AVAILABLE = True
+try:
+ import cv2
+except ImportError:
+ CV2_AVAILABLE = False
+
+
class IntegratorMachine(Test):
timeout = 90
@@ -45,3 +60,40 @@ class IntegratorMachine(Test):
"""
self.boot_integratorcp()
wait_for_console_pattern(self, 'Log in as root')
+
+ @skipUnless(NUMPY_AVAILABLE, 'Python NumPy not installed')
+ @skipUnless(CV2_AVAILABLE, 'Python OpenCV not installed')
+ @skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'), 'untrusted code')
+ def test_framebuffer_tux_logo(self):
+ """
+ Boot Linux and verify the Tux logo is displayed on the framebuffer.
+ :avocado: tags=arch:arm
+ :avocado: tags=machine:integratorcp
+ :avocado: tags=device:pl110
+ :avocado: tags=device:framebuffer
+ """
+ screendump_path = os.path.join(self.workdir, "screendump.pbm")
+ tuxlogo_url = ('https://github.com/torvalds/linux/raw/v2.6.12/'
+ 'drivers/video/logo/logo_linux_vga16.ppm')
+ tuxlogo_hash = '3991c2ddbd1ddaecda7601f8aafbcf5b02dc86af'
+ tuxlogo_path = self.fetch_asset(tuxlogo_url, asset_hash=tuxlogo_hash)
+
+ self.boot_integratorcp()
+ framebuffer_ready = 'Console: switching to colour frame buffer device'
+ wait_for_console_pattern(self, framebuffer_ready)
+ self.vm.command('human-monitor-command', command_line='stop')
+ self.vm.command('human-monitor-command',
+ command_line='screendump %s' % screendump_path)
+ logger = logging.getLogger('framebuffer')
+
+ cpu_count = 1
+ match_threshold = 0.92
+ screendump_bgr = cv2.imread(screendump_path)
+ screendump_gray = cv2.cvtColor(screendump_bgr, cv2.COLOR_BGR2GRAY)
+ result = cv2.matchTemplate(screendump_gray, cv2.imread(tuxlogo_path, 0),
+ cv2.TM_CCOEFF_NORMED)
+ loc = np.where(result >= match_threshold)
+ tux_count = 0
+ for tux_count, pt in enumerate(zip(*loc[::-1]), start=1):
+ logger.debug('found Tux at position [x, y] = %s', pt)
+ self.assertGreaterEqual(tux_count, cpu_count)
--
2.20.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 29/33] target/arm: Fix wrong use of FIELD_EX32 on ID_AA64DFR0
2020-02-28 16:38 [PULL 00/33] target-arm queue Peter Maydell
` (27 preceding siblings ...)
2020-02-28 16:38 ` [PULL 28/33] tests/acceptance/integratorcp: Verify Tux is displayed on framebuffer Peter Maydell
@ 2020-02-28 16:38 ` Peter Maydell
2020-02-28 16:38 ` [PULL 30/33] target/arm: Implement v8.3-RCPC Peter Maydell
` (4 subsequent siblings)
33 siblings, 0 replies; 57+ messages in thread
From: Peter Maydell @ 2020-02-28 16:38 UTC (permalink / raw)
To: qemu-devel
We missed an instance of using FIELD_EX32 on a 64-bit ID
register, in isar_feature_aa64_pmu_8_4(). Fix it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200224172846.13053-2-peter.maydell@linaro.org
---
target/arm/cpu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 05aa9711cd8..6013287f623 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3770,8 +3770,8 @@ static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id)
static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 &&
- FIELD_EX32(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
+ return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 &&
+ FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
}
/*
--
2.20.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 30/33] target/arm: Implement v8.3-RCPC
2020-02-28 16:38 [PULL 00/33] target-arm queue Peter Maydell
` (28 preceding siblings ...)
2020-02-28 16:38 ` [PULL 29/33] target/arm: Fix wrong use of FIELD_EX32 on ID_AA64DFR0 Peter Maydell
@ 2020-02-28 16:38 ` Peter Maydell
2020-02-28 16:38 ` [PULL 31/33] target/arm: Implement v8.4-RCPC Peter Maydell
` (3 subsequent siblings)
33 siblings, 0 replies; 57+ messages in thread
From: Peter Maydell @ 2020-02-28 16:38 UTC (permalink / raw)
To: qemu-devel
The v8.3-RCPC extension implements three new load instructions
which provide slightly weaker consistency guarantees than the
existing load-acquire operations. For QEMU we choose to simply
implement them with a full LDAQ barrier.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200224172846.13053-3-peter.maydell@linaro.org
---
target/arm/cpu.h | 5 +++++
linux-user/elfload.c | 1 +
target/arm/cpu64.c | 1 +
target/arm/translate-a64.c | 24 ++++++++++++++++++++++++
4 files changed, 31 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 6013287f623..ff30985ead4 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3774,6 +3774,11 @@ static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id)
FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
}
+static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0;
+}
+
/*
* Feature tests for "does this exist in either 32-bit or 64-bit?"
*/
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 86cda127b78..d76b828a789 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -661,6 +661,7 @@ static uint32_t get_elf_hwcap(void)
GET_FEATURE_ID(aa64_sb, ARM_HWCAP_A64_SB);
GET_FEATURE_ID(aa64_condm_4, ARM_HWCAP_A64_FLAGM);
GET_FEATURE_ID(aa64_dcpop, ARM_HWCAP_A64_DCPOP);
+ GET_FEATURE_ID(aa64_rcpc_8_3, ARM_HWCAP_A64_LRCPC);
return hwcaps;
}
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 8f2a43c938a..18c7b40f98c 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -654,6 +654,7 @@ static void aarch64_max_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);
+ t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 1); /* ARMv8.3-RCPC */
cpu->isar.id_aa64isar1 = t;
t = cpu->isar.id_aa64pfr0;
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 596bf4cf734..7a066fb7cb2 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -3142,6 +3142,8 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn,
int rs = extract32(insn, 16, 5);
int rn = extract32(insn, 5, 5);
int o3_opc = extract32(insn, 12, 4);
+ bool r = extract32(insn, 22, 1);
+ bool a = extract32(insn, 23, 1);
TCGv_i64 tcg_rs, clean_addr;
AtomicThreeOpFn *fn;
@@ -3177,6 +3179,13 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn,
case 010: /* SWP */
fn = tcg_gen_atomic_xchg_i64;
break;
+ case 014: /* LDAPR, LDAPRH, LDAPRB */
+ if (!dc_isar_feature(aa64_rcpc_8_3, s) ||
+ rs != 31 || a != 1 || r != 0) {
+ unallocated_encoding(s);
+ return;
+ }
+ break;
default:
unallocated_encoding(s);
return;
@@ -3186,6 +3195,21 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn,
gen_check_sp_alignment(s);
}
clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn));
+
+ if (o3_opc == 014) {
+ /*
+ * LDAPR* are a special case because they are a simple load, not a
+ * fetch-and-do-something op.
+ * The architectural consistency requirements here are weaker than
+ * full load-acquire (we only need "load-acquire processor consistent"),
+ * but we choose to implement them as full LDAQ.
+ */
+ do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false,
+ true, rt, disas_ldst_compute_iss_sf(size, false, 0), true);
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
+ return;
+ }
+
tcg_rs = read_cpu_reg(s, rs, true);
if (o3_opc == 1) { /* LDCLR */
--
2.20.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 31/33] target/arm: Implement v8.4-RCPC
2020-02-28 16:38 [PULL 00/33] target-arm queue Peter Maydell
` (29 preceding siblings ...)
2020-02-28 16:38 ` [PULL 30/33] target/arm: Implement v8.3-RCPC Peter Maydell
@ 2020-02-28 16:38 ` Peter Maydell
2020-02-28 16:38 ` [PULL 32/33] target/arm: Implement ARMv8.3-CCIDX Peter Maydell
` (2 subsequent siblings)
33 siblings, 0 replies; 57+ messages in thread
From: Peter Maydell @ 2020-02-28 16:38 UTC (permalink / raw)
To: qemu-devel
The v8.4-RCPC extension implements some new instructions:
* LDAPUR, LDAPURB, LDAPURH, LDAPRSB, LDAPRSH, LDAPRSW
* STLUR, STLURB, STLURH
These are all in a new subgroup of encodings that sits below the
top-level "Loads and Stores" group in the Arm ARM.
The STLUR* instructions have standard store-release semantics; the
LDAPUR* have Load-AcquirePC semantics, but (as with LDAPR*) we choose
to implement them as the slightly stronger Load-Acquire.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200224172846.13053-4-peter.maydell@linaro.org
---
target/arm/cpu.h | 5 +++
linux-user/elfload.c | 1 +
target/arm/cpu64.c | 2 +-
target/arm/translate-a64.c | 90 ++++++++++++++++++++++++++++++++++++++
4 files changed, 97 insertions(+), 1 deletion(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index ff30985ead4..ce1e2a090e5 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3779,6 +3779,11 @@ static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id)
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0;
}
+static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2;
+}
+
/*
* Feature tests for "does this exist in either 32-bit or 64-bit?"
*/
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index d76b828a789..db748c58775 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -662,6 +662,7 @@ static uint32_t get_elf_hwcap(void)
GET_FEATURE_ID(aa64_condm_4, ARM_HWCAP_A64_FLAGM);
GET_FEATURE_ID(aa64_dcpop, ARM_HWCAP_A64_DCPOP);
GET_FEATURE_ID(aa64_rcpc_8_3, ARM_HWCAP_A64_LRCPC);
+ GET_FEATURE_ID(aa64_rcpc_8_4, ARM_HWCAP_A64_ILRCPC);
return hwcaps;
}
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 18c7b40f98c..b842e2b664a 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -654,7 +654,7 @@ static void aarch64_max_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);
- t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 1); /* ARMv8.3-RCPC */
+ t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */
cpu->isar.id_aa64isar1 = t;
t = cpu->isar.id_aa64pfr0;
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 7a066fb7cb2..579180af0a9 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -3283,6 +3283,88 @@ static void disas_ldst_pac(DisasContext *s, uint32_t insn,
}
}
+/*
+ * LDAPR/STLR (unscaled immediate)
+ *
+ * 31 30 24 22 21 12 10 5 0
+ * +------+-------------+-----+---+--------+-----+----+-----+
+ * | size | 0 1 1 0 0 1 | opc | 0 | imm9 | 0 0 | Rn | Rt |
+ * +------+-------------+-----+---+--------+-----+----+-----+
+ *
+ * Rt: source or destination register
+ * Rn: base register
+ * imm9: unscaled immediate offset
+ * opc: 00: STLUR*, 01/10/11: various LDAPUR*
+ * size: size of load/store
+ */
+static void disas_ldst_ldapr_stlr(DisasContext *s, uint32_t insn)
+{
+ int rt = extract32(insn, 0, 5);
+ int rn = extract32(insn, 5, 5);
+ int offset = sextract32(insn, 12, 9);
+ int opc = extract32(insn, 22, 2);
+ int size = extract32(insn, 30, 2);
+ TCGv_i64 clean_addr, dirty_addr;
+ bool is_store = false;
+ bool is_signed = false;
+ bool extend = false;
+ bool iss_sf;
+
+ if (!dc_isar_feature(aa64_rcpc_8_4, s)) {
+ unallocated_encoding(s);
+ return;
+ }
+
+ switch (opc) {
+ case 0: /* STLURB */
+ is_store = true;
+ break;
+ case 1: /* LDAPUR* */
+ break;
+ case 2: /* LDAPURS* 64-bit variant */
+ if (size == 3) {
+ unallocated_encoding(s);
+ return;
+ }
+ is_signed = true;
+ break;
+ case 3: /* LDAPURS* 32-bit variant */
+ if (size > 1) {
+ unallocated_encoding(s);
+ return;
+ }
+ is_signed = true;
+ extend = true; /* zero-extend 32->64 after signed load */
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc);
+
+ if (rn == 31) {
+ gen_check_sp_alignment(s);
+ }
+
+ dirty_addr = read_cpu_reg_sp(s, rn, 1);
+ tcg_gen_addi_i64(dirty_addr, dirty_addr, offset);
+ clean_addr = clean_data_tbi(s, dirty_addr);
+
+ if (is_store) {
+ /* Store-Release semantics */
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
+ do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt, iss_sf, true);
+ } else {
+ /*
+ * Load-AcquirePC semantics; we implement as the slightly more
+ * restrictive Load-Acquire.
+ */
+ do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, is_signed, extend,
+ true, rt, iss_sf, true);
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
+ }
+}
+
/* Load/store register (all forms) */
static void disas_ldst_reg(DisasContext *s, uint32_t insn)
{
@@ -3634,6 +3716,14 @@ static void disas_ldst(DisasContext *s, uint32_t insn)
case 0x0d: /* AdvSIMD load/store single structure */
disas_ldst_single_struct(s, insn);
break;
+ case 0x19: /* LDAPR/STLR (unscaled immediate) */
+ if (extract32(insn, 10, 2) != 0 ||
+ extract32(insn, 21, 1) != 0) {
+ unallocated_encoding(s);
+ break;
+ }
+ disas_ldst_ldapr_stlr(s, insn);
+ break;
default:
unallocated_encoding(s);
break;
--
2.20.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 32/33] target/arm: Implement ARMv8.3-CCIDX
2020-02-28 16:38 [PULL 00/33] target-arm queue Peter Maydell
` (30 preceding siblings ...)
2020-02-28 16:38 ` [PULL 31/33] target/arm: Implement v8.4-RCPC Peter Maydell
@ 2020-02-28 16:38 ` Peter Maydell
2020-02-28 16:38 ` [PULL 33/33] hw/intc/arm_gic_kvm: Don't assume kernel can provide a GICv2 Peter Maydell
2020-02-28 17:59 ` [PULL 00/33] target-arm queue Peter Maydell
33 siblings, 0 replies; 57+ messages in thread
From: Peter Maydell @ 2020-02-28 16:38 UTC (permalink / raw)
To: qemu-devel
The ARMv8.3-CCIDX extension makes the CCSIDR_EL1 system ID registers
have a format that uses the full 64 bit width of the register, and
adds a new CCSIDR2 register so AArch32 can get at the high 32 bits.
QEMU doesn't implement caches, so we just treat these ID registers as
opaque values that are set to the correct constant values for each
CPU. The only thing we need to do is allow 64-bit values in our
cssidr[] array and provide the CCSIDR2 accessors.
We don't set the CCIDX field in our 'max' CPU because the CCSIDR
constant values we use are the same as the ones used by the
Cortex-A57 and they are in the old 32-bit format. This means
that the extra regdef added here is unused currently, but it
means that whenever in the future we add a CPU that does need
the new 64-bit format it will just work when we set the cssidr
values and the ID registers for it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200224182626.29252-1-peter.maydell@linaro.org
---
target/arm/cpu.h | 17 ++++++++++++++++-
target/arm/helper.c | 19 +++++++++++++++++++
2 files changed, 35 insertions(+), 1 deletion(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index ce1e2a090e5..0b84742b66a 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -904,7 +904,7 @@ struct ARMCPU {
/* The elements of this array are the CCSIDR values for each cache,
* in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
*/
- uint32_t ccsidr[16];
+ uint64_t ccsidr[16];
uint64_t reset_cbar;
uint32_t reset_auxcr;
bool reset_hivecs;
@@ -3577,6 +3577,11 @@ static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id)
return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0;
}
+static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id)
+{
+ return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0;
+}
+
/*
* 64-bit feature tests via id registers.
*/
@@ -3784,6 +3789,11 @@ static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id)
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2;
}
+static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
+}
+
/*
* Feature tests for "does this exist in either 32-bit or 64-bit?"
*/
@@ -3807,6 +3817,11 @@ static inline bool isar_feature_any_pmu_8_4(const ARMISARegisters *id)
return isar_feature_aa64_pmu_8_4(id) || isar_feature_aa32_pmu_8_4(id);
}
+static inline bool isar_feature_any_ccidx(const ARMISARegisters *id)
+{
+ return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id);
+}
+
/*
* Forward to the above feature tests given an ARMCPU pointer.
*/
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 8841cc7fde8..6be9ffa09ef 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6726,6 +6726,21 @@ static const ARMCPRegInfo predinv_reginfo[] = {
REGINFO_SENTINEL
};
+static uint64_t ccsidr2_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+ /* Read the high 32 bits of the current CCSIDR */
+ return extract64(ccsidr_read(env, ri), 32, 32);
+}
+
+static const ARMCPRegInfo ccsidr2_reginfo[] = {
+ { .name = "CCSIDR2", .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 2,
+ .access = PL1_R,
+ .accessfn = access_aa64_tid2,
+ .readfn = ccsidr2_read, .type = ARM_CP_NO_RAW },
+ REGINFO_SENTINEL
+};
+
static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInfo *ri,
bool isread)
{
@@ -7788,6 +7803,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
define_arm_cp_regs(cpu, predinv_reginfo);
}
+ if (cpu_isar_feature(any_ccidx, cpu)) {
+ define_arm_cp_regs(cpu, ccsidr2_reginfo);
+ }
+
#ifndef CONFIG_USER_ONLY
/*
* Register redirections and aliases must be done last,
--
2.20.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* [PULL 33/33] hw/intc/arm_gic_kvm: Don't assume kernel can provide a GICv2
2020-02-28 16:38 [PULL 00/33] target-arm queue Peter Maydell
` (31 preceding siblings ...)
2020-02-28 16:38 ` [PULL 32/33] target/arm: Implement ARMv8.3-CCIDX Peter Maydell
@ 2020-02-28 16:38 ` Peter Maydell
2020-02-28 17:59 ` [PULL 00/33] target-arm queue Peter Maydell
33 siblings, 0 replies; 57+ messages in thread
From: Peter Maydell @ 2020-02-28 16:38 UTC (permalink / raw)
To: qemu-devel
In our KVM GICv2 realize function, we try to cope with old kernels
that don't provide the device control API (KVM_CAP_DEVICE_CTRL): we
try to use the device control, and if that fails we fall back to
assuming that the kernel has the old style KVM_CREATE_IRQCHIP and
that it will provide a GICv2.
This doesn't cater for the possibility of a kernel and hardware which
only provide a GICv3, which is very common now. On that setup we
will abort() later on in kvm_arm_pmu_set_irq() when we try to wire up
an interrupt to the GIC we failed to create:
qemu-system-aarch64: PMU: KVM_SET_DEVICE_ATTR: Invalid argument
qemu-system-aarch64: failed to set irq for PMU
Aborted
If the kernel advertises KVM_CAP_DEVICE_CTRL we should trust it if it
says it can't create a GICv2, rather than assuming it has one. We
can then produce a more helpful error message including a hint about
the most probable reason for the failure.
If the kernel doesn't advertise KVM_CAP_DEVICE_CTRL then it is truly
ancient by this point but we might as well still fall back to a
KVM_CREATE_IRQCHIP GICv2.
With this patch then the user misconfiguration which previously
caused an abort now prints:
qemu-system-aarch64: Initialization of device kvm-arm-gic failed: error creating in-kernel VGIC: No such device
Perhaps the host CPU does not support GICv2?
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Tested-by: Andrew Jones <drjones@redhat.com>
Message-id: 20200225182435.1131-1-peter.maydell@linaro.org
---
hw/intc/arm_gic_kvm.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
index 9deb15e7e69..d7df423a7a3 100644
--- a/hw/intc/arm_gic_kvm.c
+++ b/hw/intc/arm_gic_kvm.c
@@ -551,7 +551,16 @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true,
&error_abort);
}
+ } else if (kvm_check_extension(kvm_state, KVM_CAP_DEVICE_CTRL)) {
+ error_setg_errno(errp, -ret, "error creating in-kernel VGIC");
+ error_append_hint(errp,
+ "Perhaps the host CPU does not support GICv2?\n");
} else if (ret != -ENODEV && ret != -ENOTSUP) {
+ /*
+ * Very ancient kernel without KVM_CAP_DEVICE_CTRL: assume that
+ * ENODEV or ENOTSUP mean "can't create GICv2 with KVM_CREATE_DEVICE",
+ * and that we will get a GICv2 via KVM_CREATE_IRQCHIP.
+ */
error_setg_errno(errp, -ret, "error creating in-kernel VGIC");
return;
}
--
2.20.1
^ permalink raw reply related [flat|nested] 57+ messages in thread* Re: [PULL 00/33] target-arm queue
2020-02-28 16:38 [PULL 00/33] target-arm queue Peter Maydell
` (32 preceding siblings ...)
2020-02-28 16:38 ` [PULL 33/33] hw/intc/arm_gic_kvm: Don't assume kernel can provide a GICv2 Peter Maydell
@ 2020-02-28 17:59 ` Peter Maydell
33 siblings, 0 replies; 57+ messages in thread
From: Peter Maydell @ 2020-02-28 17:59 UTC (permalink / raw)
To: QEMU Developers
On Fri, 28 Feb 2020 at 16:38, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Another arm pullreq; nothing particularly exciting here.
>
> -- PMM
>
>
> The following changes since commit e27d5b488ef08408691bfed61f34ee2858136287:
>
> Merge remote-tracking branch 'remotes/juanquintela/tags/pull-migration-pull-request' into staging (2020-02-28 14:02:31 +0000)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200228
>
> for you to fetch changes up to 1904f9b5f1d94fe12fe021db6b504c87d684f6db:
>
> hw/intc/arm_gic_kvm: Don't assume kernel can provide a GICv2 (2020-02-28 16:14:57 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
> * hw/arm: Use TYPE_PL011 to create serial port
> * target/arm: Set ID_MMFR4.HPDS for aarch64_max_initfn
> * hw/arm/integratorcp: Map the audio codec controller
> * GICv2: Correctly implement the limited number of priority bits
> * target/arm: refactoring of VFP related feature checks and decode
> * xilinx_zynq: Fix USB port instantiation
> * acceptance tests for n800, n810, integratorcp
> * Implement v8.3-RCPC, v8.4-RCPC, v8.3-CCIDX
> * arm_gic_kvm: Don't assume kernel can provide a GICv2
> (provide better error message for user error)
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/5.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 57+ messages in thread