From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 16/33] target/arm: Move VLLDM and VLSTM to vfp.decode
Date: Fri, 28 Feb 2020 16:38:23 +0000 [thread overview]
Message-ID: <20200228163840.23585-17-peter.maydell@linaro.org> (raw)
In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org>
From: Richard Henderson <richard.henderson@linaro.org>
Now that we no longer have an early check for ARM_FEATURE_VFP,
we can use the proper ISA check in trans_VLLDM_VLSTM.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200224222232.13807-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate-vfp.inc.c | 39 +++++++++++++++++++++++++
target/arm/translate.c | 53 ++++++----------------------------
target/arm/vfp.decode | 2 ++
3 files changed, 50 insertions(+), 44 deletions(-)
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index 03ba8d7aac0..1964af3ea5e 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -2828,3 +2828,42 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a)
tcg_temp_free_ptr(fpst);
return true;
}
+
+/*
+ * Decode VLLDM and VLSTM are nonstandard because:
+ * * if there is no FPU then these insns must NOP in
+ * Secure state and UNDEF in Nonsecure state
+ * * if there is an FPU then these insns do not have
+ * the usual behaviour that vfp_access_check() provides of
+ * being controlled by CPACR/NSACR enable bits or the
+ * lazy-stacking logic.
+ */
+static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a)
+{
+ TCGv_i32 fptr;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_M) ||
+ !arm_dc_feature(s, ARM_FEATURE_V8)) {
+ return false;
+ }
+ /* If not secure, UNDEF. */
+ if (!s->v8m_secure) {
+ return false;
+ }
+ /* If no fpu, NOP. */
+ if (!dc_isar_feature(aa32_vfp, s)) {
+ return true;
+ }
+
+ fptr = load_reg(s, a->rn);
+ if (a->l) {
+ gen_helper_v7m_vlldm(cpu_env, fptr);
+ } else {
+ gen_helper_v7m_vlstm(cpu_env, fptr);
+ }
+ tcg_temp_free_i32(fptr);
+
+ /* End the TB, because we have updated FP control bits */
+ s->base.is_jmp = DISAS_UPDATE;
+ return true;
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 893911fca70..5b7cad1ea2d 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10962,53 +10962,18 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
goto illegal_op; /* op0 = 0b11 : unallocated */
}
- /*
- * Decode VLLDM and VLSTM first: these are nonstandard because:
- * * if there is no FPU then these insns must NOP in
- * Secure state and UNDEF in Nonsecure state
- * * if there is an FPU then these insns do not have
- * the usual behaviour that disas_vfp_insn() provides of
- * being controlled by CPACR/NSACR enable bits or the
- * lazy-stacking logic.
- */
- if (arm_dc_feature(s, ARM_FEATURE_V8) &&
- (insn & 0xffa00f00) == 0xec200a00) {
- /* 0b1110_1100_0x1x_xxxx_xxxx_1010_xxxx_xxxx
- * - VLLDM, VLSTM
- * We choose to UNDEF if the RAZ bits are non-zero.
- */
- if (!s->v8m_secure || (insn & 0x0040f0ff)) {
+ if (disas_vfp_insn(s, insn)) {
+ if (((insn >> 8) & 0xe) == 10 &&
+ dc_isar_feature(aa32_fpsp_v2, s)) {
+ /* FP, and the CPU supports it */
goto illegal_op;
+ } else {
+ /* All other insns: NOCP */
+ gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
+ syn_uncategorized(),
+ default_exception_el(s));
}
-
- if (arm_dc_feature(s, ARM_FEATURE_VFP)) {
- uint32_t rn = (insn >> 16) & 0xf;
- TCGv_i32 fptr = load_reg(s, rn);
-
- if (extract32(insn, 20, 1)) {
- gen_helper_v7m_vlldm(cpu_env, fptr);
- } else {
- gen_helper_v7m_vlstm(cpu_env, fptr);
- }
- tcg_temp_free_i32(fptr);
-
- /* End the TB, because we have updated FP control bits */
- s->base.is_jmp = DISAS_UPDATE;
- }
- break;
}
- if (arm_dc_feature(s, ARM_FEATURE_VFP) &&
- ((insn >> 8) & 0xe) == 10) {
- /* FP, and the CPU supports it */
- if (disas_vfp_insn(s, insn)) {
- goto illegal_op;
- }
- break;
- }
-
- /* All other insns: NOCP */
- gen_exception_insn(s, s->pc_curr, EXCP_NOCP, syn_uncategorized(),
- default_exception_el(s));
break;
}
if ((insn & 0xfe000a00) == 0xfc000800
diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode
index a67b3f29ee5..592fe9e1e42 100644
--- a/target/arm/vfp.decode
+++ b/target/arm/vfp.decode
@@ -242,3 +242,5 @@ VCVT_sp_int ---- 1110 1.11 110 s:1 .... 1010 rz:1 1.0 .... \
vd=%vd_sp vm=%vm_sp
VCVT_dp_int ---- 1110 1.11 110 s:1 .... 1011 rz:1 1.0 .... \
vd=%vd_sp vm=%vm_dp
+
+VLLDM_VLSTM 1110 1100 001 l:1 rn:4 0000 1010 0000 0000
--
2.20.1
next prev parent reply other threads:[~2020-02-28 16:53 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-28 16:38 [PULL 00/33] target-arm queue Peter Maydell
2020-02-28 16:38 ` [PULL 01/33] hw/arm: Use TYPE_PL011 to create serial port Peter Maydell
2020-02-28 16:38 ` [PULL 02/33] target/arm: Set ID_MMFR4.HPDS for aarch64_max_initfn Peter Maydell
2020-02-28 16:38 ` [PULL 03/33] hw/arm/integratorcp: Map the audio codec controller Peter Maydell
2020-02-28 16:38 ` [PULL 04/33] arm_gic: Mask the un-supported priority bits Peter Maydell
2020-02-28 16:38 ` [PULL 05/33] cpu/a9mpcore: Set number of GIC priority bits to 5 Peter Maydell
2020-02-28 16:38 ` [PULL 06/33] cpu/arm11mpcore: Set number of GIC priority bits to 4 Peter Maydell
2020-02-28 16:38 ` [PULL 07/33] target/arm: Add isar_feature_aa32_vfp_simd Peter Maydell
2020-02-28 16:38 ` [PULL 08/33] target/arm: Rename isar_feature_aa32_fpdp_v2 Peter Maydell
2020-02-28 16:38 ` [PULL 09/33] target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3} Peter Maydell
2020-02-28 16:38 ` [PULL 10/33] target/arm: Add isar_feature_aa64_fp_simd, isar_feature_aa32_vfp Peter Maydell
2020-02-28 16:38 ` [PULL 11/33] target/arm: Perform fpdp_v2 check first Peter Maydell
2020-02-28 16:38 ` [PULL 12/33] target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3 Peter Maydell
2020-02-28 16:38 ` [PULL 13/33] target/arm: Add missing checks for fpsp_v2 Peter Maydell
2020-02-28 16:38 ` [PULL 14/33] target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac Peter Maydell
2020-02-28 16:38 ` [PULL 15/33] target/arm: Remove ARM_FEATURE_VFP check from disas_vfp_insn Peter Maydell
2020-02-28 16:38 ` Peter Maydell [this message]
2020-02-28 16:38 ` [PULL 17/33] target/arm: Move the vfp decodetree calls next to the base isa Peter Maydell
2020-02-28 16:38 ` [PULL 18/33] linux-user/arm: Replace ARM_FEATURE_VFP* tests for HWCAP Peter Maydell
2020-02-28 16:38 ` [PULL 19/33] target/arm: Remove ARM_FEATURE_VFP* Peter Maydell
2020-02-28 16:38 ` [PULL 20/33] target/arm: Add formats for some vfp 2 and 3-register insns Peter Maydell
2020-02-28 16:38 ` [PULL 21/33] target/arm: Split VFM decode Peter Maydell
2020-02-28 16:38 ` [PULL 22/33] target/arm: Split VMINMAXNM decode Peter Maydell
2020-02-28 16:38 ` [PULL 23/33] hw/arm/xilinx_zynq: Fix USB port instantiation Peter Maydell
2021-05-19 17:50 ` Philippe Mathieu-Daudé
2020-02-28 16:38 ` [PULL 24/33] hw/usb/hcd-ehci-sysbus: Remove obsolete xlnx, ps7-usb class Peter Maydell
2020-02-28 16:38 ` [PULL 25/33] tests/acceptance: Add a test for the N800 and N810 arm machines Peter Maydell
2020-10-17 17:51 ` Philippe Mathieu-Daudé
2020-10-19 6:31 ` Thomas Huth
2020-10-19 9:30 ` Philippe Mathieu-Daudé
2020-10-19 9:43 ` Philippe Mathieu-Daudé
2020-10-23 15:43 ` Igor Mammedov
2020-10-23 17:39 ` Philippe Mathieu-Daudé
2020-10-23 19:04 ` Igor Mammedov
2020-10-25 17:03 ` Peter Maydell
2020-10-26 13:36 ` Igor Mammedov
2020-10-26 14:26 ` Peter Maydell
2020-10-27 10:54 ` Igor Mammedov
2020-02-28 16:38 ` [PULL 26/33] tests/acceptance: Add a test for the integratorcp arm machine Peter Maydell
2020-02-28 16:38 ` [PULL 27/33] tests/acceptance: Extract boot_integratorcp() from test_integratorcp() Peter Maydell
2020-02-28 16:38 ` [PULL 28/33] tests/acceptance/integratorcp: Verify Tux is displayed on framebuffer Peter Maydell
2020-02-28 16:38 ` [PULL 29/33] target/arm: Fix wrong use of FIELD_EX32 on ID_AA64DFR0 Peter Maydell
2020-02-28 16:38 ` [PULL 30/33] target/arm: Implement v8.3-RCPC Peter Maydell
2020-02-28 16:38 ` [PULL 31/33] target/arm: Implement v8.4-RCPC Peter Maydell
2020-02-28 16:38 ` [PULL 32/33] target/arm: Implement ARMv8.3-CCIDX Peter Maydell
2020-02-28 16:38 ` [PULL 33/33] hw/intc/arm_gic_kvm: Don't assume kernel can provide a GICv2 Peter Maydell
2020-02-28 17:59 ` [PULL 00/33] target-arm queue Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200228163840.23585-17-peter.maydell@linaro.org \
--to=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).