From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72F46C4332B for ; Fri, 20 Mar 2020 09:30:25 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3DDBD20409 for ; Fri, 20 Mar 2020 09:30:25 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="TS0/F2qW" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3DDBD20409 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:49936 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jFDyy-0008Gz-Ah for qemu-devel@archiver.kernel.org; Fri, 20 Mar 2020 05:30:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53715) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jFDuJ-0007JO-1N for qemu-devel@nongnu.org; Fri, 20 Mar 2020 05:25:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jFDuG-0001rW-7L for qemu-devel@nongnu.org; Fri, 20 Mar 2020 05:25:33 -0400 Received: from us-smtp-delivery-74.mimecast.com ([63.128.21.74]:54900) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jFDuG-0001qX-20 for qemu-devel@nongnu.org; Fri, 20 Mar 2020 05:25:32 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1584696331; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=pyoUxJMAJISr2R1CUtM36kjsIf74x1hkGn7NNC+WmAU=; b=TS0/F2qW78NCvWuyWhZTv7HXwYw5E1ITKZedTUEODFznuzclDCcNpy7RCFi2MG9iZpRtxF a4fHxKzhULyuC5ZeDvPH0L7Wplsd5T6S2NU5Xxgm42x/ZVoyOTlR3RC4h1d2H7EWwl3GUM bH4N4qmwASraxVjeuLK3qEkfkGA6kOA= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-468-bqvhWHyZOUObR-J1dSbjyQ-1; Fri, 20 Mar 2020 05:25:28 -0400 X-MC-Unique: bqvhWHyZOUObR-J1dSbjyQ-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 66EEA1005514; Fri, 20 Mar 2020 09:25:26 +0000 (UTC) Received: from laptop.redhat.com (ovpn-113-142.ams2.redhat.com [10.36.113.142]) by smtp.corp.redhat.com (Postfix) with ESMTP id 66FB85C1D8; Fri, 20 Mar 2020 09:25:23 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Subject: [kvm-unit-tests PATCH v7 10/13] arm/arm64: ITS: INT functional tests Date: Fri, 20 Mar 2020 10:24:25 +0100 Message-Id: <20200320092428.20880-11-eric.auger@redhat.com> In-Reply-To: <20200320092428.20880-1-eric.auger@redhat.com> References: <20200320092428.20880-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 63.128.21.74 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, drjones@redhat.com, andre.przywara@arm.com, thuth@redhat.com, yuzenghui@huawei.com, alexandru.elisei@arm.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Triggers LPIs through the INT command. the test checks the LPI hits the right CPU and triggers the right LPI intid, ie. the translation is correct. Updates to the config table also are tested, along with inv and invall commands. Signed-off-by: Eric Auger --- v5 -> v6: - removed collection-unmap test - moved the collection invalidation after the MAPCs v4 -> v5: - move the test stub from the header to arm/gic.c v3 -> v4: - assert in lpi_handler if the interrupt is not an LPI - remove check_lpi_stats from its_prerequisites() v2 -> v3: - add comments - keep the report_skip in case there aren't 4 vcpus to be able to run other tests in the its category. - fix the prefix pop - move its_event and its_stats to arm/gic.c --- arm/gic.c | 215 +++++++++++++++++++++++++++++++++++++++++++--- arm/unittests.cfg | 7 ++ 2 files changed, 211 insertions(+), 11 deletions(-) diff --git a/arm/gic.c b/arm/gic.c index 649ed81..5f1e595 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -159,6 +159,85 @@ static void ipi_handler(struct pt_regs *regs __unuse= d) } } =20 +static void setup_irq(irq_handler_fn handler) +{ + gic_enable_defaults(); +#ifdef __arm__ + install_exception_handler(EXCPTN_IRQ, handler); +#else + install_irq_handler(EL1H_IRQ, handler); +#endif + local_irq_enable(); +} + +#if defined(__aarch64__) +struct its_event { + int cpu_id; + int lpi_id; +}; + +struct its_stats { + struct its_event expected; + struct its_event observed; +}; + +static struct its_stats lpi_stats; + +static void lpi_handler(struct pt_regs *regs __unused) +{ + u32 irqstat =3D gic_read_iar(); + int irqnr =3D gic_iar_irqnr(irqstat); + + gic_write_eoir(irqstat); + assert(irqnr >=3D 8192); + smp_rmb(); /* pairs with wmb in lpi_stats_expect */ + lpi_stats.observed.cpu_id =3D smp_processor_id(); + lpi_stats.observed.lpi_id =3D irqnr; + smp_wmb(); /* pairs with rmb in check_lpi_stats */ +} + +static void lpi_stats_expect(int exp_cpu_id, int exp_lpi_id) +{ + lpi_stats.expected.cpu_id =3D exp_cpu_id; + lpi_stats.expected.lpi_id =3D exp_lpi_id; + lpi_stats.observed.cpu_id =3D -1; + lpi_stats.observed.lpi_id =3D -1; + smp_wmb(); /* pairs with rmb in handler */ +} + +static void check_lpi_stats(const char *msg) +{ + bool pass =3D false; + + mdelay(100); + smp_rmb(); /* pairs with wmb in lpi_handler */ + if (lpi_stats.observed.cpu_id !=3D lpi_stats.expected.cpu_id || + lpi_stats.observed.lpi_id !=3D lpi_stats.expected.lpi_id) { + if (lpi_stats.observed.cpu_id =3D=3D -1 && + lpi_stats.observed.lpi_id =3D=3D -1) { + report_info("No LPI received whereas (cpuid=3D%d, intid=3D%d) " + "was expected", lpi_stats.expected.cpu_id, + lpi_stats.expected.lpi_id); + } else { + report_info("Unexpected LPI (cpuid=3D%d, intid=3D%d)", + lpi_stats.observed.cpu_id, + lpi_stats.observed.lpi_id); + } + } else { + pass =3D true; + } + report(pass, "%s", msg); +} + +static void secondary_lpi_test(void) +{ + setup_irq(lpi_handler); + cpumask_set_cpu(smp_processor_id(), &ready); + while (1) + wfi(); +} +#endif + static void gicv2_ipi_send_self(void) { writel(2 << 24 | IPI_IRQ, gicv2_dist_base() + GICD_SGIR); @@ -216,17 +295,6 @@ static void ipi_test_smp(void) report_prefix_pop(); } =20 -static void setup_irq(irq_handler_fn handler) -{ - gic_enable_defaults(); -#ifdef __arm__ - install_exception_handler(EXCPTN_IRQ, handler); -#else - install_irq_handler(EL1H_IRQ, handler); -#endif - local_irq_enable(); -} - static void ipi_send(void) { setup_irq(ipi_handler); @@ -521,6 +589,7 @@ static void gic_test_mmio(void) #if defined(__arm__) =20 static void test_its_introspection(void) {} +static void test_its_trigger(void) {} =20 #else /* __aarch64__ */ =20 @@ -559,6 +628,126 @@ static void test_its_introspection(void) report_info("collection table entry_size =3D 0x%x", coll_baser->esz); } =20 +static int its_prerequisites(int nb_cpus) +{ + int cpu; + + if (!gicv3_its_base()) { + report_skip("No ITS, skip ..."); + return -1; + } + + if (nr_cpus < nb_cpus) { + report_skip("Test requires at least %d vcpus", nb_cpus); + return -1; + } + + stats_reset(); + + setup_irq(lpi_handler); + + for_each_present_cpu(cpu) { + if (cpu =3D=3D 0) + continue; + smp_boot_secondary(cpu, secondary_lpi_test); + } + wait_on_ready(); + + its_enable_defaults(); + + return 0; +} + +static void test_its_trigger(void) +{ + struct its_collection *col3, *col2; + struct its_device *dev2, *dev7; + + if (its_prerequisites(4)) + return; + + dev2 =3D its_create_device(2 /* dev id */, 8 /* nb_ites */); + dev7 =3D its_create_device(7 /* dev id */, 8 /* nb_ites */); + + col3 =3D its_create_collection(3 /* col id */, 3/* target PE */); + col2 =3D its_create_collection(2 /* col id */, 2/* target PE */); + + gicv3_lpi_set_config(8195, LPI_PROP_DEFAULT); + gicv3_lpi_set_config(8196, LPI_PROP_DEFAULT); + + report_prefix_push("int"); + /* + * dev=3D2, eventid=3D20 -> lpi=3D 8195, col=3D3 + * dev=3D7, eventid=3D255 -> lpi=3D 8196, col=3D2 + * Trigger dev2, eventid=3D20 and dev7, eventid=3D255 + * Check both LPIs hit + */ + + its_send_mapd(dev2, true); + its_send_mapd(dev7, true); + + its_send_mapc(col3, true); + its_send_mapc(col2, true); + + its_send_invall(col2); + its_send_invall(col3); + + its_send_mapti(dev2, 8195 /* lpi id */, 20 /* event id */, col3); + its_send_mapti(dev7, 8196 /* lpi id */, 255 /* event id */, col2); + + lpi_stats_expect(3, 8195); + its_send_int(dev2, 20); + check_lpi_stats("dev=3D2, eventid=3D20 -> lpi=3D 8195, col=3D3"); + + lpi_stats_expect(2, 8196); + its_send_int(dev7, 255); + check_lpi_stats("dev=3D7, eventid=3D255 -> lpi=3D 8196, col=3D2"); + + report_prefix_pop(); + + report_prefix_push("inv/invall"); + + /* + * disable 8195, check dev2/eventid=3D20 does not trigger the + * corresponding LPI + */ + gicv3_lpi_set_config(8195, LPI_PROP_DEFAULT & ~LPI_PROP_ENABLED); + its_send_inv(dev2, 20); + + lpi_stats_expect(-1, -1); + its_send_int(dev2, 20); + check_lpi_stats("dev2/eventid=3D20 does not trigger any LPI"); + + /* + * re-enable the LPI but willingly do not call invall + * so the change in config is not taken into account. + * The LPI should not hit + */ + gicv3_lpi_set_config(8195, LPI_PROP_DEFAULT); + lpi_stats_expect(-1, -1); + its_send_int(dev2, 20); + check_lpi_stats("dev2/eventid=3D20 still does not trigger any LPI"); + + /* Now call the invall and check the LPI hits */ + its_send_invall(col3); + lpi_stats_expect(3, 8195); + its_send_int(dev2, 20); + check_lpi_stats("dev2/eventid=3D20 now triggers an LPI"); + + report_prefix_pop(); + + report_prefix_push("mapd valid=3Dfalse"); + /* + * Unmap device 2 and check the eventid 20 formerly + * attached to it does not hit anymore + */ + + its_send_mapd(dev2, false); + lpi_stats_expect(-1, -1); + its_send_int(dev2, 20); + check_lpi_stats("no LPI after device unmap"); + report_prefix_pop(); +} #endif =20 int main(int argc, char **argv) @@ -592,6 +781,10 @@ int main(int argc, char **argv) report_prefix_push(argv[1]); gic_test_mmio(); report_prefix_pop(); + } else if (!strcmp(argv[1], "its-trigger")) { + report_prefix_push(argv[1]); + test_its_trigger(); + report_prefix_pop(); } else if (strcmp(argv[1], "its-introspection") =3D=3D 0) { report_prefix_push(argv[1]); test_its_introspection(); diff --git a/arm/unittests.cfg b/arm/unittests.cfg index 23d378e..b9a7a2c 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -129,6 +129,13 @@ extra_params =3D -machine gic-version=3D3 -append 'i= ts-introspection' groups =3D its arch =3D arm64 =20 +[its-trigger] +file =3D gic.flat +smp =3D $MAX_SMP +extra_params =3D -machine gic-version=3D3 -append 'its-trigger' +groups =3D its +arch =3D arm64 + # Test PSCI emulation [psci] file =3D psci.flat --=20 2.20.1