From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AEDBAC4332D for ; Fri, 20 Mar 2020 09:28:51 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7731420739 for ; Fri, 20 Mar 2020 09:28:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="eBwWxKYe" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7731420739 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:49898 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jFDxS-0004RH-Ks for qemu-devel@archiver.kernel.org; Fri, 20 Mar 2020 05:28:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53533) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jFDu1-0006jg-3b for qemu-devel@nongnu.org; Fri, 20 Mar 2020 05:25:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jFDty-00017m-FT for qemu-devel@nongnu.org; Fri, 20 Mar 2020 05:25:16 -0400 Received: from us-smtp-delivery-74.mimecast.com ([63.128.21.74]:28483) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jFDty-00015M-9y for qemu-devel@nongnu.org; Fri, 20 Mar 2020 05:25:14 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1584696313; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=zbwYQRdnJ0gHuLZ6b4AnrTg2nnXD+s5eXPGTxieqPBU=; b=eBwWxKYe1qvTitvmuNc8k5uGkifsbSAn3bYvKttZJE2FZ9debGjmVVUQelvmybIj2L2kKk T2XamzeH8BtQ69UVHEs5FTdgpl3/Qojp+RiAjJcxF/sKt2s1hsizZA0XoAHMCaDzCqa8VP ekYe07YPcKkIvVkyCSml8Uofbq65ao4= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-354-zaEEvDL9NFq7ELMG1LOSnw-1; Fri, 20 Mar 2020 05:25:12 -0400 X-MC-Unique: zaEEvDL9NFq7ELMG1LOSnw-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 14AE9107ACC4; Fri, 20 Mar 2020 09:25:11 +0000 (UTC) Received: from laptop.redhat.com (ovpn-113-142.ams2.redhat.com [10.36.113.142]) by smtp.corp.redhat.com (Postfix) with ESMTP id DEE755C1D8; Fri, 20 Mar 2020 09:25:07 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org Subject: [kvm-unit-tests PATCH v7 07/13] arm/arm64: ITS: its_enable_defaults Date: Fri, 20 Mar 2020 10:24:22 +0100 Message-Id: <20200320092428.20880-8-eric.auger@redhat.com> In-Reply-To: <20200320092428.20880-1-eric.auger@redhat.com> References: <20200320092428.20880-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 63.128.21.74 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, drjones@redhat.com, andre.przywara@arm.com, thuth@redhat.com, yuzenghui@huawei.com, alexandru.elisei@arm.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" its_enable_defaults() enable LPIs at redistributor level and ITS level. gicv3_enable_defaults must be called before. Signed-off-by: Eric Auger Reviewed-by: Zenghui Yu --- v6 -> v7: - use for_each_present_cpu in its_enable_defaults v5 -> v6: - gicv3_lpi_set/get_config introduced before this patch - dist/redist in commit msg - Added Zenghui's R-b v4 -> v5: - some reformattings moved to earlier patch - add assert(!gicv3_redist_base()) in alloc_lpi_tables() - revert the usage of for_each_present_cpu() v3 -> v4: - use GITS_BASER_INDIRECT & GITS_BASER_VALID in its_setup_baser() - don't parse BASERs again in its_enable_defaults - rename its_setup_baser into its_baser_alloc_table - All allocations moved to the init function - squashed "arm/arm64: gicv3: Enable/Disable LPIs at re-distributor level= " into this patch - introduce gicv3_lpi_rdist_enable and gicv3_lpi_rdist_disable - pend and prop table bases stored as virt addresses - move some init functions from enable() to its_init - removed GICR_PROPBASER_IDBITS_MASK - introduced LPI_OFFSET - lpi_prop becomes u8 * - gicv3_lpi_set_config/get_config became macro - renamed gicv3_lpi_set_pending_table_bit into gicv3_lpi_set_clr_pending v2 -> v3: - introduce its_setup_baser in this patch - squash "arm/arm64: ITS: Init the command queue" in this patch. --- lib/arm/asm/gic-v3.h | 6 ++++++ lib/arm/gic-v3.c | 25 +++++++++++++++++++++++++ lib/arm64/asm/gic-v3-its.h | 1 + lib/arm64/gic-v3-its.c | 13 +++++++++++++ 4 files changed, 45 insertions(+) diff --git a/lib/arm/asm/gic-v3.h b/lib/arm/asm/gic-v3.h index fedffa8..cb72922 100644 --- a/lib/arm/asm/gic-v3.h +++ b/lib/arm/asm/gic-v3.h @@ -57,6 +57,10 @@ #define LPI_PROP_DEFAULT_PRIO 0xa0 #define LPI_PROP_DEFAULT (LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1 | LPI= _PROP_ENABLED) =20 +#define LPI_ID_BASE 8192 +#define LPI(lpi) ((lpi) + LPI_ID_BASE) +#define LPI_OFFSET(intid) ((intid) - LPI_ID_BASE) + #include =20 #ifndef __ASSEMBLY__ @@ -93,6 +97,8 @@ extern void gicv3_ipi_send_mask(int irq, const cpumask_= t *dest); extern void gicv3_set_redist_base(size_t stride); extern void gicv3_lpi_set_clr_pending(int rdist, int n, bool set); extern void gicv3_lpi_alloc_tables(void); +extern void gicv3_lpi_rdist_enable(int redist); +extern void gicv3_lpi_rdist_disable(int redist); =20 static inline void gicv3_do_wait_for_rwp(void *base) { diff --git a/lib/arm/gic-v3.c b/lib/arm/gic-v3.c index 6cf1d1d..a7e2cb8 100644 --- a/lib/arm/gic-v3.c +++ b/lib/arm/gic-v3.c @@ -199,4 +199,29 @@ void gicv3_lpi_set_clr_pending(int rdist, int n, boo= l set) byte &=3D ~mask; *ptr =3D byte; } + +static void gicv3_lpi_rdist_ctrl(u32 redist, bool set) +{ + void *ptr; + u64 val; + + assert(redist < nr_cpus); + + ptr =3D gicv3_data.redist_base[redist]; + val =3D readl(ptr + GICR_CTLR); + if (set) + val |=3D GICR_CTLR_ENABLE_LPIS; + else + val &=3D ~GICR_CTLR_ENABLE_LPIS; + writel(val, ptr + GICR_CTLR); +} + +void gicv3_lpi_rdist_enable(int redist) +{ + gicv3_lpi_rdist_ctrl(redist, true); +} +void gicv3_lpi_rdist_disable(int redist) +{ + gicv3_lpi_rdist_ctrl(redist, false); +} #endif /* __aarch64__ */ diff --git a/lib/arm64/asm/gic-v3-its.h b/lib/arm64/asm/gic-v3-its.h index 30f2d90..4683011 100644 --- a/lib/arm64/asm/gic-v3-its.h +++ b/lib/arm64/asm/gic-v3-its.h @@ -92,5 +92,6 @@ extern struct its_data its_data; extern void its_parse_typer(void); extern void its_init(void); extern int its_baser_lookup(int i, struct its_baser *baser); +extern void its_enable_defaults(void); =20 #endif /* _ASMARM64_GIC_V3_ITS_H_ */ diff --git a/lib/arm64/gic-v3-its.c b/lib/arm64/gic-v3-its.c index fb8e3f2..afc66a3 100644 --- a/lib/arm64/gic-v3-its.c +++ b/lib/arm64/gic-v3-its.c @@ -96,3 +96,16 @@ void its_init(void) its_cmd_queue_init(); } =20 +/* must be called after gicv3_enable_defaults */ +void its_enable_defaults(void) +{ + int cpu; + + /* Allocate LPI config and pending tables */ + gicv3_lpi_alloc_tables(); + + for_each_present_cpu(cpu) + gicv3_lpi_rdist_enable(cpu); + + writel(GITS_CTLR_ENABLE, its_data.base + GITS_CTLR); +} --=20 2.20.1