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Wed, 25 Mar 2020 08:12:09 -0700 (PDT) Date: Wed, 25 Mar 2020 11:12:05 -0400 From: Peter Xu To: "Liu, Yi L" Subject: Re: [PATCH v1 17/22] intel_iommu: do not pass down pasid bind for PASID #0 Message-ID: <20200325151205.GD354390@xz-x1> References: <1584880579-12178-1-git-send-email-yi.l.liu@intel.com> <1584880579-12178-18-git-send-email-yi.l.liu@intel.com> <20200324181326.GB127076@xz-x1> MIME-Version: 1.0 In-Reply-To: X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 216.205.24.74 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "jean-philippe@linaro.org" , "Tian, Kevin" , Jacob Pan , Yi Sun , Eduardo Habkost , "kvm@vger.kernel.org" , "mst@redhat.com" , "Tian, Jun J" , "qemu-devel@nongnu.org" , "eric.auger@redhat.com" , "alex.williamson@redhat.com" , "pbonzini@redhat.com" , "Wu, Hao" , "Sun, Yi Y" , Richard Henderson , "david@gibson.dropbear.id.au" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Wed, Mar 25, 2020 at 10:42:25AM +0000, Liu, Yi L wrote: > > From: Peter Xu < peterx@redhat.com> > > Sent: Wednesday, March 25, 2020 2:13 AM > > To: Liu, Yi L > > Subject: Re: [PATCH v1 17/22] intel_iommu: do not pass down pasid bind = for PASID > > #0 > >=20 > > On Sun, Mar 22, 2020 at 05:36:14AM -0700, Liu Yi L wrote: > > > RID_PASID field was introduced in VT-d 3.0 spec, it is used for DMA > > > requests w/o PASID in scalable mode VT-d. It is also known as IOVA. > > > And in VT-d 3.1 spec, there is definition on it: > > > > > > "Implementations not supporting RID_PASID capability (ECAP_REG.RPS is > > > 0b), use a PASID value of 0 to perform address translation for > > > requests without PASID." > > > > > > This patch adds a check against the PASIDs which are going to be boun= d > > > to device. For PASID #0, it is not necessary to pass down pasid bind > > > request for it since PASID #0 is used as RID_PASID for DMA requests > > > without pasid. Further reason is current Intel vIOMMU supports gIOVA > > > by shadowing guest 2nd level page table. However, in future, if guest > > > IOMMU driver uses 1st level page table to store IOVA mappings, then > > > guest IOVA support will also be done via nested translation. When > > > gIOVA is over FLPT, then vIOMMU should pass down the pasid bind > > > request for PASID #0 to host, host needs to bind the guest IOVA page > > > table to a proper PASID. e.g PASID value in RID_PASID field for PF/VF > > > if ECAP_REG.RPS is clear or default PASID for ADI (Assignable Device > > > Interface in Scalable IOV solution). > > > > > > IOVA over FLPT support on Intel VT-d: > > > https://lkml.org/lkml/2019/9/23/297 > > > > > > Cc: Kevin Tian > > > Cc: Jacob Pan > > > Cc: Peter Xu > > > Cc: Yi Sun > > > Cc: Paolo Bonzini > > > Cc: Richard Henderson > > > Cc: Eduardo Habkost > > > Signed-off-by: Liu Yi L > > > --- > > > hw/i386/intel_iommu.c | 10 ++++++++++ > > > 1 file changed, 10 insertions(+) > > > > > > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index > > > 1e0ccde..b007715 100644 > > > --- a/hw/i386/intel_iommu.c > > > +++ b/hw/i386/intel_iommu.c > > > @@ -1886,6 +1886,16 @@ static int vtd_bind_guest_pasid(IntelIOMMUStat= e *s, > > VTDBus *vtd_bus, > > > struct iommu_gpasid_bind_data *g_bind_data; > > > int ret =3D -1; > > > > > > + if (pasid < VTD_MIN_HPASID) { > > > + /* > > > + * If pasid < VTD_HPASID_MIN, this pasid is not allocated > >=20 > > s/VTD_HPASID_MIN/VTD_MIN_HPASID/. >=20 > Got it. >=20 > >=20 > > > + * from host. No need to pass down the changes on it to host= . > > > + * TODO: when IOVA over FLPT is ready, this switch should be > > > + * refined. > >=20 > > What will happen if without this patch? Is it a must? >=20 > Before gIOVA is supported by nested translation, it is a must. This requi= res > IOVA over 1st level page table is ready in guest kernel, also requires th= e > QEMU/VFIO supports to bind the guest IOVA page table to host. > Currently, guest kernel side is ready. However, QEMU and VFIO side is > not. OK: Reviewed-by: Peter Xu --=20 Peter Xu