From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Paul Burton" <pburton@wavecomp.com>,
"Sagar Karandikar" <sagark@eecs.berkeley.edu>,
"Michael S. Tsirkin" <mst@redhat.com>,
"Jason Wang" <jasowang@redhat.com>,
"Mark Cave-Ayland" <mark.cave-ayland@ilande.co.uk>,
"Alistair Francis" <Alistair.Francis@wdc.com>,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Markus Armbruster" <armbru@redhat.com>,
"Aleksandar Markovic" <aleksandar.qemu.devel@gmail.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Aleksandar Rikalo" <aleksandar.rikalo@rt-rk.com>,
"Richard Henderson" <rth@twiddle.net>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>,
"Eduardo Habkost" <ehabkost@redhat.com>,
"Alistair Francis" <alistair@alistair23.me>,
qemu-arm@nongnu.org, "David Gibson" <david@gibson.dropbear.id.au>,
qemu-riscv@nongnu.org,
"Bastian Koppelmann" <kbastian@mail.uni-paderborn.de>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Andrew Baumann" <Andrew.Baumann@microsoft.com>,
"Jean-Christophe Dubois" <jcd@tribudubois.net>,
qemu-ppc@nongnu.org, "Paolo Bonzini" <pbonzini@redhat.com>,
"Aurelien Jarno" <aurelien@aurel32.net>
Subject: [PATCH-for-5.0 12/12] hw/riscv/sifive_u: Add missing error-propagation code
Date: Wed, 25 Mar 2020 20:18:30 +0100 [thread overview]
Message-ID: <20200325191830.16553-13-f4bug@amsat.org> (raw)
In-Reply-To: <20200325191830.16553-1-f4bug@amsat.org>
Running the coccinelle script produced:
$ spatch \
--macro-file scripts/cocci-macro-file.h --include-headers \
--sp-file scripts/coccinelle/object_property_missing_error_propagate.cocci \
--keep-comments --smpl-spacing --dir hw
[[manual check required: error_propagate() might be missing in object_property_set_bool() hw/riscv/sifive_u.c:558:4]]
[[manual check required: error_propagate() might be missing in object_property_set_bool() hw/riscv/sifive_u.c:561:4]]
Add the missing error_propagate() after manual review.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/riscv/sifive_u.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 56351c4faa..01e44018cd 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -473,113 +473,121 @@ static void riscv_sifive_u_machine_instance_init(Object *obj)
static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
{
MachineState *ms = MACHINE(qdev_get_machine());
SiFiveUSoCState *s = RISCV_U_SOC(dev);
const struct MemmapEntry *memmap = sifive_u_memmap;
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES];
char *plic_hart_config;
size_t plic_hart_config_len;
int i;
Error *err = NULL;
NICInfo *nd = &nd_table[0];
object_property_set_bool(OBJECT(&s->e_cpus), true, "realized",
&error_abort);
object_property_set_bool(OBJECT(&s->u_cpus), true, "realized",
&error_abort);
/*
* The cluster must be realized after the RISC-V hart array container,
* as the container's CPU object is only created on realize, and the
* CPU must exist and have been parented into the cluster before the
* cluster is realized.
*/
object_property_set_bool(OBJECT(&s->e_cluster), true, "realized",
&error_abort);
object_property_set_bool(OBJECT(&s->u_cluster), true, "realized",
&error_abort);
/* boot rom */
memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom",
memmap[SIFIVE_U_MROM].size, &error_fatal);
memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base,
mask_rom);
/*
* Add L2-LIM at reset size.
* This should be reduced in size as the L2 Cache Controller WayEnable
* register is incremented. Unfortunately I don't see a nice (or any) way
* to handle reducing or blocking out the L2 LIM while still allowing it
* be re returned to all enabled after a reset. For the time being, just
* leave it enabled all the time. This won't break anything, but will be
* too generous to misbehaving guests.
*/
memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim",
memmap[SIFIVE_U_L2LIM].size, &error_fatal);
memory_region_add_subregion(system_memory, memmap[SIFIVE_U_L2LIM].base,
l2lim_mem);
/* create PLIC hart topology configuration string */
plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) *
ms->smp.cpus;
plic_hart_config = g_malloc0(plic_hart_config_len);
for (i = 0; i < ms->smp.cpus; i++) {
if (i != 0) {
strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG,
plic_hart_config_len);
} else {
strncat(plic_hart_config, "M", plic_hart_config_len);
}
plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1);
}
/* MMIO */
s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base,
plic_hart_config,
SIFIVE_U_PLIC_NUM_SOURCES,
SIFIVE_U_PLIC_NUM_PRIORITIES,
SIFIVE_U_PLIC_PRIORITY_BASE,
SIFIVE_U_PLIC_PENDING_BASE,
SIFIVE_U_PLIC_ENABLE_BASE,
SIFIVE_U_PLIC_ENABLE_STRIDE,
SIFIVE_U_PLIC_CONTEXT_BASE,
SIFIVE_U_PLIC_CONTEXT_STRIDE,
memmap[SIFIVE_U_PLIC].size);
g_free(plic_hart_config);
sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
memmap[SIFIVE_U_CLINT].size, ms->smp.cpus,
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
object_property_set_bool(OBJECT(&s->prci), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base);
object_property_set_bool(OBJECT(&s->otp), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base);
for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) {
plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i);
}
if (nd->used) {
qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
qdev_set_nic_properties(DEVICE(&s->gem), nd);
}
object_property_set_int(OBJECT(&s->gem), GEM_REVISION, "revision",
&error_abort);
object_property_set_bool(OBJECT(&s->gem), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
plic_gpios[SIFIVE_U_GEM_IRQ]);
create_unimplemented_device("riscv.sifive.u.gem-mgmt",
memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
}
--
2.21.1
next prev parent reply other threads:[~2020-03-25 19:29 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-25 19:18 [PATCH-for-5.0 00/12] hw: Add missing error-propagation code Philippe Mathieu-Daudé
2020-03-25 19:18 ` [PATCH-for-5.0 01/12] scripts/coccinelle: Add script to catch missing error_propagate() calls Philippe Mathieu-Daudé
2020-03-26 21:32 ` Peter Maydell
2020-03-25 19:18 ` [PATCH-for-5.0 02/12] hw/arm/bcm2835_peripherals: Add missing error-propagation code Philippe Mathieu-Daudé
2020-03-26 21:34 ` Peter Maydell
2020-03-25 19:18 ` [PATCH-for-5.0 03/12] hw/arm/fsl-imx: " Philippe Mathieu-Daudé
2020-03-26 21:35 ` Peter Maydell
2020-03-25 19:18 ` [PATCH-for-5.0 04/12] hw/arm/stm32fx05_soc: " Philippe Mathieu-Daudé
2020-03-25 20:51 ` Alistair Francis
2020-03-26 21:45 ` Peter Maydell
2020-03-25 19:18 ` [PATCH-for-5.0 05/12] hw/i386/x86: " Philippe Mathieu-Daudé
2020-03-26 21:38 ` Peter Maydell
2020-03-25 19:18 ` [PATCH-for-5.0 06/12] hw/dma/xilinx_axidma: " Philippe Mathieu-Daudé
2020-03-25 20:52 ` Alistair Francis
2020-03-26 21:46 ` Peter Maydell
2020-03-25 19:18 ` [PATCH-for-5.0 07/12] hw/mips/cps: " Philippe Mathieu-Daudé
2020-03-26 21:43 ` Peter Maydell
2020-03-26 22:48 ` Aleksandar Markovic
2020-03-25 19:18 ` [PATCH-for-5.0 08/12] hw/mips/boston: " Philippe Mathieu-Daudé
2020-03-26 21:47 ` Peter Maydell
2020-03-26 22:50 ` Aleksandar Markovic
2020-03-25 19:18 ` [PATCH-for-5.0 09/12] hw/mips/mips_malta: " Philippe Mathieu-Daudé
2020-03-26 21:49 ` Peter Maydell
2020-03-26 22:49 ` Aleksandar Markovic
2020-03-25 19:18 ` [PATCH-for-5.0 10/12] hw/misc/macio/macio: " Philippe Mathieu-Daudé
2020-03-25 23:55 ` David Gibson
2020-03-26 21:50 ` Peter Maydell
2020-03-25 19:18 ` [PATCH-for-5.0 11/12] hw/net/xilinx_axienet: " Philippe Mathieu-Daudé
2020-03-25 20:52 ` Alistair Francis
2020-03-26 21:51 ` Peter Maydell
2020-03-25 19:18 ` Philippe Mathieu-Daudé [this message]
2020-03-25 20:52 ` [PATCH-for-5.0 12/12] hw/riscv/sifive_u: " Alistair Francis
2020-03-26 21:55 ` Peter Maydell
2020-03-31 17:02 ` Philippe Mathieu-Daudé
2020-03-31 17:03 ` Peter Maydell
2020-03-25 19:20 ` [PATCH-for-5.0 00/12] hw: " Philippe Mathieu-Daudé
2020-03-30 9:21 ` Stefan Hajnoczi
2020-04-06 17:47 ` Philippe Mathieu-Daudé
2020-03-31 13:23 ` Markus Armbruster
2020-04-03 17:53 ` Philippe Mathieu-Daudé
2020-04-04 5:55 ` Markus Armbruster
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