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[109.66.7.121]) by smtp.gmail.com with ESMTPSA id 91sm29026681wra.37.2020.04.28.13.45.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Apr 2020 13:45:16 -0700 (PDT) Date: Tue, 28 Apr 2020 16:45:13 -0400 From: "Michael S. Tsirkin" To: Ani Sinha Subject: Re: [PATCH V2] Add a new PIIX option to control PCI hot unplugging of devices on non-root buses Message-ID: <20200428164428-mutt-send-email-mst@kernel.org> References: <1588069012-211196-1-git-send-email-ani.sinha@nutanix.com> <20200428120426-mutt-send-email-mst@kernel.org> <67e481a5-de04-4e01-b9ec-70932194d69f@Spark> <20200428121837-mutt-send-email-mst@kernel.org> MIME-Version: 1.0 In-Reply-To: X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Received-SPF: pass client-ip=205.139.110.120; envelope-from=mst@redhat.com; helo=us-smtp-1.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/28 02:16:38 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] X-Received-From: 205.139.110.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ani Sinha , Eduardo Habkost , qemu-devel@nongnu.org, Aleksandar Markovic , Paolo Bonzini , Igor Mammedov , Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, Apr 28, 2020 at 10:10:18PM +0530, Ani Sinha wrote: >=20 >=20 > On Tue, Apr 28, 2020 at 9:51 PM Michael S. Tsirkin wrote= : >=20 > On Tue, Apr 28, 2020 at 09:39:16PM +0530, Ani Sinha wrote: > > > > Ani > > On Apr 28, 2020, 21:35 +0530, Michael S. Tsirkin , = wrote: > > > >=A0 =A0 =A0On Tue, Apr 28, 2020 at 10:16:52AM +0000, Ani Sinha wrote= : > > > >=A0 =A0 =A0 =A0 =A0A new option "use_acpi_unplug" is introduced for = PIIX which will > >=A0 =A0 =A0 =A0 =A0selectively only disable hot unplugging of both h= ot plugged and > >=A0 =A0 =A0 =A0 =A0cold plugged PCI devices on non-root PCI buses. T= his will prevent > >=A0 =A0 =A0 =A0 =A0hot unplugging of devices from Windows based gues= ts from system > >=A0 =A0 =A0 =A0 =A0tray but will not prevent devices from being hot = plugged into the > >=A0 =A0 =A0 =A0 =A0guest. > > > >=A0 =A0 =A0 =A0 =A0It has been tested on Windows guests. > > > >=A0 =A0 =A0 =A0 =A0Signed-off-by: Ani Sinha > > > > > >=A0 =A0 =A0It's still a non starter until we find something similar = for PCIE and > >=A0 =A0 =A0SHPC. Do guests check command status? Can some unplug com= mands fail? > > > > > > Ok I=A0 give up! I thought we debated this on the other thread. >=20 > Sorry to hear that. > I'd rather you didn't, and worked on a solution that works for everyo= ne. >=20 >=20 > That is extremely hard for one person to do, without inputs and ideas fro= m the > community. What kind of input are you looking for? > Satisfying the entire world requires lot of time and energy > investment, not to mention a broad expertise in multiple technologies.=A0 >=20 >=20 >=20 > Pushing back on merging code is unfortunately the only mechanism > maintainers have to make sure features are complete and > orthogonal to each other, so I'm not sure I can help otherwise. >=20 > > > > > > > > > >=A0 =A0 =A0 =A0 =A0--- > >=A0 =A0 =A0 =A0 =A0hw/acpi/piix4.c | 3 +++ > >=A0 =A0 =A0 =A0 =A0hw/i386/acpi-build.c | 40 > ++++++++++++++++++++++++++-------------- > >=A0 =A0 =A0 =A0 =A02 files changed, 29 insertions(+), 14 deletions(-= ) > > > >=A0 =A0 =A0 =A0 =A0diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c > >=A0 =A0 =A0 =A0 =A0index 964d6f5..59fa707 100644 > >=A0 =A0 =A0 =A0 =A0--- a/hw/acpi/piix4.c > >=A0 =A0 =A0 =A0 =A0+++ b/hw/acpi/piix4.c > >=A0 =A0 =A0 =A0 =A0@@ -78,6 +78,7 @@ typedef struct PIIX4PMState { > > > >=A0 =A0 =A0 =A0 =A0AcpiPciHpState acpi_pci_hotplug; > >=A0 =A0 =A0 =A0 =A0bool use_acpi_pci_hotplug; > >=A0 =A0 =A0 =A0 =A0+ bool use_acpi_unplug; > > > >=A0 =A0 =A0 =A0 =A0uint8_t disable_s3; > >=A0 =A0 =A0 =A0 =A0uint8_t disable_s4; > >=A0 =A0 =A0 =A0 =A0@@ -633,6 +634,8 @@ static Property piix4_pm_prop= erties[] =3D { > >=A0 =A0 =A0 =A0 =A0DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMSta= te, s4_val, 2), > >=A0 =A0 =A0 =A0 =A0DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-su= pport", > PIIX4PMState, > >=A0 =A0 =A0 =A0 =A0use_acpi_pci_hotplug, true), > >=A0 =A0 =A0 =A0 =A0+ DEFINE_PROP_BOOL("acpi-pci-hotunplug-enable-bri= dge", > PIIX4PMState, > >=A0 =A0 =A0 =A0 =A0+ use_acpi_unplug, true), > >=A0 =A0 =A0 =A0 =A0DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4P= MState, > >=A0 =A0 =A0 =A0 =A0acpi_memory_hotplug.is_enabled, true), > >=A0 =A0 =A0 =A0 =A0DEFINE_PROP_END_OF_LIST(), > >=A0 =A0 =A0 =A0 =A0diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-= build.c > >=A0 =A0 =A0 =A0 =A0index 23c77ee..71b3ac3 100644 > >=A0 =A0 =A0 =A0 =A0--- a/hw/i386/acpi-build.c > >=A0 =A0 =A0 =A0 =A0+++ b/hw/i386/acpi-build.c > >=A0 =A0 =A0 =A0 =A0@@ -96,6 +96,7 @@ typedef struct AcpiPmInfo { > >=A0 =A0 =A0 =A0 =A0bool s3_disabled; > >=A0 =A0 =A0 =A0 =A0bool s4_disabled; > >=A0 =A0 =A0 =A0 =A0bool pcihp_bridge_en; > >=A0 =A0 =A0 =A0 =A0+ bool pcihup_bridge_en; > >=A0 =A0 =A0 =A0 =A0uint8_t s4_val; > >=A0 =A0 =A0 =A0 =A0AcpiFadtData fadt; > >=A0 =A0 =A0 =A0 =A0uint16_t cpu_hp_io_base; > >=A0 =A0 =A0 =A0 =A0@@ -240,6 +241,9 @@ static void acpi_get_pm_info(= MachineState > *machine, > >=A0 =A0 =A0 =A0 =A0AcpiPmInfo *pm) > >=A0 =A0 =A0 =A0 =A0pm->pcihp_bridge_en =3D > >=A0 =A0 =A0 =A0 =A0object_property_get_bool(obj, > "acpi-pci-hotplug-with-bridge-support", > >=A0 =A0 =A0 =A0 =A0NULL); > >=A0 =A0 =A0 =A0 =A0+ pm->pcihup_bridge_en =3D > >=A0 =A0 =A0 =A0 =A0+ object_property_get_bool(obj, > "acpi-pci-hotunplug-enable-bridge", > >=A0 =A0 =A0 =A0 =A0+ NULL); > >=A0 =A0 =A0 =A0 =A0} > > > >=A0 =A0 =A0 =A0 =A0static void acpi_get_misc_info(AcpiMiscInfo *info= ) > >=A0 =A0 =A0 =A0 =A0@@ -451,7 +455,8 @@ static void build_append_pcih= p_notify_entry > (Aml > >=A0 =A0 =A0 =A0 =A0*method, int slot) > >=A0 =A0 =A0 =A0 =A0} > > > >=A0 =A0 =A0 =A0 =A0static void build_append_pci_bus_devices(Aml *par= ent_scope, > PCIBus > >=A0 =A0 =A0 =A0 =A0*bus, > >=A0 =A0 =A0 =A0 =A0- bool pcihp_bridge_en) > >=A0 =A0 =A0 =A0 =A0+ bool pcihp_bridge_en, > >=A0 =A0 =A0 =A0 =A0+ bool pcihup_bridge_en) > >=A0 =A0 =A0 =A0 =A0{ > >=A0 =A0 =A0 =A0 =A0Aml *dev, *notify_method =3D NULL, *method; > >=A0 =A0 =A0 =A0 =A0QObject *bsel; > >=A0 =A0 =A0 =A0 =A0@@ -479,11 +484,14 @@ static void build_append_pc= i_bus_devices > (Aml > >=A0 =A0 =A0 =A0 =A0*parent_scope, PCIBus *bus, > >=A0 =A0 =A0 =A0 =A0dev =3D aml_device("S%.02X", PCI_DEVFN(slot, 0)); > >=A0 =A0 =A0 =A0 =A0aml_append(dev, aml_name_decl("_SUN", aml_int(slo= t))); > >=A0 =A0 =A0 =A0 =A0aml_append(dev, aml_name_decl("_ADR", aml_int(slo= t << 16))); > >=A0 =A0 =A0 =A0 =A0- method =3D aml_method("_EJ0", 1, AML_NOTSERIALI= ZED); > >=A0 =A0 =A0 =A0 =A0- aml_append(method, > >=A0 =A0 =A0 =A0 =A0- aml_call2("PCEJ", aml_name("BSEL"), aml_name("_= SUN")) > >=A0 =A0 =A0 =A0 =A0- ); > >=A0 =A0 =A0 =A0 =A0- aml_append(dev, method); > >=A0 =A0 =A0 =A0 =A0+ if (pcihup_bridge_en || pci_bus_is_root(bus)) { > >=A0 =A0 =A0 =A0 =A0+ method =3D aml_method("_EJ0", 1, AML_NOTSERIALI= ZED); > >=A0 =A0 =A0 =A0 =A0+ aml_append(method, > >=A0 =A0 =A0 =A0 =A0+ aml_call2("PCEJ", aml_name("BSEL"), > >=A0 =A0 =A0 =A0 =A0+ aml_name("_SUN")) > >=A0 =A0 =A0 =A0 =A0+ ); > >=A0 =A0 =A0 =A0 =A0+ aml_append(dev, method); > >=A0 =A0 =A0 =A0 =A0+ } > >=A0 =A0 =A0 =A0 =A0aml_append(parent_scope, dev); > > > >=A0 =A0 =A0 =A0 =A0build_append_pcihp_notify_entry(notify_method, sl= ot); > >=A0 =A0 =A0 =A0 =A0@@ -537,12 +545,14 @@ static void build_append_pc= i_bus_devices > (Aml > >=A0 =A0 =A0 =A0 =A0*parent_scope, PCIBus *bus, > >=A0 =A0 =A0 =A0 =A0/* add _SUN/_EJ0 to make slot hotpluggable */ > >=A0 =A0 =A0 =A0 =A0aml_append(dev, aml_name_decl("_SUN", aml_int(slo= t))); > > > >=A0 =A0 =A0 =A0 =A0- method =3D aml_method("_EJ0", 1, AML_NOTSERIALI= ZED); > >=A0 =A0 =A0 =A0 =A0- aml_append(method, > >=A0 =A0 =A0 =A0 =A0- aml_call2("PCEJ", aml_name("BSEL"), aml_name("_= SUN")) > >=A0 =A0 =A0 =A0 =A0- ); > >=A0 =A0 =A0 =A0 =A0- aml_append(dev, method); > >=A0 =A0 =A0 =A0 =A0- > >=A0 =A0 =A0 =A0 =A0+ if (pcihup_bridge_en || pci_bus_is_root(bus)) { > >=A0 =A0 =A0 =A0 =A0+ method =3D aml_method("_EJ0", 1, AML_NOTSERIALI= ZED); > >=A0 =A0 =A0 =A0 =A0+ aml_append(method, > >=A0 =A0 =A0 =A0 =A0+ aml_call2("PCEJ", aml_name("BSEL"), > >=A0 =A0 =A0 =A0 =A0+ aml_name("_SUN")) > >=A0 =A0 =A0 =A0 =A0+ ); > >=A0 =A0 =A0 =A0 =A0+ aml_append(dev, method); > >=A0 =A0 =A0 =A0 =A0+ } > >=A0 =A0 =A0 =A0 =A0if (bsel) { > >=A0 =A0 =A0 =A0 =A0build_append_pcihp_notify_entry(notify_method, sl= ot); > >=A0 =A0 =A0 =A0 =A0} > >=A0 =A0 =A0 =A0 =A0@@ -553,7 +563,8 @@ static void build_append_pci_= bus_devices(Aml > >=A0 =A0 =A0 =A0 =A0*parent_scope, PCIBus *bus, > >=A0 =A0 =A0 =A0 =A0*/ > >=A0 =A0 =A0 =A0 =A0PCIBus *sec_bus =3D pci_bridge_get_sec_bus(PCI_BR= IDGE(pdev)); > > > >=A0 =A0 =A0 =A0 =A0- build_append_pci_bus_devices(dev, sec_bus, pcih= p_bridge_en); > >=A0 =A0 =A0 =A0 =A0+ build_append_pci_bus_devices(dev, sec_bus, pcih= p_bridge_en, > >=A0 =A0 =A0 =A0 =A0+ pcihup_bridge_en); > >=A0 =A0 =A0 =A0 =A0} > >=A0 =A0 =A0 =A0 =A0/* slot descriptor has been composed, add it into= parent context > */ > >=A0 =A0 =A0 =A0 =A0aml_append(parent_scope, dev); > >=A0 =A0 =A0 =A0 =A0@@ -2196,7 +2207,8 @@ build_dsdt(GArray *table_da= ta, BIOSLinker > >=A0 =A0 =A0 =A0 =A0*linker, > >=A0 =A0 =A0 =A0 =A0if (bus) { > >=A0 =A0 =A0 =A0 =A0Aml *scope =3D aml_scope("PCI0"); > >=A0 =A0 =A0 =A0 =A0/* Scan all PCI buses. Generate tables to support= hotplug. */ > >=A0 =A0 =A0 =A0 =A0- build_append_pci_bus_devices(scope, bus, pm->pc= ihp_bridge_en); > >=A0 =A0 =A0 =A0 =A0+ build_append_pci_bus_devices(scope, bus, pm->pc= ihp_bridge_en, > >=A0 =A0 =A0 =A0 =A0+ pm->pcihup_bridge_en); > > > >=A0 =A0 =A0 =A0 =A0if (TPM_IS_TIS_ISA(tpm)) { > >=A0 =A0 =A0 =A0 =A0if (misc->tpm_version =3D=3D TPM_VERSION_2_0) { > >=A0 =A0 =A0 =A0 =A0-- > >=A0 =A0 =A0 =A0 =A01.9.4 > > > > > > >=20 >=20