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[109.66.7.121]) by smtp.gmail.com with ESMTPSA id 1sm4679753wmi.0.2020.05.06.13.25.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 May 2020 13:25:44 -0700 (PDT) Date: Wed, 6 May 2020 16:25:41 -0400 From: "Michael S. Tsirkin" To: gengdongjiu Subject: Re: [PATCH v25 00/10] Add ARMv8 RAS virtualization support in QEMU Message-ID: <20200506162439-mutt-send-email-mst@kernel.org> References: <20200410114639.32844-1-gengdongjiu@huawei.com> MIME-Version: 1.0 In-Reply-To: X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Received-SPF: pass client-ip=205.139.110.61; envelope-from=mst@redhat.com; helo=us-smtp-delivery-1.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/06 05:50:09 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Peter Maydell , Xiao Guangrong , kvm-devel , Igor Mammedov , Marcelo Tosatti , QEMU Developers , Linuxarm , Shannon Zhao , Zheng Xiang , qemu-arm , Jonathan Cameron , Paolo Bonzini , Richard Henderson , Eduardo Habkost Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Wed, May 06, 2020 at 07:42:19PM +0800, gengdongjiu wrote: > On 2020/4/17 21:32, Peter Maydell wrote: > > On Fri, 10 Apr 2020 at 12:46, Dongjiu Geng wro= te: > >> > >> In the ARMv8 platform, the CPU error types includes synchronous extern= al abort(SEA) > >> and SError Interrupt (SEI). If exception happens in guest, host does n= ot know the detailed > >> information of guest, so it is expected that guest can do the recovery= . For example, if an > >> exception happens in a guest user-space application, host does not kno= w which application > >> encounters errors, only guest knows it. > >> > >> For the ARMv8 SEA/SEI, KVM or host kernel delivers SIGBUS to notify us= erspace. > >> After user space gets the notification, it will record the CPER into g= uest GHES > >> buffer and inject an exception or IRQ to guest. > >> > >> In the current implementation, if the type of SIGBUS is BUS_MCEERR_AR,= we will > >> treat it as a synchronous exception, and notify guest with ARMv8 SEA > >> notification type after recording CPER into guest. > >=20 > > Hi. I left a comment on patch 1. The other 3 patches unreviewed > > are 5, 6 and 8, which are all ACPI core code, so that's for > > MST, Igor or Shannon to review. > >=20 > > Once those have been reviewed, please ping me if you want this > > to go via target-arm.next. >=20 > Hi Peter, > Igor have reviewed all ACPI core code. whether you can apply this seri= es to target-arm.next I can make another patches to solve your comments on = patch1 and another APCI comment. > Thanks very much in advance. Given it all starts with patch 1, it's probably easier to address the comment and repost. > >=20 > > thanks > > -- PMM > >=20 > > . > >=20