* [PATCH 0/1] tricore: added AURIX TC277 D-Step TriBoard
@ 2020-05-11 12:21 David Brenken
2020-05-11 12:21 ` [PATCH 1/1] " David Brenken
0 siblings, 1 reply; 6+ messages in thread
From: David Brenken @ 2020-05-11 12:21 UTC (permalink / raw)
To: qemu-devel; +Cc: kbastian, Andreas Konopik
From: Andreas Konopik <andreas.konopik@efs-auto.de>
Hello everyone,
this patch adds the AURIX TC277 D-Step TriBoard as QEMU machine
(-M AURIX_TriBoard_TC277D). Memory maps are implemented according to the the
"AURIX TC27x D-Step User's Manual V2.2 2014-12". AURIX memory layouts normally
are specified by the processor, so this machine should not be used with any
other cpu than the "tc27x".
Andreas Konopik (1):
tricore: added AURIX TC277 D-Step TriBoard
hw/tricore/Makefile.objs | 1 +
hw/tricore/aurix_triboard_tc277d.c | 240 +++++++++++++++++++++++++++++
2 files changed, 241 insertions(+)
create mode 100644 hw/tricore/aurix_triboard_tc277d.c
--
2.26.0
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/1] tricore: added AURIX TC277 D-Step TriBoard
2020-05-11 12:21 [PATCH 0/1] tricore: added AURIX TC277 D-Step TriBoard David Brenken
@ 2020-05-11 12:21 ` David Brenken
2020-05-11 13:48 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 6+ messages in thread
From: David Brenken @ 2020-05-11 12:21 UTC (permalink / raw)
To: qemu-devel
Cc: kbastian, Lars Biermanski, Georg Hofstetter, David Brenken,
Robert Rasche, Andreas Konopik
From: Andreas Konopik <andreas.konopik@efs-auto.de>
Signed-off-by: Andreas Konopik <andreas.konopik@efs-auto.de>
Signed-off-by: David Brenken <david.brenken@efs-auto.de>
Signed-off-by: Georg Hofstetter <georg.hofstetter@efs-auto.de>
Signed-off-by: Robert Rasche <robert.rasche@efs-auto.de>
Signed-off-by: Lars Biermanski <lars.biermanski@efs-auto.de>
---
hw/tricore/Makefile.objs | 1 +
hw/tricore/aurix_triboard_tc277d.c | 240 +++++++++++++++++++++++++++++
2 files changed, 241 insertions(+)
create mode 100644 hw/tricore/aurix_triboard_tc277d.c
diff --git a/hw/tricore/Makefile.objs b/hw/tricore/Makefile.objs
index 5501f6c1a8..e4a2106dd9 100644
--- a/hw/tricore/Makefile.objs
+++ b/hw/tricore/Makefile.objs
@@ -1 +1,2 @@
obj-$(CONFIG_TRICORE) += tricore_testboard.o
+obj-$(CONFIG_TRICORE) += aurix_triboard_tc277d.o
diff --git a/hw/tricore/aurix_triboard_tc277d.c b/hw/tricore/aurix_triboard_tc277d.c
new file mode 100644
index 0000000000..86deff9a50
--- /dev/null
+++ b/hw/tricore/aurix_triboard_tc277d.c
@@ -0,0 +1,240 @@
+/*
+ * Infineon AURIX TC277 D-Step TriBoard System emulation.
+ *
+ * Copyright (c) 2019 Andreas Konopik <andreas.konopik@efs-auto.de>
+ * Copyright (c) 2019 David Brenken <david.brenken@efs-auto.de>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "qapi/error.h"
+#include "hw/qdev-properties.h"
+#include "cpu.h"
+#include "net/net.h"
+#include "hw/boards.h"
+#include "hw/loader.h"
+#include "exec/address-spaces.h"
+#include "elf.h"
+#include "hw/tricore/tricore.h"
+#include "qemu/error-report.h"
+
+/*
+ * The TriCore processor architecture defines their respective on-chip memory
+ * layout. Therefore, in contrast to other common architectures, the QEMU
+ * TriCore machine and cpu are closely coupled.
+ *
+ * Memory maps are aligned with the TC27x D-Step Microcontroller layout.
+ */
+
+#define TC27XD_MEMMAP_DSPR2 0x50000000
+#define TC27XD_MEMMAP_DCACHE2 0x5001E000
+#define TC27XD_MEMMAP_DTAG2 0x500C0000
+#define TC27XD_MEMMAP_PSPR2 0x50100000
+#define TC27XD_MEMMAP_PCACHE2 0x50108000
+#define TC27XD_MEMMAP_PTAG2 0x501C0000
+#define TC27XD_MEMMAP_DSPR1 0x60000000
+#define TC27XD_MEMMAP_DCACHE1 0x6001E000
+#define TC27XD_MEMMAP_DTAG1 0x600C0000
+#define TC27XD_MEMMAP_PSPR1 0x60100000
+#define TC27XD_MEMMAP_PCACHE1 0x60108000
+#define TC27XD_MEMMAP_PTAG1 0x601C0000
+#define TC27XD_MEMMAP_DSPR0 0x70000000
+#define TC27XD_MEMMAP_PSPR0 0x70100000
+#define TC27XD_MEMMAP_PCACHE0 0x70106000
+#define TC27XD_MEMMAP_PTAG0 0x701C0000
+#define TC27XD_MEMMAP_PFLASH0_C 0x80000000
+#define TC27XD_MEMMAP_PFLASH1_C 0x80200000
+#define TC27XD_MEMMAP_OLDA_C 0x8FE70000
+#define TC27XD_MEMMAP_BROM_C 0x8FFF8000
+#define TC27XD_MEMMAP_LMURAM_C 0x90000000
+#define TC27XD_MEMMAP_EMEM_C 0x9F000000
+#define TC27XD_MEMMAP_PFLASH0_U 0xA0000000
+#define TC27XD_MEMMAP_PFLASH1_U 0xA0200000
+#define TC27XD_MEMMAP_DFLASH0 0xAF000000
+#define TC27XD_MEMMAP_DFLASH1 0xAF110000
+#define TC27XD_MEMMAP_OLDA_U 0xAFE70000
+#define TC27XD_MEMMAP_BROM_U 0xAFFF8000
+#define TC27XD_MEMMAP_LMURAM_U 0xB0000000
+#define TC27XD_MEMMAP_EMEM_U 0xBF000000
+#define TC27XD_MEMMAP_PSPRX 0xC0000000
+#define TC27XD_MEMMAP_DSPRX 0xD0000000
+
+static struct tricore_boot_info tc27xd_db_binfo;
+
+static void tricore_load_kernel(CPUTriCoreState *env)
+{
+ uint64_t entry;
+ long kernel_size;
+
+ kernel_size = load_elf(tc27xd_db_binfo.kernel_filename, NULL,
+ NULL, NULL, &entry, NULL,
+ NULL, NULL, 0,
+ EM_TRICORE, 1, 0);
+ if (kernel_size <= 0) {
+ error_report("no kernel file '%s'",
+ tc27xd_db_binfo.kernel_filename);
+ exit(1);
+ }
+ env->PC = entry;
+
+}
+
+/*
+ * Initialize the auxiliary ROM region @mr and map it into
+ * the memory map at @base.
+ */
+static void make_rom(MemoryRegion *mr, const char *name,
+ hwaddr base, hwaddr size)
+{
+ memory_region_init_rom(mr, NULL, name, size, &error_fatal);
+ memory_region_add_subregion(get_system_memory(), base, mr);
+}
+
+/*
+ * Initialize the auxiliary RAM region @mr and map it into
+ * the memory map at @base.
+ */
+static void make_ram(MemoryRegion *mr, const char *name,
+ hwaddr base, hwaddr size)
+{
+ memory_region_init_ram(mr, NULL, name, size, &error_fatal);
+ memory_region_add_subregion(get_system_memory(), base, mr);
+}
+
+/*
+ * Create an alias of an entire original MemoryRegion @orig
+ * located at @base in the memory map.
+ */
+static void make_alias(MemoryRegion *mr, const char *name,
+ MemoryRegion *orig, hwaddr base)
+{
+ memory_region_init_alias(mr, NULL, name, orig, 0,
+ memory_region_size(orig));
+ memory_region_add_subregion(get_system_memory(), base, mr);
+}
+
+static void tc27xd_memory_maps_init(void)
+{
+ MemoryRegion *dspr0 = g_new(MemoryRegion, 1);
+ MemoryRegion *dspr1 = g_new(MemoryRegion, 1);
+ MemoryRegion *dspr2 = g_new(MemoryRegion, 1);
+ MemoryRegion *dsprX = g_new(MemoryRegion, 1);
+ MemoryRegion *pspr0 = g_new(MemoryRegion, 1);
+ MemoryRegion *pspr1 = g_new(MemoryRegion, 1);
+ MemoryRegion *pspr2 = g_new(MemoryRegion, 1);
+ MemoryRegion *psprX = g_new(MemoryRegion, 1);
+
+ MemoryRegion *pflash0_c = g_new(MemoryRegion, 1);
+ MemoryRegion *pflash1_c = g_new(MemoryRegion, 1);
+ MemoryRegion *pflash0_u = g_new(MemoryRegion, 1);
+ MemoryRegion *pflash1_u = g_new(MemoryRegion, 1);
+ MemoryRegion *dflash0 = g_new(MemoryRegion, 1);
+ MemoryRegion *dflash1 = g_new(MemoryRegion, 1);
+ MemoryRegion *olda_c = g_new(MemoryRegion, 1);
+ MemoryRegion *olda_u = g_new(MemoryRegion, 1);
+ MemoryRegion *brom_c = g_new(MemoryRegion, 1);
+ MemoryRegion *brom_u = g_new(MemoryRegion, 1);
+ MemoryRegion *lmuram_c = g_new(MemoryRegion, 1);
+ MemoryRegion *lmuram_u = g_new(MemoryRegion, 1);
+ MemoryRegion *emem_c = g_new(MemoryRegion, 1);
+ MemoryRegion *emem_u = g_new(MemoryRegion, 1);
+
+ MemoryRegion *pcache0 = g_new(MemoryRegion, 1);
+ MemoryRegion *ptag0 = g_new(MemoryRegion, 1);
+
+ MemoryRegion *dcache1 = g_new(MemoryRegion, 1);
+ MemoryRegion *dtag1 = g_new(MemoryRegion, 1);
+ MemoryRegion *pcache1 = g_new(MemoryRegion, 1);
+ MemoryRegion *ptag1 = g_new(MemoryRegion, 1);
+
+ MemoryRegion *dcache2 = g_new(MemoryRegion, 1);
+ MemoryRegion *dtag2 = g_new(MemoryRegion, 1);
+ MemoryRegion *pcache2 = g_new(MemoryRegion, 1);
+ MemoryRegion *ptag2 = g_new(MemoryRegion, 1);
+
+ make_ram(dspr2, "CPU2.DSPR", TC27XD_MEMMAP_DSPR2, 120 * KiB);
+ make_ram(pspr2, "CPU2.PSPR", TC27XD_MEMMAP_PSPR2, 32 * KiB);
+ make_ram(dspr1, "CPU1.DSPR", TC27XD_MEMMAP_DSPR1, 120 * KiB);
+ make_ram(pspr1, "CPU1.PSPR", TC27XD_MEMMAP_PSPR1, 32 * KiB);
+ make_ram(dspr0, "CPU0.DSPR", TC27XD_MEMMAP_DSPR0, 112 * KiB);
+ make_ram(pspr0, "CPU0.PSPR", TC27XD_MEMMAP_PSPR0, 24 * KiB);
+
+ /*
+ * TriCore QEMU executes CPU0 only, thus it is sufficient to map
+ * LOCAL.PSPR/LOCAL.DSPR exclusively onto PSPR0/DSPR0.
+ */
+ make_alias(psprX, "LOCAL.PSPR", pspr0,
+ TC27XD_MEMMAP_PSPRX);
+ make_alias(dsprX, "LOCAL.DSPR", dspr0,
+ TC27XD_MEMMAP_DSPRX);
+
+ make_ram(pflash0_c, "PF0", TC27XD_MEMMAP_PFLASH0_C, 2 * MiB);
+ make_ram(pflash1_c, "PF1", TC27XD_MEMMAP_PFLASH1_C, 2 * MiB);
+ make_ram(dflash0, "DF0", TC27XD_MEMMAP_DFLASH0, 1 * MiB + 16 * KiB);
+ make_ram(dflash1, "DF1", TC27XD_MEMMAP_DFLASH1, 64 * KiB);
+ make_ram(olda_c, "OLDA", TC27XD_MEMMAP_OLDA_C, 32 * KiB);
+ make_rom(brom_c, "BROM", TC27XD_MEMMAP_BROM_C, 32 * KiB);
+ make_ram(lmuram_c, "LMURAM", TC27XD_MEMMAP_LMURAM_C, 32 * KiB);
+ make_ram(emem_c, "EMEM", TC27XD_MEMMAP_EMEM_C, 1 * MiB);
+
+ make_alias(pflash0_u, "PF0.U", pflash0_c, TC27XD_MEMMAP_PFLASH0_U);
+ make_alias(pflash1_u, "PF1.U", pflash1_c, TC27XD_MEMMAP_PFLASH1_U);
+ make_alias(olda_u, "OLDA.U", olda_c, TC27XD_MEMMAP_OLDA_U);
+ make_alias(brom_u, "BROM.U", brom_c, TC27XD_MEMMAP_BROM_U);
+ make_alias(lmuram_u, "LMURAM.U", lmuram_c, TC27XD_MEMMAP_LMURAM_U);
+ make_alias(emem_u, "EMEM.U", emem_c, TC27XD_MEMMAP_EMEM_U);
+
+ /* TODO: Control Cache mapping with Memory Test Unit (MTU) */
+ make_ram(dcache2, "CPU2.DCACHE", TC27XD_MEMMAP_DCACHE2, 8 * KiB);
+ make_ram(dtag2, "CPU2.DTAG", TC27XD_MEMMAP_DTAG2, 2560);
+ make_ram(pcache2, "CPU2.PCACHE", TC27XD_MEMMAP_PCACHE2, 16 * KiB);
+ make_ram(ptag2, "CPU2.PTAG", TC27XD_MEMMAP_PTAG2, 6144);
+
+ make_ram(dcache1, "CPU1.DCACHE", TC27XD_MEMMAP_DCACHE1, 8 * KiB);
+ make_ram(dtag1, "CPU1.DTAG", TC27XD_MEMMAP_DTAG1, 2560);
+ make_ram(pcache1, "CPU1.PCACHE", TC27XD_MEMMAP_PCACHE1, 16 * KiB);
+ make_ram(ptag1, "CPU1.PTAG", TC27XD_MEMMAP_PTAG1, 6144);
+
+ make_ram(pcache0, "CPU0.PCACHE", TC27XD_MEMMAP_PCACHE0, 8 * KiB);
+ make_ram(ptag0, "CPU0.PTAG", TC27XD_MEMMAP_PTAG0, 2560);
+}
+
+static void tc27xd_tb_init(MachineState *machine)
+{
+ TriCoreCPU *cpu;
+ CPUTriCoreState *env;
+
+ cpu = TRICORE_CPU(cpu_create(machine->cpu_type));
+ env = &cpu->env;
+
+ tc27xd_memory_maps_init();
+
+ tc27xd_db_binfo.ram_size = machine->ram_size;
+ tc27xd_db_binfo.kernel_filename = machine->kernel_filename;
+
+ if (machine->kernel_filename) {
+ tricore_load_kernel(env);
+ }
+}
+
+static void tc27xd_tb_machine_init(MachineClass *mc)
+{
+ mc->desc = "Infineon AURIX TC277 D-Step TriBoard";
+ mc->init = tc27xd_tb_init;
+ mc->is_default = 0;
+ mc->default_cpu_type = TRICORE_CPU_TYPE_NAME("tc27x");
+}
+DEFINE_MACHINE("AURIX_TriBoard_TC277D", tc27xd_tb_machine_init)
--
2.26.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/1] tricore: added AURIX TC277 D-Step TriBoard
2020-05-11 12:21 ` [PATCH 1/1] " David Brenken
@ 2020-05-11 13:48 ` Philippe Mathieu-Daudé
2020-05-12 8:32 ` AW: " Konopik, Andreas (EFS-GH2)
0 siblings, 1 reply; 6+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-05-11 13:48 UTC (permalink / raw)
To: David Brenken, qemu-devel
Cc: kbastian, Lars Biermanski, Georg Hofstetter, David Brenken,
Robert Rasche, Andreas Konopik
Hello David,
On 5/11/20 2:21 PM, David Brenken wrote:
> From: Andreas Konopik <andreas.konopik@efs-auto.de>
>
> Signed-off-by: Andreas Konopik <andreas.konopik@efs-auto.de>
> Signed-off-by: David Brenken <david.brenken@efs-auto.de>
> Signed-off-by: Georg Hofstetter <georg.hofstetter@efs-auto.de>
> Signed-off-by: Robert Rasche <robert.rasche@efs-auto.de>
> Signed-off-by: Lars Biermanski <lars.biermanski@efs-auto.de>
> ---
> hw/tricore/Makefile.objs | 1 +
> hw/tricore/aurix_triboard_tc277d.c | 240 +++++++++++++++++++++++++++++
> 2 files changed, 241 insertions(+)
> create mode 100644 hw/tricore/aurix_triboard_tc277d.c
>
> diff --git a/hw/tricore/Makefile.objs b/hw/tricore/Makefile.objs
> index 5501f6c1a8..e4a2106dd9 100644
> --- a/hw/tricore/Makefile.objs
> +++ b/hw/tricore/Makefile.objs
> @@ -1 +1,2 @@
> obj-$(CONFIG_TRICORE) += tricore_testboard.o
> +obj-$(CONFIG_TRICORE) += aurix_triboard_tc277d.o
> diff --git a/hw/tricore/aurix_triboard_tc277d.c b/hw/tricore/aurix_triboard_tc277d.c
> new file mode 100644
> index 0000000000..86deff9a50
> --- /dev/null
> +++ b/hw/tricore/aurix_triboard_tc277d.c
> @@ -0,0 +1,240 @@
> +/*
> + * Infineon AURIX TC277 D-Step TriBoard System emulation.
> + *
> + * Copyright (c) 2019 Andreas Konopik <andreas.konopik@efs-auto.de>
> + * Copyright (c) 2019 David Brenken <david.brenken@efs-auto.de>
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/units.h"
> +#include "qapi/error.h"
> +#include "hw/qdev-properties.h"
> +#include "cpu.h"
> +#include "net/net.h"
> +#include "hw/boards.h"
> +#include "hw/loader.h"
> +#include "exec/address-spaces.h"
> +#include "elf.h"
> +#include "hw/tricore/tricore.h"
> +#include "qemu/error-report.h"
> +
> +/*
> + * The TriCore processor architecture defines their respective on-chip memory
> + * layout. Therefore, in contrast to other common architectures, the QEMU
> + * TriCore machine and cpu are closely coupled.
> + *
> + * Memory maps are aligned with the TC27x D-Step Microcontroller layout.
> + */
> +
> +#define TC27XD_MEMMAP_DSPR2 0x50000000
> +#define TC27XD_MEMMAP_DCACHE2 0x5001E000
> +#define TC27XD_MEMMAP_DTAG2 0x500C0000
> +#define TC27XD_MEMMAP_PSPR2 0x50100000
> +#define TC27XD_MEMMAP_PCACHE2 0x50108000
> +#define TC27XD_MEMMAP_PTAG2 0x501C0000
> +#define TC27XD_MEMMAP_DSPR1 0x60000000
> +#define TC27XD_MEMMAP_DCACHE1 0x6001E000
> +#define TC27XD_MEMMAP_DTAG1 0x600C0000
> +#define TC27XD_MEMMAP_PSPR1 0x60100000
> +#define TC27XD_MEMMAP_PCACHE1 0x60108000
> +#define TC27XD_MEMMAP_PTAG1 0x601C0000
> +#define TC27XD_MEMMAP_DSPR0 0x70000000
> +#define TC27XD_MEMMAP_PSPR0 0x70100000
> +#define TC27XD_MEMMAP_PCACHE0 0x70106000
> +#define TC27XD_MEMMAP_PTAG0 0x701C0000
> +#define TC27XD_MEMMAP_PFLASH0_C 0x80000000
> +#define TC27XD_MEMMAP_PFLASH1_C 0x80200000
> +#define TC27XD_MEMMAP_OLDA_C 0x8FE70000
> +#define TC27XD_MEMMAP_BROM_C 0x8FFF8000
> +#define TC27XD_MEMMAP_LMURAM_C 0x90000000
> +#define TC27XD_MEMMAP_EMEM_C 0x9F000000
> +#define TC27XD_MEMMAP_PFLASH0_U 0xA0000000
> +#define TC27XD_MEMMAP_PFLASH1_U 0xA0200000
> +#define TC27XD_MEMMAP_DFLASH0 0xAF000000
> +#define TC27XD_MEMMAP_DFLASH1 0xAF110000
> +#define TC27XD_MEMMAP_OLDA_U 0xAFE70000
> +#define TC27XD_MEMMAP_BROM_U 0xAFFF8000
> +#define TC27XD_MEMMAP_LMURAM_U 0xB0000000
> +#define TC27XD_MEMMAP_EMEM_U 0xBF000000
> +#define TC27XD_MEMMAP_PSPRX 0xC0000000
> +#define TC27XD_MEMMAP_DSPRX 0xD0000000
> +
> +static struct tricore_boot_info tc27xd_db_binfo;
> +
> +static void tricore_load_kernel(CPUTriCoreState *env)
> +{
> + uint64_t entry;
> + long kernel_size;
> +
> + kernel_size = load_elf(tc27xd_db_binfo.kernel_filename, NULL,
> + NULL, NULL, &entry, NULL,
> + NULL, NULL, 0,
> + EM_TRICORE, 1, 0);
> + if (kernel_size <= 0) {
> + error_report("no kernel file '%s'",
> + tc27xd_db_binfo.kernel_filename);
What kernel are you using? Do you have one we can use to try this board?
> + exit(1);
> + }
> + env->PC = entry;
> +
> +}
> +
> +/*
> + * Initialize the auxiliary ROM region @mr and map it into
> + * the memory map at @base.
> + */
> +static void make_rom(MemoryRegion *mr, const char *name,
> + hwaddr base, hwaddr size)
> +{
> + memory_region_init_rom(mr, NULL, name, size, &error_fatal);
> + memory_region_add_subregion(get_system_memory(), base, mr);
> +}
> +
> +/*
> + * Initialize the auxiliary RAM region @mr and map it into
> + * the memory map at @base.
> + */
> +static void make_ram(MemoryRegion *mr, const char *name,
> + hwaddr base, hwaddr size)
> +{
> + memory_region_init_ram(mr, NULL, name, size, &error_fatal);
> + memory_region_add_subregion(get_system_memory(), base, mr);
> +}
> +
> +/*
> + * Create an alias of an entire original MemoryRegion @orig
> + * located at @base in the memory map.
> + */
> +static void make_alias(MemoryRegion *mr, const char *name,
> + MemoryRegion *orig, hwaddr base)
> +{
> + memory_region_init_alias(mr, NULL, name, orig, 0,
> + memory_region_size(orig));
> + memory_region_add_subregion(get_system_memory(), base, mr);
> +}
> +
> +static void tc27xd_memory_maps_init(void)
> +{
Nitpicking, I'd rather use a SoC structure, ...
> + MemoryRegion *dspr0 = g_new(MemoryRegion, 1);
> + MemoryRegion *dspr1 = g_new(MemoryRegion, 1);
> + MemoryRegion *dspr2 = g_new(MemoryRegion, 1);
> + MemoryRegion *dsprX = g_new(MemoryRegion, 1);
> + MemoryRegion *pspr0 = g_new(MemoryRegion, 1);
> + MemoryRegion *pspr1 = g_new(MemoryRegion, 1);
> + MemoryRegion *pspr2 = g_new(MemoryRegion, 1);
> + MemoryRegion *psprX = g_new(MemoryRegion, 1);
... holding 3 CPU structure regions + the default alias...
> +
> + MemoryRegion *pflash0_c = g_new(MemoryRegion, 1);
> + MemoryRegion *pflash1_c = g_new(MemoryRegion, 1);
> + MemoryRegion *pflash0_u = g_new(MemoryRegion, 1);
> + MemoryRegion *pflash1_u = g_new(MemoryRegion, 1);
> + MemoryRegion *dflash0 = g_new(MemoryRegion, 1);
> + MemoryRegion *dflash1 = g_new(MemoryRegion, 1);
> + MemoryRegion *olda_c = g_new(MemoryRegion, 1);
> + MemoryRegion *olda_u = g_new(MemoryRegion, 1);
> + MemoryRegion *brom_c = g_new(MemoryRegion, 1);
> + MemoryRegion *brom_u = g_new(MemoryRegion, 1);
... and one structure holding the flash regions.
> + MemoryRegion *lmuram_c = g_new(MemoryRegion, 1);
> + MemoryRegion *lmuram_u = g_new(MemoryRegion, 1);
> + MemoryRegion *emem_c = g_new(MemoryRegion, 1);
> + MemoryRegion *emem_u = g_new(MemoryRegion, 1);
> +
> + MemoryRegion *pcache0 = g_new(MemoryRegion, 1);
> + MemoryRegion *ptag0 = g_new(MemoryRegion, 1);
> +
> + MemoryRegion *dcache1 = g_new(MemoryRegion, 1);
> + MemoryRegion *dtag1 = g_new(MemoryRegion, 1);
> + MemoryRegion *pcache1 = g_new(MemoryRegion, 1);
> + MemoryRegion *ptag1 = g_new(MemoryRegion, 1);
> +
> + MemoryRegion *dcache2 = g_new(MemoryRegion, 1);
> + MemoryRegion *dtag2 = g_new(MemoryRegion, 1);
> + MemoryRegion *pcache2 = g_new(MemoryRegion, 1);
> + MemoryRegion *ptag2 = g_new(MemoryRegion, 1);
> +
> + make_ram(dspr2, "CPU2.DSPR", TC27XD_MEMMAP_DSPR2, 120 * KiB);
> + make_ram(pspr2, "CPU2.PSPR", TC27XD_MEMMAP_PSPR2, 32 * KiB);
> + make_ram(dspr1, "CPU1.DSPR", TC27XD_MEMMAP_DSPR1, 120 * KiB);
> + make_ram(pspr1, "CPU1.PSPR", TC27XD_MEMMAP_PSPR1, 32 * KiB);
> + make_ram(dspr0, "CPU0.DSPR", TC27XD_MEMMAP_DSPR0, 112 * KiB);
> + make_ram(pspr0, "CPU0.PSPR", TC27XD_MEMMAP_PSPR0, 24 * KiB);
> +
> + /*
> + * TriCore QEMU executes CPU0 only, thus it is sufficient to map
> + * LOCAL.PSPR/LOCAL.DSPR exclusively onto PSPR0/DSPR0.
> + */
> + make_alias(psprX, "LOCAL.PSPR", pspr0,
> + TC27XD_MEMMAP_PSPRX);
> + make_alias(dsprX, "LOCAL.DSPR", dspr0,
> + TC27XD_MEMMAP_DSPRX);
> +
> + make_ram(pflash0_c, "PF0", TC27XD_MEMMAP_PFLASH0_C, 2 * MiB);
> + make_ram(pflash1_c, "PF1", TC27XD_MEMMAP_PFLASH1_C, 2 * MiB);
> + make_ram(dflash0, "DF0", TC27XD_MEMMAP_DFLASH0, 1 * MiB + 16 * KiB);
> + make_ram(dflash1, "DF1", TC27XD_MEMMAP_DFLASH1, 64 * KiB);
> + make_ram(olda_c, "OLDA", TC27XD_MEMMAP_OLDA_C, 32 * KiB);
> + make_rom(brom_c, "BROM", TC27XD_MEMMAP_BROM_C, 32 * KiB);
> + make_ram(lmuram_c, "LMURAM", TC27XD_MEMMAP_LMURAM_C, 32 * KiB);
> + make_ram(emem_c, "EMEM", TC27XD_MEMMAP_EMEM_C, 1 * MiB);
> +
> + make_alias(pflash0_u, "PF0.U", pflash0_c, TC27XD_MEMMAP_PFLASH0_U);
> + make_alias(pflash1_u, "PF1.U", pflash1_c, TC27XD_MEMMAP_PFLASH1_U);
> + make_alias(olda_u, "OLDA.U", olda_c, TC27XD_MEMMAP_OLDA_U);
> + make_alias(brom_u, "BROM.U", brom_c, TC27XD_MEMMAP_BROM_U);
> + make_alias(lmuram_u, "LMURAM.U", lmuram_c, TC27XD_MEMMAP_LMURAM_U);
> + make_alias(emem_u, "EMEM.U", emem_c, TC27XD_MEMMAP_EMEM_U);
> +
> + /* TODO: Control Cache mapping with Memory Test Unit (MTU) */
> + make_ram(dcache2, "CPU2.DCACHE", TC27XD_MEMMAP_DCACHE2, 8 * KiB);
> + make_ram(dtag2, "CPU2.DTAG", TC27XD_MEMMAP_DTAG2, 2560);
> + make_ram(pcache2, "CPU2.PCACHE", TC27XD_MEMMAP_PCACHE2, 16 * KiB);
> + make_ram(ptag2, "CPU2.PTAG", TC27XD_MEMMAP_PTAG2, 6144);
> +
> + make_ram(dcache1, "CPU1.DCACHE", TC27XD_MEMMAP_DCACHE1, 8 * KiB);
> + make_ram(dtag1, "CPU1.DTAG", TC27XD_MEMMAP_DTAG1, 2560);
> + make_ram(pcache1, "CPU1.PCACHE", TC27XD_MEMMAP_PCACHE1, 16 * KiB);
> + make_ram(ptag1, "CPU1.PTAG", TC27XD_MEMMAP_PTAG1, 6144);
> +
> + make_ram(pcache0, "CPU0.PCACHE", TC27XD_MEMMAP_PCACHE0, 8 * KiB);
> + make_ram(ptag0, "CPU0.PTAG", TC27XD_MEMMAP_PTAG0, 2560);
> +}
> +
> +static void tc27xd_tb_init(MachineState *machine)
> +{
> + TriCoreCPU *cpu;
> + CPUTriCoreState *env;
> +
> + cpu = TRICORE_CPU(cpu_create(machine->cpu_type));
> + env = &cpu->env;
> +
> + tc27xd_memory_maps_init();
> +
> + tc27xd_db_binfo.ram_size = machine->ram_size;
> + tc27xd_db_binfo.kernel_filename = machine->kernel_filename;
> +
> + if (machine->kernel_filename) {
> + tricore_load_kernel(env);
} else {
// error message
exit(1);
> + }
> +}
> +
> +static void tc27xd_tb_machine_init(MachineClass *mc)
> +{
> + mc->desc = "Infineon AURIX TC277 D-Step TriBoard";
> + mc->init = tc27xd_tb_init;
> + mc->is_default = 0;
> + mc->default_cpu_type = TRICORE_CPU_TYPE_NAME("tc27x");
> +}
> +DEFINE_MACHINE("AURIX_TriBoard_TC277D", tc27xd_tb_machine_init)
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* AW: [PATCH 1/1] tricore: added AURIX TC277 D-Step TriBoard
2020-05-11 13:48 ` Philippe Mathieu-Daudé
@ 2020-05-12 8:32 ` Konopik, Andreas (EFS-GH2)
2020-05-12 8:40 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 6+ messages in thread
From: Konopik, Andreas (EFS-GH2) @ 2020-05-12 8:32 UTC (permalink / raw)
To: qemu-devel
Cc: kbastian, Philippe Mathieu-Daudé,
Hofstetter, Georg (EFS-GH2), Brenken, David (EFS-GH5),
Rasche, Robert (EFS-GH2), Biermanski, Lars (EFS-GH3)
Hello Philippe,
thank you for your feedback, implementing the TriBoard within an SoC structure seems to be best practice.
We will rewrite the patch accordingly.
I also attached an elf with an empty main-function to test the Machine.
Best regards,
Andreas
> -----Ursprüngliche Nachricht-----
> Von: Philippe Mathieu-Daudé <philmd@redhat.com>
> Gesendet: Montag, 11. Mai 2020 15:48
> An: David Brenken <david.brenken@efs-auto.org>; qemu-devel@nongnu.org
> Cc: kbastian@mail.uni-paderborn.de; Biermanski, Lars (EFS-GH3)
> <lars.biermanski@efs-auto.de>; Hofstetter, Georg (EFS-GH2)
> <Georg.Hofstetter@efs-auto.de>; Brenken, David (EFS-GH5)
> <david.brenken@efs-auto.de>; Rasche, Robert (EFS-GH2) <robert.rasche@efs-
> auto.de>; Konopik, Andreas (EFS-GH2) <andreas.konopik@efs-auto.de>
> Betreff: Re: [PATCH 1/1] tricore: added AURIX TC277 D-Step TriBoard
>
> Hello David,
>
> On 5/11/20 2:21 PM, David Brenken wrote:
> > From: Andreas Konopik <andreas.konopik@efs-auto.de>
> >
> > Signed-off-by: Andreas Konopik <andreas.konopik@efs-auto.de>
> > Signed-off-by: David Brenken <david.brenken@efs-auto.de>
> > Signed-off-by: Georg Hofstetter <georg.hofstetter@efs-auto.de>
> > Signed-off-by: Robert Rasche <robert.rasche@efs-auto.de>
> > Signed-off-by: Lars Biermanski <lars.biermanski@efs-auto.de>
> > ---
> > hw/tricore/Makefile.objs | 1 +
> > hw/tricore/aurix_triboard_tc277d.c | 240
> +++++++++++++++++++++++++++++
> > 2 files changed, 241 insertions(+)
> > create mode 100644 hw/tricore/aurix_triboard_tc277d.c
> >
> > diff --git a/hw/tricore/Makefile.objs b/hw/tricore/Makefile.objs index
> > 5501f6c1a8..e4a2106dd9 100644
> > --- a/hw/tricore/Makefile.objs
> > +++ b/hw/tricore/Makefile.objs
> > @@ -1 +1,2 @@
> > obj-$(CONFIG_TRICORE) += tricore_testboard.o
> > +obj-$(CONFIG_TRICORE) += aurix_triboard_tc277d.o
> > diff --git a/hw/tricore/aurix_triboard_tc277d.c
> > b/hw/tricore/aurix_triboard_tc277d.c
> > new file mode 100644
> > index 0000000000..86deff9a50
> > --- /dev/null
> > +++ b/hw/tricore/aurix_triboard_tc277d.c
> > @@ -0,0 +1,240 @@
> > +/*
> > + * Infineon AURIX TC277 D-Step TriBoard System emulation.
> > + *
> > + * Copyright (c) 2019 Andreas Konopik <andreas.konopik@efs-auto.de>
> > + * Copyright (c) 2019 David Brenken <david.brenken@efs-auto.de>
> > + *
> > + * This library is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU Lesser General Public
> > + * License as published by the Free Software Foundation; either
> > + * version 2 of the License, or (at your option) any later version.
> > + *
> > + * This library is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > + * Lesser General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU Lesser General Public
> > + * License along with this library; if not, see <http://www.gnu.org/licenses/>.
> > + */
> > +
> > +#include "qemu/osdep.h"
> > +#include "qemu/units.h"
> > +#include "qapi/error.h"
> > +#include "hw/qdev-properties.h"
> > +#include "cpu.h"
> > +#include "net/net.h"
> > +#include "hw/boards.h"
> > +#include "hw/loader.h"
> > +#include "exec/address-spaces.h"
> > +#include "elf.h"
> > +#include "hw/tricore/tricore.h"
> > +#include "qemu/error-report.h"
> > +
> > +/*
> > + * The TriCore processor architecture defines their respective
> > +on-chip memory
> > + * layout. Therefore, in contrast to other common architectures, the
> > +QEMU
> > + * TriCore machine and cpu are closely coupled.
> > + *
> > + * Memory maps are aligned with the TC27x D-Step Microcontroller layout.
> > + */
> > +
> > +#define TC27XD_MEMMAP_DSPR2 0x50000000
> > +#define TC27XD_MEMMAP_DCACHE2 0x5001E000
> > +#define TC27XD_MEMMAP_DTAG2 0x500C0000
> > +#define TC27XD_MEMMAP_PSPR2 0x50100000
> > +#define TC27XD_MEMMAP_PCACHE2 0x50108000
> > +#define TC27XD_MEMMAP_PTAG2 0x501C0000
> > +#define TC27XD_MEMMAP_DSPR1 0x60000000
> > +#define TC27XD_MEMMAP_DCACHE1 0x6001E000
> > +#define TC27XD_MEMMAP_DTAG1 0x600C0000
> > +#define TC27XD_MEMMAP_PSPR1 0x60100000
> > +#define TC27XD_MEMMAP_PCACHE1 0x60108000
> > +#define TC27XD_MEMMAP_PTAG1 0x601C0000
> > +#define TC27XD_MEMMAP_DSPR0 0x70000000
> > +#define TC27XD_MEMMAP_PSPR0 0x70100000
> > +#define TC27XD_MEMMAP_PCACHE0 0x70106000
> > +#define TC27XD_MEMMAP_PTAG0 0x701C0000
> > +#define TC27XD_MEMMAP_PFLASH0_C 0x80000000
> > +#define TC27XD_MEMMAP_PFLASH1_C 0x80200000
> > +#define TC27XD_MEMMAP_OLDA_C 0x8FE70000
> > +#define TC27XD_MEMMAP_BROM_C 0x8FFF8000
> > +#define TC27XD_MEMMAP_LMURAM_C 0x90000000
> > +#define TC27XD_MEMMAP_EMEM_C 0x9F000000
> > +#define TC27XD_MEMMAP_PFLASH0_U 0xA0000000
> > +#define TC27XD_MEMMAP_PFLASH1_U 0xA0200000
> > +#define TC27XD_MEMMAP_DFLASH0 0xAF000000
> > +#define TC27XD_MEMMAP_DFLASH1 0xAF110000
> > +#define TC27XD_MEMMAP_OLDA_U 0xAFE70000
> > +#define TC27XD_MEMMAP_BROM_U 0xAFFF8000
> > +#define TC27XD_MEMMAP_LMURAM_U 0xB0000000
> > +#define TC27XD_MEMMAP_EMEM_U 0xBF000000
> > +#define TC27XD_MEMMAP_PSPRX 0xC0000000
> > +#define TC27XD_MEMMAP_DSPRX 0xD0000000
> > +
> > +static struct tricore_boot_info tc27xd_db_binfo;
> > +
> > +static void tricore_load_kernel(CPUTriCoreState *env) {
> > + uint64_t entry;
> > + long kernel_size;
> > +
> > + kernel_size = load_elf(tc27xd_db_binfo.kernel_filename, NULL,
> > + NULL, NULL, &entry, NULL,
> > + NULL, NULL, 0,
> > + EM_TRICORE, 1, 0);
> > + if (kernel_size <= 0) {
> > + error_report("no kernel file '%s'",
> > + tc27xd_db_binfo.kernel_filename);
>
> What kernel are you using? Do you have one we can use to try this board?
>
> > + exit(1);
> > + }
> > + env->PC = entry;
> > +
> > +}
> > +
> > +/*
> > + * Initialize the auxiliary ROM region @mr and map it into
> > + * the memory map at @base.
> > + */
> > +static void make_rom(MemoryRegion *mr, const char *name,
> > + hwaddr base, hwaddr size) {
> > + memory_region_init_rom(mr, NULL, name, size, &error_fatal);
> > + memory_region_add_subregion(get_system_memory(), base, mr); }
> > +
> > +/*
> > + * Initialize the auxiliary RAM region @mr and map it into
> > + * the memory map at @base.
> > + */
> > +static void make_ram(MemoryRegion *mr, const char *name,
> > + hwaddr base, hwaddr size)
> > +{
> > + memory_region_init_ram(mr, NULL, name, size, &error_fatal);
> > + memory_region_add_subregion(get_system_memory(), base, mr);
> > +}
> > +
> > +/*
> > + * Create an alias of an entire original MemoryRegion @orig
> > + * located at @base in the memory map.
> > + */
> > +static void make_alias(MemoryRegion *mr, const char *name,
> > + MemoryRegion *orig, hwaddr base)
> > +{
> > + memory_region_init_alias(mr, NULL, name, orig, 0,
> > + memory_region_size(orig));
> > + memory_region_add_subregion(get_system_memory(), base, mr);
> > +}
> > +
> > +static void tc27xd_memory_maps_init(void)
> > +{
>
> Nitpicking, I'd rather use a SoC structure, ...
>
> > + MemoryRegion *dspr0 = g_new(MemoryRegion, 1);
> > + MemoryRegion *dspr1 = g_new(MemoryRegion, 1);
> > + MemoryRegion *dspr2 = g_new(MemoryRegion, 1);
> > + MemoryRegion *dsprX = g_new(MemoryRegion, 1);
> > + MemoryRegion *pspr0 = g_new(MemoryRegion, 1);
> > + MemoryRegion *pspr1 = g_new(MemoryRegion, 1);
> > + MemoryRegion *pspr2 = g_new(MemoryRegion, 1);
> > + MemoryRegion *psprX = g_new(MemoryRegion, 1);
>
> ... holding 3 CPU structure regions + the default alias...
>
> > +
> > + MemoryRegion *pflash0_c = g_new(MemoryRegion, 1);
> > + MemoryRegion *pflash1_c = g_new(MemoryRegion, 1);
> > + MemoryRegion *pflash0_u = g_new(MemoryRegion, 1);
> > + MemoryRegion *pflash1_u = g_new(MemoryRegion, 1);
> > + MemoryRegion *dflash0 = g_new(MemoryRegion, 1);
> > + MemoryRegion *dflash1 = g_new(MemoryRegion, 1);
> > + MemoryRegion *olda_c = g_new(MemoryRegion, 1);
> > + MemoryRegion *olda_u = g_new(MemoryRegion, 1);
> > + MemoryRegion *brom_c = g_new(MemoryRegion, 1);
> > + MemoryRegion *brom_u = g_new(MemoryRegion, 1);
>
> ... and one structure holding the flash regions.
>
> > + MemoryRegion *lmuram_c = g_new(MemoryRegion, 1);
> > + MemoryRegion *lmuram_u = g_new(MemoryRegion, 1);
> > + MemoryRegion *emem_c = g_new(MemoryRegion, 1);
> > + MemoryRegion *emem_u = g_new(MemoryRegion, 1);
> > +
> > + MemoryRegion *pcache0 = g_new(MemoryRegion, 1);
> > + MemoryRegion *ptag0 = g_new(MemoryRegion, 1);
> > +
> > + MemoryRegion *dcache1 = g_new(MemoryRegion, 1);
> > + MemoryRegion *dtag1 = g_new(MemoryRegion, 1);
> > + MemoryRegion *pcache1 = g_new(MemoryRegion, 1);
> > + MemoryRegion *ptag1 = g_new(MemoryRegion, 1);
> > +
> > + MemoryRegion *dcache2 = g_new(MemoryRegion, 1);
> > + MemoryRegion *dtag2 = g_new(MemoryRegion, 1);
> > + MemoryRegion *pcache2 = g_new(MemoryRegion, 1);
> > + MemoryRegion *ptag2 = g_new(MemoryRegion, 1);
> > +
> > + make_ram(dspr2, "CPU2.DSPR", TC27XD_MEMMAP_DSPR2, 120 * KiB);
> > + make_ram(pspr2, "CPU2.PSPR", TC27XD_MEMMAP_PSPR2, 32 * KiB);
> > + make_ram(dspr1, "CPU1.DSPR", TC27XD_MEMMAP_DSPR1, 120 * KiB);
> > + make_ram(pspr1, "CPU1.PSPR", TC27XD_MEMMAP_PSPR1, 32 * KiB);
> > + make_ram(dspr0, "CPU0.DSPR", TC27XD_MEMMAP_DSPR0, 112 * KiB);
> > + make_ram(pspr0, "CPU0.PSPR", TC27XD_MEMMAP_PSPR0, 24 * KiB);
> > +
> > + /*
> > + * TriCore QEMU executes CPU0 only, thus it is sufficient to map
> > + * LOCAL.PSPR/LOCAL.DSPR exclusively onto PSPR0/DSPR0.
> > + */
> > + make_alias(psprX, "LOCAL.PSPR", pspr0,
> > + TC27XD_MEMMAP_PSPRX);
> > + make_alias(dsprX, "LOCAL.DSPR", dspr0,
> > + TC27XD_MEMMAP_DSPRX);
> > +
> > + make_ram(pflash0_c, "PF0", TC27XD_MEMMAP_PFLASH0_C, 2 * MiB);
> > + make_ram(pflash1_c, "PF1", TC27XD_MEMMAP_PFLASH1_C, 2 * MiB);
> > + make_ram(dflash0, "DF0", TC27XD_MEMMAP_DFLASH0, 1 * MiB + 16 *
> KiB);
> > + make_ram(dflash1, "DF1", TC27XD_MEMMAP_DFLASH1, 64 * KiB);
> > + make_ram(olda_c, "OLDA", TC27XD_MEMMAP_OLDA_C, 32 * KiB);
> > + make_rom(brom_c, "BROM", TC27XD_MEMMAP_BROM_C, 32 * KiB);
> > + make_ram(lmuram_c, "LMURAM", TC27XD_MEMMAP_LMURAM_C, 32 *
> KiB);
> > + make_ram(emem_c, "EMEM", TC27XD_MEMMAP_EMEM_C, 1 *
> MiB);
> > +
> > + make_alias(pflash0_u, "PF0.U", pflash0_c,
> TC27XD_MEMMAP_PFLASH0_U);
> > + make_alias(pflash1_u, "PF1.U", pflash1_c,
> TC27XD_MEMMAP_PFLASH1_U);
> > + make_alias(olda_u, "OLDA.U", olda_c, TC27XD_MEMMAP_OLDA_U);
> > + make_alias(brom_u, "BROM.U", brom_c,
> TC27XD_MEMMAP_BROM_U);
> > + make_alias(lmuram_u, "LMURAM.U", lmuram_c,
> TC27XD_MEMMAP_LMURAM_U);
> > + make_alias(emem_u, "EMEM.U", emem_c,
> TC27XD_MEMMAP_EMEM_U);
> > +
> > + /* TODO: Control Cache mapping with Memory Test Unit (MTU) */
> > + make_ram(dcache2, "CPU2.DCACHE", TC27XD_MEMMAP_DCACHE2, 8 *
> KiB);
> > + make_ram(dtag2, "CPU2.DTAG", TC27XD_MEMMAP_DTAG2, 2560);
> > + make_ram(pcache2, "CPU2.PCACHE", TC27XD_MEMMAP_PCACHE2, 16 *
> KiB);
> > + make_ram(ptag2, "CPU2.PTAG", TC27XD_MEMMAP_PTAG2, 6144);
> > +
> > + make_ram(dcache1, "CPU1.DCACHE", TC27XD_MEMMAP_DCACHE1, 8 *
> KiB);
> > + make_ram(dtag1, "CPU1.DTAG", TC27XD_MEMMAP_DTAG1, 2560);
> > + make_ram(pcache1, "CPU1.PCACHE", TC27XD_MEMMAP_PCACHE1, 16 *
> KiB);
> > + make_ram(ptag1, "CPU1.PTAG", TC27XD_MEMMAP_PTAG1, 6144);
> > +
> > + make_ram(pcache0, "CPU0.PCACHE", TC27XD_MEMMAP_PCACHE0, 8 *
> KiB);
> > + make_ram(ptag0, "CPU0.PTAG", TC27XD_MEMMAP_PTAG0, 2560);
> > +}
> > +
> > +static void tc27xd_tb_init(MachineState *machine)
> > +{
> > + TriCoreCPU *cpu;
> > + CPUTriCoreState *env;
> > +
> > + cpu = TRICORE_CPU(cpu_create(machine->cpu_type));
> > + env = &cpu->env;
> > +
> > + tc27xd_memory_maps_init();
> > +
> > + tc27xd_db_binfo.ram_size = machine->ram_size;
> > + tc27xd_db_binfo.kernel_filename = machine->kernel_filename;
> > +
> > + if (machine->kernel_filename) {
> > + tricore_load_kernel(env);
>
> } else {
> // error message
> exit(1);
>
> > + }
> > +}
> > +
> > +static void tc27xd_tb_machine_init(MachineClass *mc)
> > +{
> > + mc->desc = "Infineon AURIX TC277 D-Step TriBoard";
> > + mc->init = tc27xd_tb_init;
> > + mc->is_default = 0;
> > + mc->default_cpu_type = TRICORE_CPU_TYPE_NAME("tc27x");
> > +}
> > +DEFINE_MACHINE("AURIX_TriBoard_TC277D", tc27xd_tb_machine_init)
> >
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: AW: [PATCH 1/1] tricore: added AURIX TC277 D-Step TriBoard
2020-05-12 8:32 ` AW: " Konopik, Andreas (EFS-GH2)
@ 2020-05-12 8:40 ` Philippe Mathieu-Daudé
2020-05-22 10:40 ` AW: " Konopik, Andreas (EFS-GH2)
0 siblings, 1 reply; 6+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-05-12 8:40 UTC (permalink / raw)
To: Konopik, Andreas (EFS-GH2), qemu-devel
Cc: kbastian, Brenken, David (EFS-GH5), Rasche, Robert (EFS-GH2),
Hofstetter, Georg (EFS-GH2), Biermanski, Lars (EFS-GH3)
On 5/12/20 10:32 AM, Konopik, Andreas (EFS-GH2) wrote:
> Hello Philippe,
>
> thank you for your feedback, implementing the TriBoard within an SoC structure seems to be best practice.
> We will rewrite the patch accordingly.
>
> I also attached an elf with an empty main-function to test the Machine.
Thanks, I am getting:
$ qemu-system-tricore -M AURIX_TriBoard_TC277D \
-kernel hello_world.elf -d unimp,in_asm
qemu-system-tricore: function cpu_get_phys_page_attrs_debug not
implemented, aborting
>
> Best regards,
>
> Andreas
>
>> -----Ursprüngliche Nachricht-----
>> Von: Philippe Mathieu-Daudé <philmd@redhat.com>
>> Gesendet: Montag, 11. Mai 2020 15:48
>> An: David Brenken <david.brenken@efs-auto.org>; qemu-devel@nongnu.org
>> Cc: kbastian@mail.uni-paderborn.de; Biermanski, Lars (EFS-GH3)
>> <lars.biermanski@efs-auto.de>; Hofstetter, Georg (EFS-GH2)
>> <Georg.Hofstetter@efs-auto.de>; Brenken, David (EFS-GH5)
>> <david.brenken@efs-auto.de>; Rasche, Robert (EFS-GH2) <robert.rasche@efs-
>> auto.de>; Konopik, Andreas (EFS-GH2) <andreas.konopik@efs-auto.de>
>> Betreff: Re: [PATCH 1/1] tricore: added AURIX TC277 D-Step TriBoard
>>
>> Hello David,
>>
>> On 5/11/20 2:21 PM, David Brenken wrote:
>>> From: Andreas Konopik <andreas.konopik@efs-auto.de>
>>>
>>> Signed-off-by: Andreas Konopik <andreas.konopik@efs-auto.de>
>>> Signed-off-by: David Brenken <david.brenken@efs-auto.de>
>>> Signed-off-by: Georg Hofstetter <georg.hofstetter@efs-auto.de>
>>> Signed-off-by: Robert Rasche <robert.rasche@efs-auto.de>
>>> Signed-off-by: Lars Biermanski <lars.biermanski@efs-auto.de>
>>> ---
>>> hw/tricore/Makefile.objs | 1 +
>>> hw/tricore/aurix_triboard_tc277d.c | 240
>> +++++++++++++++++++++++++++++
>>> 2 files changed, 241 insertions(+)
>>> create mode 100644 hw/tricore/aurix_triboard_tc277d.c
>>>
>>> diff --git a/hw/tricore/Makefile.objs b/hw/tricore/Makefile.objs index
>>> 5501f6c1a8..e4a2106dd9 100644
>>> --- a/hw/tricore/Makefile.objs
>>> +++ b/hw/tricore/Makefile.objs
>>> @@ -1 +1,2 @@
>>> obj-$(CONFIG_TRICORE) += tricore_testboard.o
>>> +obj-$(CONFIG_TRICORE) += aurix_triboard_tc277d.o
>>> diff --git a/hw/tricore/aurix_triboard_tc277d.c
[...]
^ permalink raw reply [flat|nested] 6+ messages in thread
* AW: AW: [PATCH 1/1] tricore: added AURIX TC277 D-Step TriBoard
2020-05-12 8:40 ` Philippe Mathieu-Daudé
@ 2020-05-22 10:40 ` Konopik, Andreas (EFS-GH2)
0 siblings, 0 replies; 6+ messages in thread
From: Konopik, Andreas (EFS-GH2) @ 2020-05-22 10:40 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: kbastian, Biermanski, Lars (EFS-GH3),
Hofstetter, Georg (EFS-GH2), Brenken, David (EFS-GH5),
Rasche, Robert (EFS-GH2),
David Brenken
Hello Philippe,
sorry to keep you waiting.
> -----Ursprüngliche Nachricht-----
> Von: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Im Auftrag
> von Philippe Mathieu-Daudé
> Gesendet: Dienstag, 12. Mai 2020 10:40
> An: Konopik, Andreas (EFS-GH2) <andreas.konopik@efs-auto.de>; qemu-
> devel@nongnu.org
> Cc: kbastian@mail.uni-paderborn.de; Brenken, David (EFS-GH5)
> <david.brenken@efs-auto.de>; Hofstetter, Georg (EFS-GH2)
> <Georg.Hofstetter@efs-auto.de>; Rasche, Robert (EFS-GH2)
> <robert.rasche@efs-auto.de>; Biermanski, Lars (EFS-GH3)
> <lars.biermanski@efs-auto.de>
> Betreff: Re: AW: [PATCH 1/1] tricore: added AURIX TC277 D-Step TriBoard
>
> On 5/12/20 10:32 AM, Konopik, Andreas (EFS-GH2) wrote:
> > Hello Philippe,
> >
> > thank you for your feedback, implementing the TriBoard within an SoC
> structure seems to be best practice.
> > We will rewrite the patch accordingly.
> >
> > I also attached an elf with an empty main-function to test the Machine.
>
> Thanks, I am getting:
>
> $ qemu-system-tricore -M AURIX_TriBoard_TC277D \
> -kernel hello_world.elf -d unimp,in_asm
> qemu-system-tricore: function cpu_get_phys_page_attrs_debug not
> implemented, aborting
>
The current state of tricore target is in some areas more of a rudimentary implementation and lacks many features, especially disassembly.
Your error has something to do with the "in_asm" logging.
In our case we test tricore implementations using a dummy device which prints to the commandline.
The bare-metal elf then writes logging strings one char at a time into the dummy devices address.
If you like, I can send you patches for a "real" hello_world example including dummy device.
Best regards,
Andreas
> >
> > Best regards,
> >
> > Andreas
> >
> >> -----Ursprüngliche Nachricht-----
> >> Von: Philippe Mathieu-Daudé <philmd@redhat.com>
> >> Gesendet: Montag, 11. Mai 2020 15:48
> >> An: David Brenken <david.brenken@efs-auto.org>; qemu-devel@nongnu.org
> >> Cc: kbastian@mail.uni-paderborn.de; Biermanski, Lars (EFS-GH3)
> >> <lars.biermanski@efs-auto.de>; Hofstetter, Georg (EFS-GH2)
> >> <Georg.Hofstetter@efs-auto.de>; Brenken, David (EFS-GH5)
> >> <david.brenken@efs-auto.de>; Rasche, Robert (EFS-GH2)
> >> <robert.rasche@efs- auto.de>; Konopik, Andreas (EFS-GH2)
> >> <andreas.konopik@efs-auto.de>
> >> Betreff: Re: [PATCH 1/1] tricore: added AURIX TC277 D-Step TriBoard
> >>
> >> Hello David,
> >>
> >> On 5/11/20 2:21 PM, David Brenken wrote:
> >>> From: Andreas Konopik <andreas.konopik@efs-auto.de>
> >>>
> >>> Signed-off-by: Andreas Konopik <andreas.konopik@efs-auto.de>
> >>> Signed-off-by: David Brenken <david.brenken@efs-auto.de>
> >>> Signed-off-by: Georg Hofstetter <georg.hofstetter@efs-auto.de>
> >>> Signed-off-by: Robert Rasche <robert.rasche@efs-auto.de>
> >>> Signed-off-by: Lars Biermanski <lars.biermanski@efs-auto.de>
> >>> ---
> >>> hw/tricore/Makefile.objs | 1 +
> >>> hw/tricore/aurix_triboard_tc277d.c | 240
> >> +++++++++++++++++++++++++++++
> >>> 2 files changed, 241 insertions(+)
> >>> create mode 100644 hw/tricore/aurix_triboard_tc277d.c
> >>>
> >>> diff --git a/hw/tricore/Makefile.objs b/hw/tricore/Makefile.objs
> >>> index
> >>> 5501f6c1a8..e4a2106dd9 100644
> >>> --- a/hw/tricore/Makefile.objs
> >>> +++ b/hw/tricore/Makefile.objs
> >>> @@ -1 +1,2 @@
> >>> obj-$(CONFIG_TRICORE) += tricore_testboard.o
> >>> +obj-$(CONFIG_TRICORE) += aurix_triboard_tc277d.o
> >>> diff --git a/hw/tricore/aurix_triboard_tc277d.c
> [...]
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-05-22 10:41 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-05-11 12:21 [PATCH 0/1] tricore: added AURIX TC277 D-Step TriBoard David Brenken
2020-05-11 12:21 ` [PATCH 1/1] " David Brenken
2020-05-11 13:48 ` Philippe Mathieu-Daudé
2020-05-12 8:32 ` AW: " Konopik, Andreas (EFS-GH2)
2020-05-12 8:40 ` Philippe Mathieu-Daudé
2020-05-22 10:40 ` AW: " Konopik, Andreas (EFS-GH2)
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