From: frank.chang@sifive.com
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: "Frank Chang" <frank.chang@sifive.com>,
"Chih-Min Chao" <chihmin.chao@sifive.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Aurelien Jarno" <aurelien@aurel32.net>,
"Peter Maydell" <peter.maydell@linaro.org>
Subject: [RFC v2 68/76] fpu: add api to handle alternative sNaN propagation
Date: Wed, 22 Jul 2020 17:16:31 +0800 [thread overview]
Message-ID: <20200722091641.8834-69-frank.chang@sifive.com> (raw)
In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com>
From: Chih-Min Chao <chihmin.chao@sifive.com>
For "fmax/fmin ft0, ft1, ft2" and if one of the inputs is sNaN,
The original logic
return NaN and set invalid flag if ft1 == sNaN || ft2 == sNan
The alternative path
set invalid flag if ft1 == sNaN || ft2 == sNaN
return NaN if ft1 == sNaN && ft2 == sNaN
The ieee754 spec allows both implementation and some architecture such
as riscv choose differenct defintion in two spec versions.
(riscv-spec-v2.2 use original one, riscv-spec-20191213 changes to
alternative one)
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
fpu/softfloat.c | 75 ++++++++++++++++++++++++++---------------
include/fpu/softfloat.h | 6 ++++
2 files changed, 54 insertions(+), 27 deletions(-)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 9c6640862e..e1661f22a5 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -898,11 +898,16 @@ static FloatParts return_nan(FloatParts a, float_status *s)
return a;
}
-static FloatParts pick_nan(FloatParts a, FloatParts b, float_status *s)
+static void set_snan_flag(FloatParts a, FloatParts b, float_status *s)
{
if (is_snan(a.cls) || is_snan(b.cls)) {
s->float_exception_flags |= float_flag_invalid;
}
+}
+
+static FloatParts pick_nan(FloatParts a, FloatParts b, float_status *s)
+{
+ set_snan_flag(a, b, s);
if (s->default_nan_mode) {
return parts_default_nan(s);
@@ -2771,23 +2776,32 @@ float64 uint16_to_float64(uint16_t a, float_status *status)
* and minNumMag() from the IEEE-754 2008.
*/
static FloatParts minmax_floats(FloatParts a, FloatParts b, bool ismin,
- bool ieee, bool ismag, float_status *s)
+ bool ieee, bool ismag, bool issnan_prop,
+ float_status *s)
{
if (unlikely(is_nan(a.cls) || is_nan(b.cls))) {
if (ieee) {
/* Takes two floating-point values `a' and `b', one of
* which is a NaN, and returns the appropriate NaN
* result. If either `a' or `b' is a signaling NaN,
- * the invalid exception is raised.
+ * the invalid exception is raised but the NaN
+ * propagation is 'shall'.
*/
if (is_snan(a.cls) || is_snan(b.cls)) {
- return pick_nan(a, b, s);
- } else if (is_nan(a.cls) && !is_nan(b.cls)) {
+ if (issnan_prop) {
+ return pick_nan(a, b, s);
+ } else {
+ set_snan_flag(a, b, s);
+ }
+ }
+
+ if (is_nan(a.cls) && !is_nan(b.cls)) {
return b;
} else if (is_nan(b.cls) && !is_nan(a.cls)) {
return a;
}
}
+
return pick_nan(a, b, s);
} else {
int a_exp, b_exp;
@@ -2841,37 +2855,44 @@ static FloatParts minmax_floats(FloatParts a, FloatParts b, bool ismin,
}
}
-#define MINMAX(sz, name, ismin, isiee, ismag) \
+#define MINMAX(sz, name, ismin, isiee, ismag, issnan_prop) \
float ## sz float ## sz ## _ ## name(float ## sz a, float ## sz b, \
float_status *s) \
{ \
FloatParts pa = float ## sz ## _unpack_canonical(a, s); \
FloatParts pb = float ## sz ## _unpack_canonical(b, s); \
- FloatParts pr = minmax_floats(pa, pb, ismin, isiee, ismag, s); \
+ FloatParts pr = minmax_floats(pa, pb, ismin, isiee, ismag, \
+ issnan_prop, s); \
\
return float ## sz ## _round_pack_canonical(pr, s); \
}
-MINMAX(16, min, true, false, false)
-MINMAX(16, minnum, true, true, false)
-MINMAX(16, minnummag, true, true, true)
-MINMAX(16, max, false, false, false)
-MINMAX(16, maxnum, false, true, false)
-MINMAX(16, maxnummag, false, true, true)
-
-MINMAX(32, min, true, false, false)
-MINMAX(32, minnum, true, true, false)
-MINMAX(32, minnummag, true, true, true)
-MINMAX(32, max, false, false, false)
-MINMAX(32, maxnum, false, true, false)
-MINMAX(32, maxnummag, false, true, true)
-
-MINMAX(64, min, true, false, false)
-MINMAX(64, minnum, true, true, false)
-MINMAX(64, minnummag, true, true, true)
-MINMAX(64, max, false, false, false)
-MINMAX(64, maxnum, false, true, false)
-MINMAX(64, maxnummag, false, true, true)
+MINMAX(16, min, true, false, false, true)
+MINMAX(16, minnum, true, true, false, true)
+MINMAX(16, minnum_noprop, true, true, false, false)
+MINMAX(16, minnummag, true, true, true, true)
+MINMAX(16, max, false, false, false, true)
+MINMAX(16, maxnum, false, true, false, true)
+MINMAX(16, maxnum_noprop, false, true, false, false)
+MINMAX(16, maxnummag, false, true, true, true)
+
+MINMAX(32, min, true, false, false, true)
+MINMAX(32, minnum, true, true, false, true)
+MINMAX(32, minnum_noprop, true, true, false, false)
+MINMAX(32, minnummag, true, true, true, true)
+MINMAX(32, max, false, false, false, true)
+MINMAX(32, maxnum, false, true, false, true)
+MINMAX(32, maxnum_noprop, false, true, false, false)
+MINMAX(32, maxnummag, false, true, true, true)
+
+MINMAX(64, min, true, false, false, true)
+MINMAX(64, minnum, true, true, false, true)
+MINMAX(64, minnum_noprop, true, true, false, false)
+MINMAX(64, minnummag, true, true, true, true)
+MINMAX(64, max, false, false, false, true)
+MINMAX(64, maxnum, false, true, false, true)
+MINMAX(64, maxnum_noprop, false, true, false, false)
+MINMAX(64, maxnummag, false, true, true, true)
#undef MINMAX
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index 267519cd65..078cad8ad9 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -231,6 +231,8 @@ float16 float16_minnum(float16, float16, float_status *status);
float16 float16_maxnum(float16, float16, float_status *status);
float16 float16_minnummag(float16, float16, float_status *status);
float16 float16_maxnummag(float16, float16, float_status *status);
+float16 float16_minnum_noprop(float16, float16, float_status *status);
+float16 float16_maxnum_noprop(float16, float16, float_status *status);
float16 float16_sqrt(float16, float_status *status);
FloatRelation float16_compare(float16, float16, float_status *status);
FloatRelation float16_compare_quiet(float16, float16, float_status *status);
@@ -392,6 +394,8 @@ float32 float32_minnum(float32, float32, float_status *status);
float32 float32_maxnum(float32, float32, float_status *status);
float32 float32_minnummag(float32, float32, float_status *status);
float32 float32_maxnummag(float32, float32, float_status *status);
+float32 float32_minnum_noprop(float32, float32, float_status *status);
+float32 float32_maxnum_noprop(float32, float32, float_status *status);
bool float32_is_quiet_nan(float32, float_status *status);
bool float32_is_signaling_nan(float32, float_status *status);
float32 float32_silence_nan(float32, float_status *status);
@@ -581,6 +585,8 @@ float64 float64_minnum(float64, float64, float_status *status);
float64 float64_maxnum(float64, float64, float_status *status);
float64 float64_minnummag(float64, float64, float_status *status);
float64 float64_maxnummag(float64, float64, float_status *status);
+float64 float64_minnum_noprop(float64, float64, float_status *status);
+float64 float64_maxnum_noprop(float64, float64, float_status *status);
bool float64_is_quiet_nan(float64 a, float_status *status);
bool float64_is_signaling_nan(float64, float_status *status);
float64 float64_silence_nan(float64, float_status *status);
--
2.17.1
next prev parent reply other threads:[~2020-07-22 9:44 UTC|newest]
Thread overview: 147+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-22 9:15 [RFC v2 00/76] target/riscv: support vector extension v0.9 frank.chang
2020-07-22 9:15 ` [RFC v2 01/76] target/riscv: drop vector 0.7.1 support frank.chang
2020-07-22 16:37 ` Alistair Francis
2020-07-27 19:54 ` Palmer Dabbelt
2020-07-27 19:55 ` Alistair Francis
2020-07-30 8:07 ` Frank Chang
2020-07-30 12:27 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 02/76] target/riscv: rvv-0.9: support vector 0.9 frank.chang
2020-07-22 16:13 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 03/76] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion frank.chang
2020-07-22 16:18 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 04/76] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64() frank.chang
2020-07-22 9:15 ` [RFC v2 05/76] target/riscv: fix return value of do_opivx_widen() frank.chang
2020-07-22 9:15 ` [RFC v2 06/76] target/riscv: fix vill bit index in vtype register frank.chang
2020-07-22 9:15 ` [RFC v2 07/76] target/riscv: Use FIELD_EX32() to extract wd field frank.chang
2020-07-22 16:19 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 08/76] target/riscv: rvv-0.9: add mstatus VS field frank.chang
2020-07-22 16:33 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 09/76] target/riscv: rvv-0.9: add sstatus " frank.chang
2020-07-22 16:34 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 10/76] target/riscv: rvv-0.9: add translation-time vector context status frank.chang
2020-07-22 16:53 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 11/76] target/riscv: rvv-0.9: remove vxrm and vxsat fields from fcsr register frank.chang
2020-07-22 16:54 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 12/76] target/riscv: rvv-0.9: add vcsr register frank.chang
2020-07-22 16:57 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 13/76] target/riscv: rvv-0.9: add vlenb register frank.chang
2020-07-22 16:58 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 14/76] target/riscv: rvv-0.9: remove MLEN calculations frank.chang
2020-07-22 17:04 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 15/76] target/riscv: rvv-0.9: add fractional LMUL frank.chang
2020-07-22 17:30 ` Richard Henderson
2020-07-23 2:11 ` Frank Chang
2020-07-22 9:15 ` [RFC v2 16/76] target/riscv: rvv-0.9: add VMA and VTA frank.chang
2020-07-22 18:00 ` Richard Henderson
2020-07-23 2:18 ` Frank Chang
2020-07-22 9:15 ` [RFC v2 17/76] target/riscv: rvv-0.9: update check functions frank.chang
2020-07-22 9:15 ` [RFC v2 18/76] target/riscv: introduce more imm value modes in translator functions frank.chang
2020-07-22 18:08 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 19/76] target/riscv: rvv-0.9: add narrower_nanbox_fpr helper frank.chang
2020-07-22 19:15 ` Richard Henderson
2020-07-23 7:13 ` Frank Chang
2020-07-23 16:14 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 20/76] target/riscv: rvv-0.9: apply narrower nanbox helper in opfvf_trans frank.chang
2020-07-22 9:15 ` [RFC v2 21/76] target/riscv: rvv-0.9: configure instructions frank.chang
2020-07-22 20:00 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 22/76] target/riscv: rvv-0.9: stride load and store instructions frank.chang
2020-07-22 9:15 ` [RFC v2 23/76] target/riscv: rvv-0.9: index " frank.chang
2020-07-22 9:15 ` [RFC v2 24/76] target/riscv: rvv-0.9: fix address index overflow bug of indexed load/store insns frank.chang
2020-07-22 9:15 ` [RFC v2 25/76] target/riscv: rvv-0.9: fault-only-first unit stride load frank.chang
2020-07-22 9:15 ` [RFC v2 26/76] target/riscv: rvv-0.9: amo operations frank.chang
2020-07-22 9:15 ` [RFC v2 27/76] target/riscv: rvv-0.9: load/store whole register instructions frank.chang
2020-07-29 20:30 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 28/76] target/riscv: rvv-0.9: update vext_max_elems() for load/store insns frank.chang
2020-07-30 12:44 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 29/76] target/riscv: rvv-0.9: take fractional LMUL into vector max elements calculation frank.chang
2020-07-30 12:52 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 30/76] target/riscv: rvv-0.9: floating-point square-root instruction frank.chang
2020-07-30 13:02 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 31/76] target/riscv: rvv-0.9: floating-point classify instructions frank.chang
2020-07-30 13:02 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 32/76] target/riscv: rvv-0.9: mask population count instruction frank.chang
2020-07-30 13:05 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 33/76] target/riscv: rvv-0.9: find-first-set mask bit instruction frank.chang
2020-07-30 13:13 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 34/76] target/riscv: rvv-0.9: set-X-first mask bit instructions frank.chang
2020-07-30 13:26 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 35/76] target/riscv: rvv-0.9: iota instruction frank.chang
2020-07-30 13:29 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 36/76] target/riscv: rvv-0.9: element index instruction frank.chang
2020-07-30 13:30 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 37/76] target/riscv: rvv-0.9: allow load element with sign-extended frank.chang
2020-07-30 13:43 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 38/76] target/riscv: rvv-0.9: register gather instructions frank.chang
2020-07-22 9:16 ` [RFC v2 39/76] target/riscv: rvv-0.9: integer scalar move instructions frank.chang
2020-07-30 14:50 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 40/76] target/riscv: rvv-0.9: floating-point move instruction frank.chang
2020-07-30 19:57 ` Richard Henderson
2020-07-30 20:05 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 41/76] target/riscv: rvv-0.9: floating-point scalar move instructions frank.chang
2020-07-30 20:03 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 42/76] target/riscv: rvv-0.9: whole register " frank.chang
2020-07-30 20:14 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 43/76] target/riscv: rvv-0.9: integer extension instructions frank.chang
2020-07-30 20:35 ` Richard Henderson
2020-07-31 10:17 ` Frank Chang
2020-07-31 17:30 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 44/76] target/riscv: rvv-0.9: single-width averaging add and subtract instructions frank.chang
2020-07-30 20:45 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 45/76] target/riscv: rvv-0.9: single-width bit shift instructions frank.chang
2020-07-30 20:47 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 46/76] target/riscv: rvv-0.9: integer add-with-carry/subtract-with-borrow frank.chang
2020-07-22 9:16 ` [RFC v2 47/76] target/riscv: rvv-0.9: narrowing integer right shift instructions frank.chang
2020-07-30 21:02 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 48/76] target/riscv: rvv-0.9: widening integer multiply-add instructions frank.chang
2020-07-30 21:04 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 49/76] target/riscv: rvv-0.9: quad-widening " frank.chang
2020-07-30 21:19 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 50/76] target/riscv: rvv-0.9: single-width saturating add and subtract instructions frank.chang
2020-07-30 21:24 ` Richard Henderson
2020-08-04 2:40 ` Frank Chang
2020-08-05 16:48 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 51/76] target/riscv: rvv-0.9: integer comparison instructions frank.chang
2020-07-30 21:30 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 52/76] fpu: implement full set compare for fp16 frank.chang
2020-07-22 11:35 ` Alex Bennée
2020-07-22 9:16 ` [RFC v2 53/76] target/riscv: use softfloat lib float16 comparison functions frank.chang
2020-07-30 21:32 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 54/76] target/riscv: rvv-0.9: floating-point compare instructions frank.chang
2020-07-22 9:16 ` [RFC v2 55/76] target/riscv: rvv-0.9: single-width integer reduction instructions frank.chang
2020-07-22 9:16 ` [RFC v2 56/76] target/riscv: rvv-0.9: widening " frank.chang
2020-07-31 15:13 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 57/76] target/riscv: rvv-0.9: mask-register logical instructions frank.chang
2020-07-22 9:16 ` [RFC v2 58/76] target/riscv: rvv-0.9: slide instructions frank.chang
2020-07-31 15:57 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 59/76] target/riscv: rvv-0.9: floating-point " frank.chang
2020-07-31 16:05 ` Richard Henderson
2020-08-03 10:35 ` Frank Chang
2020-08-03 18:57 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 60/76] target/riscv: rvv-0.9: narrowing fixed-point clip instructions frank.chang
2020-07-31 16:07 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 61/76] target/riscv: rvv-0.9: floating-point/integer type-convert instructions frank.chang
2020-07-31 16:32 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 62/76] target/riscv: rvv-0.9: single-width floating-point reduction frank.chang
2020-07-31 16:45 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 63/76] target/riscv: rvv-0.9: widening floating-point reduction instructions frank.chang
2020-07-22 9:16 ` [RFC v2 64/76] target/riscv: rvv-0.9: single-width scaling shift instructions frank.chang
2020-07-31 16:59 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 65/76] target/riscv: rvv-0.9: remove widening saturating scaled multiply-add frank.chang
2020-07-31 17:02 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 66/76] target/riscv: rvv-0.9: remove vmford.vv and vmford.vf frank.chang
2020-07-31 17:03 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 67/76] target/riscv: rvv-0.9: remove integer extract instruction frank.chang
2020-07-31 17:05 ` Richard Henderson
2020-07-22 9:16 ` frank.chang [this message]
2020-07-22 9:16 ` [RFC v2 69/76] target/riscv: rvv-0.9: floating-point min/max instructions frank.chang
2020-07-22 9:16 ` [RFC v2 70/76] softfloat: add fp16 and uint8/int8 interconvert functions frank.chang
2020-07-22 9:16 ` [RFC v2 71/76] target/riscv: rvv-0.9: widening floating-point/integer type-convert frank.chang
2020-07-31 17:10 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 72/76] target/riscv: rvv-0.9: narrowing " frank.chang
2020-07-31 17:18 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 73/76] fpu: fix float16 nan check frank.chang
2020-07-22 9:16 ` [RFC v2 74/76] target/riscv: gdb: modify gdb csr xml file to align with csr register map frank.chang
2020-07-22 9:16 ` [RFC v2 75/76] target/riscv: gdb: support vector registers for rv64 frank.chang
2020-07-31 17:25 ` Richard Henderson
2020-08-03 11:31 ` Alex Bennée
2020-07-22 9:16 ` [RFC v2 76/76] target/riscv: gdb: support vector registers for rv32 frank.chang
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