From: Eduardo Habkost <ehabkost@redhat.com>
To: qemu-devel@nongnu.org
Cc: "Daniel P. Berrange" <berrange@redhat.com>,
qemu-riscv@nongnu.org,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Alistair Francis <Alistair.Francis@wdc.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: [PATCH v3 09/74] sifive_u: Rename memmap enum constants
Date: Tue, 25 Aug 2020 15:20:05 -0400 [thread overview]
Message-ID: <20200825192110.3528606-10-ehabkost@redhat.com> (raw)
In-Reply-To: <20200825192110.3528606-1-ehabkost@redhat.com>
Some of the enum constant names conflict with the QOM type check
macros (SIFIVE_U_OTP, SIFIVE_U_PRCI). This needs to be addressed
to allow us to transform the QOM type check macros into functions
generated by OBJECT_DECLARE_TYPE().
Rename all the constants to SIFIVE_U_DEV_*, to avoid conflicts.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
Changes v2 -> v3:
* Solved conflicts on rebase to latest qemu.git
* As this is a new patch, Reviewed-by lines from Alistair Francis
and Daniel P. Berrangé were dropped
Changes v1 -> v2:
* Added more details to commit message
---
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: qemu-riscv@nongnu.org
Cc: qemu-devel@nongnu.org
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
include/hw/riscv/sifive_u.h | 32 ++++----
hw/riscv/sifive_u.c | 146 ++++++++++++++++++------------------
2 files changed, 89 insertions(+), 89 deletions(-)
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index d3c0c00d10..2cefc611dd 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -68,22 +68,22 @@ typedef struct SiFiveUState {
} SiFiveUState;
enum {
- SIFIVE_U_DEBUG,
- SIFIVE_U_MROM,
- SIFIVE_U_CLINT,
- SIFIVE_U_L2CC,
- SIFIVE_U_L2LIM,
- SIFIVE_U_PLIC,
- SIFIVE_U_PRCI,
- SIFIVE_U_UART0,
- SIFIVE_U_UART1,
- SIFIVE_U_GPIO,
- SIFIVE_U_OTP,
- SIFIVE_U_DMC,
- SIFIVE_U_FLASH0,
- SIFIVE_U_DRAM,
- SIFIVE_U_GEM,
- SIFIVE_U_GEM_MGMT
+ SIFIVE_U_DEV_DEBUG,
+ SIFIVE_U_DEV_MROM,
+ SIFIVE_U_DEV_CLINT,
+ SIFIVE_U_DEV_L2CC,
+ SIFIVE_U_DEV_L2LIM,
+ SIFIVE_U_DEV_PLIC,
+ SIFIVE_U_DEV_PRCI,
+ SIFIVE_U_DEV_UART0,
+ SIFIVE_U_DEV_UART1,
+ SIFIVE_U_DEV_GPIO,
+ SIFIVE_U_DEV_OTP,
+ SIFIVE_U_DEV_DMC,
+ SIFIVE_U_DEV_FLASH0,
+ SIFIVE_U_DEV_DRAM,
+ SIFIVE_U_DEV_GEM,
+ SIFIVE_U_DEV_GEM_MGMT
};
enum {
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 18301e6fa5..b0555a2f7a 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -69,22 +69,22 @@ static const struct MemmapEntry {
hwaddr base;
hwaddr size;
} sifive_u_memmap[] = {
- [SIFIVE_U_DEBUG] = { 0x0, 0x100 },
- [SIFIVE_U_MROM] = { 0x1000, 0xf000 },
- [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 },
- [SIFIVE_U_L2CC] = { 0x2010000, 0x1000 },
- [SIFIVE_U_L2LIM] = { 0x8000000, 0x2000000 },
- [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 },
- [SIFIVE_U_PRCI] = { 0x10000000, 0x1000 },
- [SIFIVE_U_UART0] = { 0x10010000, 0x1000 },
- [SIFIVE_U_UART1] = { 0x10011000, 0x1000 },
- [SIFIVE_U_GPIO] = { 0x10060000, 0x1000 },
- [SIFIVE_U_OTP] = { 0x10070000, 0x1000 },
- [SIFIVE_U_GEM] = { 0x10090000, 0x2000 },
- [SIFIVE_U_GEM_MGMT] = { 0x100a0000, 0x1000 },
- [SIFIVE_U_DMC] = { 0x100b0000, 0x10000 },
- [SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 },
- [SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
+ [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 },
+ [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 },
+ [SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 },
+ [SIFIVE_U_DEV_L2CC] = { 0x2010000, 0x1000 },
+ [SIFIVE_U_DEV_L2LIM] = { 0x8000000, 0x2000000 },
+ [SIFIVE_U_DEV_PLIC] = { 0xc000000, 0x4000000 },
+ [SIFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 },
+ [SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 },
+ [SIFIVE_U_DEV_UART1] = { 0x10011000, 0x1000 },
+ [SIFIVE_U_DEV_GPIO] = { 0x10060000, 0x1000 },
+ [SIFIVE_U_DEV_OTP] = { 0x10070000, 0x1000 },
+ [SIFIVE_U_DEV_GEM] = { 0x10090000, 0x2000 },
+ [SIFIVE_U_DEV_GEM_MGMT] = { 0x100a0000, 0x1000 },
+ [SIFIVE_U_DEV_DMC] = { 0x100b0000, 0x10000 },
+ [SIFIVE_U_DEV_FLASH0] = { 0x20000000, 0x10000000 },
+ [SIFIVE_U_DEV_DRAM] = { 0x80000000, 0x0 },
};
#define OTP_SERIAL 1
@@ -143,10 +143,10 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
g_free(nodename);
nodename = g_strdup_printf("/memory@%lx",
- (long)memmap[SIFIVE_U_DRAM].base);
+ (long)memmap[SIFIVE_U_DEV_DRAM].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base,
+ memmap[SIFIVE_U_DEV_DRAM].base >> 32, memmap[SIFIVE_U_DEV_DRAM].base,
mem_size >> 32, mem_size);
qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
g_free(nodename);
@@ -201,39 +201,39 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
g_free(nodename);
}
nodename = g_strdup_printf("/soc/clint@%lx",
- (long)memmap[SIFIVE_U_CLINT].base);
+ (long)memmap[SIFIVE_U_DEV_CLINT].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_CLINT].base,
- 0x0, memmap[SIFIVE_U_CLINT].size);
+ 0x0, memmap[SIFIVE_U_DEV_CLINT].base,
+ 0x0, memmap[SIFIVE_U_DEV_CLINT].size);
qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
cells, ms->smp.cpus * sizeof(uint32_t) * 4);
g_free(cells);
g_free(nodename);
nodename = g_strdup_printf("/soc/otp@%lx",
- (long)memmap[SIFIVE_U_OTP].base);
+ (long)memmap[SIFIVE_U_DEV_OTP].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE);
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_OTP].base,
- 0x0, memmap[SIFIVE_U_OTP].size);
+ 0x0, memmap[SIFIVE_U_DEV_OTP].base,
+ 0x0, memmap[SIFIVE_U_DEV_OTP].size);
qemu_fdt_setprop_string(fdt, nodename, "compatible",
"sifive,fu540-c000-otp");
g_free(nodename);
prci_phandle = phandle++;
nodename = g_strdup_printf("/soc/clock-controller@%lx",
- (long)memmap[SIFIVE_U_PRCI].base);
+ (long)memmap[SIFIVE_U_DEV_PRCI].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle);
qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1);
qemu_fdt_setprop_cells(fdt, nodename, "clocks",
hfclk_phandle, rtcclk_phandle);
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_PRCI].base,
- 0x0, memmap[SIFIVE_U_PRCI].size);
+ 0x0, memmap[SIFIVE_U_DEV_PRCI].base,
+ 0x0, memmap[SIFIVE_U_DEV_PRCI].size);
qemu_fdt_setprop_string(fdt, nodename, "compatible",
"sifive,fu540-c000-prci");
g_free(nodename);
@@ -257,7 +257,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
g_free(nodename);
}
nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
- (long)memmap[SIFIVE_U_PLIC].base);
+ (long)memmap[SIFIVE_U_DEV_PLIC].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
@@ -265,8 +265,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t));
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_PLIC].base,
- 0x0, memmap[SIFIVE_U_PLIC].size);
+ 0x0, memmap[SIFIVE_U_DEV_PLIC].base,
+ 0x0, memmap[SIFIVE_U_DEV_PLIC].size);
qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
@@ -275,7 +275,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
gpio_phandle = phandle++;
nodename = g_strdup_printf("/soc/gpio@%lx",
- (long)memmap[SIFIVE_U_GPIO].base);
+ (long)memmap[SIFIVE_U_DEV_GPIO].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle);
qemu_fdt_setprop_cells(fdt, nodename, "clocks",
@@ -285,8 +285,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2);
qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0);
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_GPIO].base,
- 0x0, memmap[SIFIVE_U_GPIO].size);
+ 0x0, memmap[SIFIVE_U_DEV_GPIO].base,
+ 0x0, memmap[SIFIVE_U_DEV_GPIO].size);
qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0,
SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3,
SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6,
@@ -304,11 +304,11 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
g_free(nodename);
nodename = g_strdup_printf("/soc/cache-controller@%lx",
- (long)memmap[SIFIVE_U_L2CC].base);
+ (long)memmap[SIFIVE_U_DEV_L2CC].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_L2CC].base,
- 0x0, memmap[SIFIVE_U_L2CC].size);
+ 0x0, memmap[SIFIVE_U_DEV_L2CC].base,
+ 0x0, memmap[SIFIVE_U_DEV_L2CC].size);
qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
SIFIVE_U_L2CC_IRQ0, SIFIVE_U_L2CC_IRQ1, SIFIVE_U_L2CC_IRQ2);
qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
@@ -323,15 +323,15 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
phy_phandle = phandle++;
nodename = g_strdup_printf("/soc/ethernet@%lx",
- (long)memmap[SIFIVE_U_GEM].base);
+ (long)memmap[SIFIVE_U_DEV_GEM].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_string(fdt, nodename, "compatible",
"sifive,fu540-c000-gem");
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_GEM].base,
- 0x0, memmap[SIFIVE_U_GEM].size,
- 0x0, memmap[SIFIVE_U_GEM_MGMT].base,
- 0x0, memmap[SIFIVE_U_GEM_MGMT].size);
+ 0x0, memmap[SIFIVE_U_DEV_GEM].base,
+ 0x0, memmap[SIFIVE_U_DEV_GEM].size,
+ 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].base,
+ 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].size);
qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle);
@@ -352,19 +352,19 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
g_free(nodename);
nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
- (long)memmap[SIFIVE_U_GEM].base);
+ (long)memmap[SIFIVE_U_DEV_GEM].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle);
qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
g_free(nodename);
nodename = g_strdup_printf("/soc/serial@%lx",
- (long)memmap[SIFIVE_U_UART0].base);
+ (long)memmap[SIFIVE_U_DEV_UART0].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_UART0].base,
- 0x0, memmap[SIFIVE_U_UART0].size);
+ 0x0, memmap[SIFIVE_U_DEV_UART0].base,
+ 0x0, memmap[SIFIVE_U_DEV_UART0].size);
qemu_fdt_setprop_cells(fdt, nodename, "clocks",
prci_phandle, PRCI_CLK_TLCLK);
qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
@@ -396,7 +396,7 @@ static void sifive_u_machine_init(MachineState *machine)
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
MemoryRegion *flash0 = g_new(MemoryRegion, 1);
- target_ulong start_addr = memmap[SIFIVE_U_DRAM].base;
+ target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
uint32_t start_addr_hi32 = 0x00000000;
int i;
uint32_t fdt_load_addr;
@@ -411,13 +411,13 @@ static void sifive_u_machine_init(MachineState *machine)
/* register RAM */
memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
machine->ram_size, &error_fatal);
- memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base,
+ memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base,
main_mem);
/* register QSPI0 Flash */
memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0",
- memmap[SIFIVE_U_FLASH0].size, &error_fatal);
- memory_region_add_subregion(system_memory, memmap[SIFIVE_U_FLASH0].base,
+ memmap[SIFIVE_U_DEV_FLASH0].size, &error_fatal);
+ memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_FLASH0].base,
flash0);
/* register gpio-restart */
@@ -443,14 +443,14 @@ static void sifive_u_machine_init(MachineState *machine)
switch (s->msel) {
case MSEL_MEMMAP_QSPI0_FLASH:
- start_addr = memmap[SIFIVE_U_FLASH0].base;
+ start_addr = memmap[SIFIVE_U_DEV_FLASH0].base;
break;
case MSEL_L2LIM_QSPI0_FLASH:
case MSEL_L2LIM_QSPI2_SD:
- start_addr = memmap[SIFIVE_U_L2LIM].base;
+ start_addr = memmap[SIFIVE_U_DEV_L2LIM].base;
break;
default:
- start_addr = memmap[SIFIVE_U_DRAM].base;
+ start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
break;
}
@@ -478,7 +478,7 @@ static void sifive_u_machine_init(MachineState *machine)
}
/* Compute the fdt load address in dram */
- fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DRAM].base,
+ fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base,
machine->ram_size, s->fdt);
#if defined(TARGET_RISCV64)
start_addr_hi32 = start_addr >> 32;
@@ -510,10 +510,10 @@ static void sifive_u_machine_init(MachineState *machine)
reset_vec[i] = cpu_to_le32(reset_vec[i]);
}
rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
- memmap[SIFIVE_U_MROM].base, &address_space_memory);
+ memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory);
- riscv_rom_copy_firmware_info(memmap[SIFIVE_U_MROM].base,
- memmap[SIFIVE_U_MROM].size,
+ riscv_rom_copy_firmware_info(memmap[SIFIVE_U_DEV_MROM].base,
+ memmap[SIFIVE_U_DEV_MROM].size,
sizeof(reset_vec), kernel_entry);
}
@@ -653,8 +653,8 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
/* boot rom */
memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom",
- memmap[SIFIVE_U_MROM].size, &error_fatal);
- memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base,
+ memmap[SIFIVE_U_DEV_MROM].size, &error_fatal);
+ memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_MROM].base,
mask_rom);
/*
@@ -667,8 +667,8 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
* too generous to misbehaving guests.
*/
memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim",
- memmap[SIFIVE_U_L2LIM].size, &error_fatal);
- memory_region_add_subregion(system_memory, memmap[SIFIVE_U_L2LIM].base,
+ memmap[SIFIVE_U_DEV_L2LIM].size, &error_fatal);
+ memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_L2LIM].base,
l2lim_mem);
/* create PLIC hart topology configuration string */
@@ -686,7 +686,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
}
/* MMIO */
- s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base,
+ s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base,
plic_hart_config,
SIFIVE_U_PLIC_NUM_SOURCES,
SIFIVE_U_PLIC_NUM_PRIORITIES,
@@ -696,26 +696,26 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
SIFIVE_U_PLIC_ENABLE_STRIDE,
SIFIVE_U_PLIC_CONTEXT_BASE,
SIFIVE_U_PLIC_CONTEXT_STRIDE,
- memmap[SIFIVE_U_PLIC].size);
+ memmap[SIFIVE_U_DEV_PLIC].size);
g_free(plic_hart_config);
- sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
+ sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART0].base,
serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
- sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
+ sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base,
serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
- sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
- memmap[SIFIVE_U_CLINT].size, ms->smp.cpus,
+ sifive_clint_create(memmap[SIFIVE_U_DEV_CLINT].base,
+ memmap[SIFIVE_U_DEV_CLINT].size, ms->smp.cpus,
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {
return;
}
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_DEV_PRCI].base);
qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
return;
}
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_GPIO].base);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_DEV_GPIO].base);
/* Pass all GPIOs to the SOC layer so they are available to the board */
qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
@@ -731,7 +731,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) {
return;
}
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_DEV_OTP].base);
/* FIXME use qdev NIC properties instead of nd_table[] */
if (nd->used) {
@@ -743,18 +743,18 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) {
return;
}
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_DEV_GEM].base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ));
create_unimplemented_device("riscv.sifive.u.gem-mgmt",
- memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
+ memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT].size);
create_unimplemented_device("riscv.sifive.u.dmc",
- memmap[SIFIVE_U_DMC].base, memmap[SIFIVE_U_DMC].size);
+ memmap[SIFIVE_U_DEV_DMC].base, memmap[SIFIVE_U_DEV_DMC].size);
create_unimplemented_device("riscv.sifive.u.l2cc",
- memmap[SIFIVE_U_L2CC].base, memmap[SIFIVE_U_L2CC].size);
+ memmap[SIFIVE_U_DEV_L2CC].base, memmap[SIFIVE_U_DEV_L2CC].size);
}
static Property sifive_u_soc_props[] = {
--
2.26.2
next prev parent reply other threads:[~2020-08-25 19:27 UTC|newest]
Thread overview: 101+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-25 19:19 [PATCH v3 00/74] qom: Automated conversion of type checking boilerplate Eduardo Habkost
2020-08-25 19:19 ` [PATCH v3 01/74] e1000: Rename QOM class cast macros Eduardo Habkost
2020-08-25 19:19 ` [PATCH v3 02/74] megasas: " Eduardo Habkost
2020-08-25 19:19 ` [PATCH v3 03/74] vmw_pvscsi: " Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 04/74] pl110: Rename pl110_version enum values Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 05/74] allwinner-h3: Rename memmap enum constants Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 06/74] aspeed_soc: Rename memmap/irqmap " Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 07/74] opentitan: Rename memmap " Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 08/74] sifive_e: " Eduardo Habkost
2020-08-25 19:20 ` Eduardo Habkost [this message]
2020-08-25 19:20 ` [PATCH v3 10/74] aspeed_timer: Fix ASPEED_TIMER macro definition Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 11/74] versatile: Fix typo in PCI_VPB_HOST definition Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 12/74] virtio-ccw: Fix definition of VIRTIO_CCW_BUS_GET_CLASS Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 13/74] hvf: Add missing include Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 14/74] hcd-dwc2: Rename USB_*CLASS macros for consistency Eduardo Habkost
2020-08-26 5:10 ` Gerd Hoffmann
2020-08-25 19:20 ` [PATCH v3 15/74] tulip: Move TulipState typedef to header Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 16/74] throttle-groups: Move ThrottleGroup " Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 17/74] pci: Move PCIBusClass typedef to pci.h Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 18/74] i8254: Move PITCommonState/PITCommonClass typedefs to i8254.h Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 19/74] hvf: Move HVFState typedef to hvf.h Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 20/74] mcf_fec: Move mcf_fec_state typedef to header Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 21/74] s390_flic: Move KVMS390FLICState " Eduardo Habkost
2020-08-27 8:08 ` Thomas Huth
2020-08-25 19:20 ` [PATCH v3 22/74] can_emu: Delete macros for non-existing typedef Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 23/74] nubus: Delete unused NUBUS_BRIDGE macro Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 24/74] platform-bus: Delete macros for non-existing typedef Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 25/74] armsse: Rename QOM macros to avoid conflicts Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 26/74] xen-legacy-backend: Add missing typedef XenLegacyDevice Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 27/74] spapr: Move typedef SpaprMachineState to spapr.h Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 28/74] s390x: Move typedef SCLPEventFacility to event-facility.h Eduardo Habkost
2020-08-27 8:07 ` Thomas Huth
2020-08-25 19:20 ` [PATCH v3 29/74] vhost-user-gpu: Move QOM macro to header Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 30/74] ahci: Move QOM macros " Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 31/74] i8257: Move QOM macro " Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 32/74] ahci: " Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 33/74] pckbd: " Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 34/74] vmbus: Move QOM macros to vmbus.h Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 35/74] virtio-serial-bus: Move QOM macros to header Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 36/74] piix: " Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 37/74] auxbus: " Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 38/74] rocker: " Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 39/74] pxa2xx: " Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 40/74] mptsas: " Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 41/74] kvm: Move QOM macros to kvm.h Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 42/74] vfio/pci: Move QOM macros to header Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 43/74] nubus: Rename class type checking macros Eduardo Habkost
2020-08-26 10:18 ` Laurent Vivier
2020-08-25 19:20 ` [PATCH v3 44/74] imx_ccm: Rename IMX_GET_CLASS macro Eduardo Habkost
2020-08-31 18:45 ` Peter Maydell
2020-08-25 19:20 ` [PATCH v3 45/74] mos6522: Rename QOM macros Eduardo Habkost
2020-08-31 18:46 ` Peter Maydell
2020-08-25 19:20 ` [PATCH v3 46/74] x86-iommu: Rename QOM type macros Eduardo Habkost
2020-08-31 19:02 ` Peter Xu
2020-08-25 19:20 ` [PATCH v3 47/74] rdma: Rename INTERFACE_RDMA_PROVIDER_CLASS macro Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 48/74] s390-virtio-ccw: Rename S390_MACHINE_CLASS macro Eduardo Habkost
2020-08-26 7:16 ` Cornelia Huck
2020-08-25 19:20 ` [PATCH v3 49/74] swim: Rename struct SWIM to Swim Eduardo Habkost
2020-08-26 10:19 ` Laurent Vivier
2020-08-25 19:20 ` [PATCH v3 50/74] migration: Rename class type checking macros Eduardo Habkost
2020-08-26 7:59 ` Juan Quintela
2020-08-25 19:20 ` [PATCH v3 51/74] arm: Fix typo in AARCH64_CPU_GET_CLASS definition Eduardo Habkost
2020-08-31 18:45 ` Peter Maydell
2020-08-25 19:20 ` [PATCH v3 52/74] rx: Rename QOM type check macros Eduardo Habkost
2020-08-31 18:48 ` Peter Maydell
2020-08-25 19:20 ` [PATCH v3 53/74] rx: Move typedef RXCPU to cpu-qom.h Eduardo Habkost
2020-08-31 18:48 ` Peter Maydell
2020-08-25 19:20 ` [PATCH v3 54/74] qom: make object_ref/unref use a void * instead of Object * Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 55/74] qom: provide convenient macros for declaring and defining types Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 56/74] qom: Allow class type name to be specified in OBJECT_DECLARE* Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 57/74] qom: DECLARE_*_CHECKERS macros Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 58/74] qom: Make type checker functions accept const pointers Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 59/74] qom: TYPE_INFO macro Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 60/74] codeconverter: script for automating QOM code cleanups Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 61/74] [automated] Delete duplicate QOM typedefs Eduardo Habkost
2020-08-25 19:20 ` [PATCH v3 62/74] [automated] Use TYPE_INFO macro Eduardo Habkost
2020-08-26 8:02 ` Juan Quintela
2020-08-25 19:20 ` [PATCH v3 63/74] [automated] Use TYPE_INFO macro (pass 2) Eduardo Habkost
2020-08-25 19:21 ` [PATCH v3 64/74] [automated] Move QOM typedefs and add missing includes Eduardo Habkost
2020-08-26 8:05 ` Juan Quintela
2020-08-25 19:21 ` [PATCH v3 65/74] [automated] Move QOM typedefs and add missing includes (pass 2) Eduardo Habkost
2020-08-26 8:03 ` Juan Quintela
2020-08-25 19:21 ` [PATCH v3 66/74] [automated] Use DECLARE_*CHECKER* macros Eduardo Habkost
2020-08-26 8:08 ` Juan Quintela
2020-08-25 19:21 ` [PATCH v3 67/74] [automated] Use DECLARE_*CHECKER* macros (pass 2) Eduardo Habkost
2020-08-26 8:06 ` Juan Quintela
2020-08-25 19:21 ` [PATCH v3 68/74] [semi-automated] Use DECLARE_*CHECKER* when possible (--force mode) Eduardo Habkost
2020-08-25 19:21 ` [PATCH v3 69/74] [automated] Use OBJECT_DECLARE_TYPE where possible Eduardo Habkost
2020-08-25 19:21 ` [PATCH v3 70/74] [automated] Use OBJECT_DECLARE_TYPE where possible (pass 2) Eduardo Habkost
2020-08-25 19:21 ` [PATCH v3 71/74] [automated] Use OBJECT_DECLARE_SIMPLE_TYPE when possible Eduardo Habkost
2020-08-25 19:21 ` [PATCH v3 72/74] [automated] Remove redundant instance_size/class_size fields Eduardo Habkost
2020-08-26 15:54 ` Eduardo Habkost
2020-08-25 19:21 ` [PATCH v3 73/74] crypto: use QOM macros for declaration/definition of secret types Eduardo Habkost
2020-08-25 19:21 ` [PATCH v3 74/74] crypto: use QOM macros for declaration/definition of TLS creds types Eduardo Habkost
2020-08-26 10:22 ` [PATCH v3 00/74] qom: Automated conversion of type checking boilerplate Roman Bolshakov
2020-08-26 11:18 ` Eduardo Habkost
2020-08-26 17:06 ` Roman Bolshakov
2020-08-27 18:18 ` Eduardo Habkost
2020-08-31 17:23 ` Eduardo Habkost
2020-08-31 18:52 ` Peter Maydell
2020-08-31 19:07 ` Eduardo Habkost
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