From: andrew@daynix.com
To: qemu-devel@nongnu.org
Cc: mst@redhat.com
Subject: [PATCH v3 1/2] hw/virtio-pci Added counter for pcie capabilities offsets.
Date: Mon, 5 Oct 2020 14:56:00 +0300 [thread overview]
Message-ID: <20201005115601.103791-2-andrew@daynix.com> (raw)
In-Reply-To: <20201005115601.103791-1-andrew@daynix.com>
From: Andrew <andrew@daynix.com>
Removed hardcoded offset for ats. Added cap offset counter
for future capabilities like AER.
Signed-off-by: Andrew Melnychenko <andrew@daynix.com>
---
hw/virtio/virtio-pci.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
index 5bc769f685..ae60c1e249 100644
--- a/hw/virtio/virtio-pci.c
+++ b/hw/virtio/virtio-pci.c
@@ -1788,6 +1788,7 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
if (pcie_port && pci_is_express(pci_dev)) {
int pos;
+ uint16_t last_pcie_cap_offset = PCI_CONFIG_SPACE_SIZE;
pos = pcie_endpoint_cap_init(pci_dev, 0);
assert(pos > 0);
@@ -1823,7 +1824,8 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
}
if (proxy->flags & VIRTIO_PCI_FLAG_ATS) {
- pcie_ats_init(pci_dev, 256);
+ pcie_ats_init(pci_dev, last_pcie_cap_offset);
+ last_pcie_cap_offset += PCI_EXT_CAP_ATS_SIZEOF;
}
if (proxy->flags & VIRTIO_PCI_FLAG_INIT_FLR) {
--
2.28.0
next prev parent reply other threads:[~2020-10-05 11:28 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-05 11:55 [PATCH v3 0/2] hw/virtio-pci: AER capability andrew
2020-10-05 11:56 ` andrew [this message]
2020-10-05 11:56 ` [PATCH v3 2/2] hw/virtio-pci Added " andrew
2020-10-05 17:46 ` Michael S. Tsirkin
2020-10-07 6:41 ` Yan Vugenfirer
2020-10-07 7:13 ` Andrew Melnichenko
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