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a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1602338224; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=MOTPkXjvC2zXyPDpTmjJaf2TrTkZXbIsOjedNDmg/rk=; b=FCXcW2HPG1yj2RzwiuY/fAD8oswAAAspJiOBgCOK1E3Y1WiSgMTtYN+XCAA46Ds8WgujGY 3/g2DX2v4GCfLE2HYYFsxoGOD7Rv0kCiuPGWLH8aGX65LX40waKiUBWd20fiDgZuPJLNTJ Cz8+fAIjrAf0hdltxnHXzTKmxCuKNgurbPJg+2SxQ/ZZ2Nu0AxFmZZxh4g/dK/fHraG/xS +9y03q4IXxxgOnORfBDl4kDyI3NwLJHiLUMAf5ZyzAu+hPdWtt1dRRU3Zt4Mk39wf8f+cE E2JgoRKp3ZMVfgB3w0MvCEXQQLoqu97A5RjnswQawUnv/8+l5d6oVEifKqZZ5w== From: Luc Michel To: qemu-devel@nongnu.org Subject: [PATCH v3 09/15] hw/misc/bcm2835_cprman: implement PLL channels behaviour Date: Sat, 10 Oct 2020 15:57:53 +0200 Message-Id: <20201010135759.437903-10-luc@lmichel.fr> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201010135759.437903-1-luc@lmichel.fr> References: <20201010135759.437903-1-luc@lmichel.fr> MIME-Version: 1.0 Content-Type: text/plain; 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pharaoh.lmichel.fr Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/10 07:32:09 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Andrew Baumann , Paul Zimmerman , Niek Linnenbank , qemu-arm@nongnu.org, Havard Skinnemoen Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" A PLL channel is able to further divide the generated PLL frequency. The divider is given in the CTRL_A2W register. Some channels have an additional fixed divider which is always applied to the signal. Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Luc Michel --- hw/misc/bcm2835_cprman.c | 33 ++++++++++++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/hw/misc/bcm2835_cprman.c b/hw/misc/bcm2835_cprman.c index 12fa78181b..71c1d7b9e7 100644 --- a/hw/misc/bcm2835_cprman.c +++ b/hw/misc/bcm2835_cprman.c @@ -132,13 +132,44 @@ static const TypeInfo cprman_pll_info = { }; /* PLL channel */ +static bool pll_channel_is_enabled(CprmanPllChannelState *channel) +{ + /* + * XXX I'm not sure of the purpose of the LOAD field. The Linux driver does + * not set it when enabling the channel, but does clear it when disabling + * it. + */ + return !FIELD_EX32(*channel->reg_a2w_ctrl, A2W_PLLx_CHANNELy, DISABLE) + && !(*channel->reg_cm & channel->hold_mask); +} + static void pll_channel_update(CprmanPllChannelState *channel) { - clock_update(channel->out, 0); + uint64_t freq, div; + + if (!pll_channel_is_enabled(channel)) { + clock_update(channel->out, 0); + return; + } + + div = FIELD_EX32(*channel->reg_a2w_ctrl, A2W_PLLx_CHANNELy, DIV); + + if (!div) { + /* + * It seems that when the divider value is 0, it is considered as + * being maximum by the hardware (see the Linux driver). + */ + div = R_A2W_PLLx_CHANNELy_DIV_MASK; + } + + /* Some channels have an additional fixed divider */ + freq = clock_get_hz(channel->pll_in) / (div * channel->fixed_divider); + + clock_update_hz(channel->out, freq); } /* Update a PLL and all its channels */ static void pll_update_all_channels(BCM2835CprmanState *s, CprmanPllState *pll) -- 2.28.0