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23 Oct 2020 08:12:57 -0700 IronPort-SDR: hw8s0of+U4APhC+odBxKjrQniUGkqy3jjHeJDt1lBl2ARSNTBp/1wkQElTj92yLZ1pnS/LixTP yZTzwQ1YfJm7tpD1ftro4pWzjvM3MnHOUKKIJKy13bYjAGoPxpZf2C5h2xPbcObN8AvMuwrpuk JehLccy++dT57wrAyrgqrFWSAB1mDe4j2q51I9QKvK1FlNCguIvDRZ+8xww9kqx2b+8Zy6jozm iFE+RNzFijvP7KgUFGRFHItL/zFE4KDssBfQzmwNaOg1OpJ56V5fyMON5YQXDXmHrLauem2QkB liY= WDCIronportException: Internal Received: from cnf006900.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.60.46]) by uls-op-cesaip02.wdc.com with ESMTP; 23 Oct 2020 08:27:42 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Subject: [PULL 00/12] riscv-to-apply queue Date: Fri, 23 Oct 2020 08:16:07 -0700 Message-Id: <20201023151619.3175155-1-alistair.francis@wdc.com> X-Mailer: git-send-email 2.28.0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=558518344=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/23 11:27:42 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Alistair Francis Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The following changes since commit 4c5b97bfd0dd54dc27717ae8d1cd10e14eef1430: Merge remote-tracking branch 'remotes/kraxel/tags/modules-20201022-pull-request' into staging (2020-10-22 12:33:21 +0100) are available in the Git repository at: git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20201023 for you to fetch changes up to 51b6c1bbc3dd1b139a9e9b021d87bcfd7d82299e: hw/misc/sifive_u_otp: Add backend drive support (2020-10-22 12:00:50 -0700) ---------------------------------------------------------------- A collection of RISC-V fixes for the next QEMU release. This includes: - Improvements to logging output - Hypervisor instruction fixups - The ability to load a noMMU kernel - SiFive OTP support ---------------------------------------------------------------- Alistair Francis (5): riscv: Convert interrupt logs to use qemu_log_mask() hw/riscv: sifive_u: Allow specifying the CPU hw/riscv: Return the end address of the loaded firmware hw/riscv: Add a riscv_is_32_bit() function hw/riscv: Load the kernel after the firmware Bin Meng (1): hw/intc: Move sifive_plic.h to the include directory Georg Kotheimer (3): target/riscv: Fix update of hstatus.SPVP target/riscv: Fix update of hstatus.GVA in riscv_cpu_do_interrupt target/riscv: Fix implementation of HLVX.WU instruction Green Wan (2): hw/misc/sifive_u_otp: Add write function and write-once protection hw/misc/sifive_u_otp: Add backend drive support Yifei Jiang (1): target/riscv: raise exception to HS-mode at get_physical_address {hw => include/hw}/intc/sifive_plic.h | 0 include/hw/misc/sifive_u_otp.h | 5 ++ include/hw/riscv/boot.h | 13 +++-- include/hw/riscv/sifive_u.h | 1 + target/riscv/cpu.h | 10 ++-- hw/misc/sifive_u_otp.c | 95 ++++++++++++++++++++++++++++++++++- hw/riscv/boot.c | 56 +++++++++++++++------ hw/riscv/opentitan.c | 3 +- hw/riscv/sifive_e.c | 3 +- hw/riscv/sifive_u.c | 28 ++++++++--- hw/riscv/spike.c | 11 ++-- hw/riscv/virt.c | 11 ++-- target/riscv/cpu_helper.c | 50 +++++++++++++----- target/riscv/op_helper.c | 7 ++- 14 files changed, 238 insertions(+), 55 deletions(-) rename {hw => include/hw}/intc/sifive_plic.h (100%)