From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: [PATCH v2 26/28] hw/intc/armv7m_nvic: Implement read/write for RAS register block
Date: Thu, 19 Nov 2020 21:56:15 +0000 [thread overview]
Message-ID: <20201119215617.29887-27-peter.maydell@linaro.org> (raw)
In-Reply-To: <20201119215617.29887-1-peter.maydell@linaro.org>
The RAS feature has a block of memory-mapped registers at offset
0x5000 within the PPB. For a "minimal RAS" implementation we provide
no error records and so the only registers that exist in the block
are ERRIIDR and ERRDEVID.
The "RAZ/WI for privileged, BusFault for nonprivileged" behaviour
of the "nvic-default" region is actually valid for minimal-RAS,
so the main benefit of providing an explicit implementation of
the register block is more accurate LOG_UNIMP messages, and a
framework for where we could add a real RAS implementation later
if necessary.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/intc/armv7m_nvic.h | 1 +
hw/intc/armv7m_nvic.c | 56 +++++++++++++++++++++++++++++++++++
2 files changed, 57 insertions(+)
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
index 33b6d8810c7..39c71e15936 100644
--- a/include/hw/intc/armv7m_nvic.h
+++ b/include/hw/intc/armv7m_nvic.h
@@ -83,6 +83,7 @@ struct NVICState {
MemoryRegion sysreg_ns_mem;
MemoryRegion systickmem;
MemoryRegion systick_ns_mem;
+ MemoryRegion ras_mem;
MemoryRegion container;
MemoryRegion defaultmem;
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index c42b291f881..5ab77a3530c 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -2530,6 +2530,56 @@ static const MemoryRegionOps nvic_systick_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
+
+static MemTxResult ras_read(void *opaque, hwaddr addr,
+ uint64_t *data, unsigned size,
+ MemTxAttrs attrs)
+{
+ if (attrs.user) {
+ return MEMTX_ERROR;
+ }
+
+ switch (addr) {
+ case 0xe10: /* ERRIIDR */
+ /* architect field = Arm; product/variant/revision 0 */
+ *data = 0x43b;
+ break;
+ case 0xfc8: /* ERRDEVID */
+ /* Minimal RAS: we implement 0 error record indexes */
+ *data = 0;
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "Read RAS register offset 0x%x\n",
+ (uint32_t)addr);
+ *data = 0;
+ break;
+ }
+ return MEMTX_OK;
+}
+
+static MemTxResult ras_write(void *opaque, hwaddr addr,
+ uint64_t value, unsigned size,
+ MemTxAttrs attrs)
+{
+ if (attrs.user) {
+ return MEMTX_ERROR;
+ }
+
+ switch (addr) {
+ default:
+ qemu_log_mask(LOG_UNIMP, "Write to RAS register offset 0x%x\n",
+ (uint32_t)addr);
+ break;
+ }
+ return MEMTX_OK;
+}
+
+static const MemoryRegionOps ras_ops = {
+ .read_with_attrs = ras_read,
+ .write_with_attrs = ras_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
/*
* Unassigned portions of the PPB space are RAZ/WI for privileged
* accesses, and fault for non-privileged accesses.
@@ -2877,6 +2927,12 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
&s->systick_ns_mem, 1);
}
+ if (cpu_isar_feature(aa32_ras, s->cpu)) {
+ memory_region_init_io(&s->ras_mem, OBJECT(s),
+ &ras_ops, s, "nvic_ras", 0x1000);
+ memory_region_add_subregion(&s->container, 0x5000, &s->ras_mem);
+ }
+
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container);
}
--
2.20.1
next prev parent reply other threads:[~2020-11-19 22:10 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-19 21:55 [PATCH v2 00/28] target/arm: Implement v8.1M and Cortex-M55 Peter Maydell
2020-11-19 21:55 ` [PATCH v2 01/28] hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault Peter Maydell
2020-11-19 21:55 ` [PATCH v2 02/28] target/arm: Implement v8.1M PXN extension Peter Maydell
2020-11-19 21:55 ` [PATCH v2 03/28] target/arm: Don't clobber ID_PFR1.Security on M-profile cores Peter Maydell
2020-11-19 21:55 ` [PATCH v2 04/28] target/arm: Implement VSCCLRM insn Peter Maydell
2020-11-19 21:55 ` [PATCH v2 05/28] target/arm: Implement CLRM instruction Peter Maydell
2020-11-19 21:55 ` [PATCH v2 06/28] target/arm: Enforce M-profile VMRS/VMSR register restrictions Peter Maydell
2020-11-19 21:55 ` [PATCH v2 07/28] target/arm: Refactor M-profile VMSR/VMRS handling Peter Maydell
2020-12-01 12:54 ` Richard Henderson
2020-11-19 21:55 ` [PATCH v2 08/28] target/arm: Move general-use constant expanders up in translate.c Peter Maydell
2020-11-19 21:55 ` [PATCH v2 09/28] target/arm: Implement VLDR/VSTR system register Peter Maydell
2020-12-01 13:11 ` Richard Henderson
2020-12-03 11:39 ` Peter Maydell
2020-12-03 16:14 ` Richard Henderson
2020-11-19 21:55 ` [PATCH v2 10/28] target/arm: Implement M-profile FPSCR_nzcvqc Peter Maydell
2020-12-01 13:16 ` Richard Henderson
2020-11-19 21:56 ` [PATCH v2 11/28] target/arm: Use new FPCR_NZCV_MASK constant Peter Maydell
2020-11-19 21:56 ` [PATCH v2 12/28] target/arm: Factor out preserve-fp-state from full_vfp_access_check() Peter Maydell
2020-11-19 22:18 ` Philippe Mathieu-Daudé
2020-11-19 21:56 ` [PATCH v2 13/28] target/arm: Implement FPCXT_S fp system register Peter Maydell
2020-12-01 13:40 ` Richard Henderson
2020-11-19 21:56 ` [PATCH v2 14/28] target/arm: Implement FPCXT_NS " Peter Maydell
2020-12-01 14:05 ` Richard Henderson
2020-11-19 21:56 ` [PATCH v2 15/28] hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1M Peter Maydell
2020-12-01 14:28 ` Richard Henderson
2020-11-19 21:56 ` [PATCH v2 16/28] target/arm: For v8.1M, always clear R0-R3, R12, APSR, EPSR on exception entry Peter Maydell
2020-12-01 14:33 ` Richard Henderson
2020-11-19 21:56 ` [PATCH v2 17/28] target/arm: In v8.1M, don't set HFSR.FORCED on vector table fetch failures Peter Maydell
2020-12-01 14:41 ` Richard Henderson
2020-11-19 21:56 ` [PATCH v2 18/28] target/arm: Implement v8.1M REVIDR register Peter Maydell
2020-12-01 14:43 ` Richard Henderson
2020-11-19 21:56 ` [PATCH v2 19/28] target/arm: Implement new v8.1M NOCP check for exception return Peter Maydell
2020-12-01 14:49 ` Richard Henderson
2020-11-19 21:56 ` [PATCH v2 20/28] target/arm: Implement new v8.1M VLLDM and VLSTM encodings Peter Maydell
2020-12-01 15:09 ` Richard Henderson
2020-11-19 21:56 ` [PATCH v2 21/28] hw/intc/armv7m_nvic: Correct handling of CCR.BFHFNMIGN Peter Maydell
2020-12-01 15:16 ` Richard Henderson
2020-12-01 15:22 ` Peter Maydell
2020-11-19 21:56 ` [PATCH v2 22/28] hw/intc/armv7m_nvic: Support v8.1M CCR.TRD bit Peter Maydell
2020-12-01 15:19 ` Richard Henderson
2020-11-19 21:56 ` [PATCH v2 23/28] target/arm: Implement CCR_S.TRD behaviour for SG insns Peter Maydell
2020-12-01 15:53 ` Richard Henderson
2020-11-19 21:56 ` [PATCH v2 24/28] hw/intc/armv7m_nvic: Fix "return from inactive handler" check Peter Maydell
2020-12-01 15:58 ` Richard Henderson
2020-11-19 21:56 ` [PATCH v2 25/28] target/arm: Implement M-profile "minimal RAS implementation" Peter Maydell
2020-12-01 16:04 ` Richard Henderson
2020-11-19 21:56 ` Peter Maydell [this message]
2020-12-01 16:11 ` [PATCH v2 26/28] hw/intc/armv7m_nvic: Implement read/write for RAS register block Richard Henderson
2020-11-19 21:56 ` [PATCH v2 27/28] hw/arm/armv7m: Correct typo in QOM object name Peter Maydell
2020-11-19 22:19 ` Philippe Mathieu-Daudé
2020-12-01 16:12 ` Richard Henderson
2020-11-19 21:56 ` [PATCH v2 28/28] target/arm: Implement Cortex-M55 model Peter Maydell
2020-12-01 16:24 ` Richard Henderson
2020-12-03 12:02 ` [PATCH v2 00/28] target/arm: Implement v8.1M and Cortex-M55 Peter Maydell
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