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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Subject: [PATCH 01/11] target/arm: Enforce word alignment for LDRD/STRD
Date: Tue, 24 Nov 2020 20:06:32 -0800	[thread overview]
Message-ID: <20201125040642.2339476-2-richard.henderson@linaro.org> (raw)
In-Reply-To: <20201125040642.2339476-1-richard.henderson@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/translate.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index 6d04ca3a8a..17883d00f4 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -6458,7 +6458,7 @@ static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a)
     addr = op_addr_rr_pre(s, a);
 
     tmp = tcg_temp_new_i32();
-    gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data);
+    gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN_4 | s->be_data);
     store_reg(s, a->rt, tmp);
 
     tcg_gen_addi_i32(addr, addr, 4);
@@ -6487,7 +6487,7 @@ static bool trans_STRD_rr(DisasContext *s, arg_ldst_rr *a)
     addr = op_addr_rr_pre(s, a);
 
     tmp = load_reg(s, a->rt);
-    gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data);
+    gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN_4 | s->be_data);
     tcg_temp_free_i32(tmp);
 
     tcg_gen_addi_i32(addr, addr, 4);
@@ -6595,7 +6595,7 @@ static bool op_ldrd_ri(DisasContext *s, arg_ldst_ri *a, int rt2)
     addr = op_addr_ri_pre(s, a);
 
     tmp = tcg_temp_new_i32();
-    gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data);
+    gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN_4 | s->be_data);
     store_reg(s, a->rt, tmp);
 
     tcg_gen_addi_i32(addr, addr, 4);
@@ -6634,7 +6634,7 @@ static bool op_strd_ri(DisasContext *s, arg_ldst_ri *a, int rt2)
     addr = op_addr_ri_pre(s, a);
 
     tmp = load_reg(s, a->rt);
-    gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data);
+    gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN_4 | s->be_data);
     tcg_temp_free_i32(tmp);
 
     tcg_gen_addi_i32(addr, addr, 4);
-- 
2.25.1



  reply	other threads:[~2020-11-25  4:08 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-25  4:06 [PATCH for-6.0 00/11] target/arm: enforce alignment Richard Henderson
2020-11-25  4:06 ` Richard Henderson [this message]
2020-11-25  8:11   ` [PATCH 01/11] target/arm: Enforce word alignment for LDRD/STRD Philippe Mathieu-Daudé
2020-11-25  4:06 ` [PATCH 02/11] target/arm: Enforce alignment for LDA/LDAH/STL/STLH Richard Henderson
2020-11-25  8:13   ` Philippe Mathieu-Daudé
2020-11-25  4:06 ` [PATCH 03/11] target/arm: Enforce alignment for LDM/STM Richard Henderson
2020-11-25  4:06 ` [PATCH 04/11] target/arm: Enforce alignment for RFE Richard Henderson
2020-11-25  4:06 ` [PATCH 05/11] target/arm: Enforce alignment for SRS Richard Henderson
2020-12-03 11:38   ` Peter Maydell
2020-11-25  4:06 ` [PATCH 06/11] target/arm: Enforce alignment for VLDM/VSTM Richard Henderson
2020-11-25  4:06 ` [PATCH 07/11] target/arm: Enforce alignment for VLDR/VSTR Richard Henderson
2020-11-25  4:06 ` [PATCH 08/11] target/arm: Enforce alignment for VLD1 (all lanes) Richard Henderson
2020-11-25  4:06 ` [PATCH 09/11] target/arm: Enforce alignment for VLDn/VSTn (multiple) Richard Henderson
2020-11-25  4:06 ` [PATCH 10/11] target/arm: Fix decode of align in VLDST_single Richard Henderson
2020-12-01 14:09   ` Peter Maydell
2020-11-25  4:06 ` [PATCH 11/11] target/arm: Enforce alignment for VLDn/VSTn (single) Richard Henderson
2020-12-01 14:27 ` [PATCH for-6.0 00/11] target/arm: enforce alignment Peter Maydell
2020-12-01 14:37   ` Richard Henderson
2020-12-01 15:55 ` Peter Maydell
2020-12-03 12:30   ` Philippe Mathieu-Daudé
2020-12-03 16:10     ` Pavel Dovgalyuk
2020-12-03 16:14       ` Peter Maydell
2020-12-04  6:17         ` Pavel Dovgalyuk
2020-12-04 16:36           ` Peter Maydell
2020-12-04 17:28           ` Richard Henderson

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