From: Igor Mammedov <imammedo@redhat.com>
To: "Michael S. Tsirkin" <mst@redhat.com>
Cc: xieyingtai@huawei.com, Jiahui Cen <cenjiahui@huawei.com>,
Eduardo Habkost <ehabkost@redhat.com>,
Richard Henderson <richard.henderson@linaro.org>,
qemu-devel@nongnu.org, Ard Biesheuvel <ard.biesheuvel@arm.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Laszlo Ersek <lersek@redhat.com>,
wu.wubin@huawei.com
Subject: Re: [PATCH v3 5/8] acpi/gpex: Append pxb devs in ascending order
Date: Tue, 5 Jan 2021 01:21:36 +0100 [thread overview]
Message-ID: <20210105012136.01c82f9b@redhat.com> (raw)
In-Reply-To: <20201230160814-mutt-send-email-mst@kernel.org>
On Wed, 30 Dec 2020 16:17:14 -0500
"Michael S. Tsirkin" <mst@redhat.com> wrote:
> On Tue, Dec 29, 2020 at 02:47:35PM +0100, Igor Mammedov wrote:
> > On Wed, 23 Dec 2020 17:08:33 +0800
> > Jiahui Cen <cenjiahui@huawei.com> wrote:
> >
> > > The overlap check of IO resource window would fail when Linux kernel
> > > registers an IO resource [b, c) earlier than another resource [a, b).
> > > Though this incorrect check could be fixed by [1], it would be better to
> > > append pxb devs into DSDT table in ascending order.
> > >
> > > [1]: https://lore.kernel.org/lkml/20201218062335.5320-1-cenjiahui@huawei.com/
> >
> > considering there is acceptable fix for kernel I'd rather avoid
> > workarounds on QEMU side. So I suggest dropping this patch.
>
> Well there's something to be said for a defined order of things.
> And patch is from Dec 2020 will take ages for guests to be fixed,
> and changing pci core on stable kernels is risky and needs
> a ton of testing, not done eaily ...
> Which guests are affected by the bug?
it's workaround for a trivial bug for niche configuration
for a new QEMU feature that never worked for arm/virt machine
Downstream that think that it is important enough to support
can backport and test patch thus helping stable trees to merge
it sooner.
> There are also some issues with the patch see below.
>
> > it also should reduce noise in [8/8] masking other changes.
> >
> > > Signed-off-by: Jiahui Cen <cenjiahui@huawei.com>
> > > ---
> > > hw/pci-host/gpex-acpi.c | 11 +++++++++--
> > > 1 file changed, 9 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c
> > > index 4bf1e94309..95a7a0f12b 100644
> > > --- a/hw/pci-host/gpex-acpi.c
> > > +++ b/hw/pci-host/gpex-acpi.c
> > > @@ -141,7 +141,7 @@ static void acpi_dsdt_add_pci_osc(Aml *dev)
> > > void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
> > > {
> > > int nr_pcie_buses = cfg->ecam.size / PCIE_MMCFG_SIZE_MIN;
> > > - Aml *method, *crs, *dev, *rbuf;
> > > + Aml *method, *crs, *dev, *rbuf, *pxb_devs[nr_pcie_buses];
>
> dynamically sized array on stack poses security issues
>
> > > PCIBus *bus = cfg->bus;
> > > CrsRangeSet crs_range_set;
> > > CrsRangeEntry *entry;
> > > @@ -149,6 +149,7 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
> > >
> > > /* start to construct the tables for pxb */
> > > crs_range_set_init(&crs_range_set);
> > > + memset(pxb_devs, 0, sizeof(pxb_devs));
> > > if (bus) {
> > > QLIST_FOREACH(bus, &bus->child, sibling) {
> > > uint8_t bus_num = pci_bus_num(bus);
> > > @@ -190,7 +191,7 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
> > >
> > > acpi_dsdt_add_pci_osc(dev);
> > >
> > > - aml_append(scope, dev);
> > > + pxb_devs[bus_num] = dev;
>
> If bus numbers intersect this will overwrite old one.
> I'd rather not worry about it, just have an array
> of structs with bus numbers and sort it.
>
>
> > > }
> > > }
> > >
> > > @@ -278,5 +279,11 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
> > > aml_append(dev, dev_res0);
> > > aml_append(scope, dev);
> > >
> > > + for (i = 0; i < ARRAY_SIZE(pxb_devs); i++) {
> > > + if (pxb_devs[i]) {
> > > + aml_append(scope, pxb_devs[i]);
> > > + }
> > > + }
>
>
> so this sorts them by bus number not by io address.
> Probably happens to help since bios numbers them in the same order ...
> Is there a way to address this more robustly in case
> bios changes? E.g. I see the bug is only in PIO so sort by that address maybe?
>
> Also pls add a code comment explaining why we are doing all this
> with link to patch, which guests are affected etc.
>
> > > +
> > > crs_range_set_free(&crs_range_set);
> > > }
>
>
next prev parent reply other threads:[~2021-01-05 0:22 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-23 9:08 [PATCH v3 0/8] acpi: Some fixes for pxb support for ARM virt machine Jiahui Cen
2020-12-23 9:08 ` [PATCH v3 1/8] acpi: Allow DSDT acpi table changes Jiahui Cen
2020-12-23 9:08 ` [PATCH v3 2/8] acpi: Add addr offset in build_crs Jiahui Cen
2020-12-29 13:36 ` Igor Mammedov
2020-12-31 3:26 ` Jiahui Cen
2020-12-23 9:08 ` [PATCH v3 3/8] acpi/gpex: Inform os to keep firmware resource map Jiahui Cen
2020-12-29 13:41 ` Igor Mammedov
2020-12-30 21:22 ` Michael S. Tsirkin
2020-12-31 8:22 ` Jiahui Cen
2021-01-05 0:35 ` Igor Mammedov
2021-01-05 1:53 ` Jiahui Cen
2021-01-06 13:29 ` Igor Mammedov
2021-01-07 5:54 ` Jiahui Cen
2021-01-05 19:33 ` Laszlo Ersek
2020-12-31 3:30 ` Jiahui Cen
2020-12-23 9:08 ` [PATCH v3 4/8] acpi/gpex: Exclude pxb's resources from PCI0 Jiahui Cen
2020-12-23 9:08 ` [PATCH v3 5/8] acpi/gpex: Append pxb devs in ascending order Jiahui Cen
2020-12-29 13:47 ` Igor Mammedov
2020-12-30 21:17 ` Michael S. Tsirkin
2020-12-31 7:34 ` Jiahui Cen
2021-01-05 0:21 ` Igor Mammedov [this message]
2020-12-23 9:08 ` [PATCH v3 6/8] Kconfig: Enable PXB for ARM_VIRT by default Jiahui Cen
2020-12-29 13:50 ` Igor Mammedov
2020-12-31 7:35 ` Jiahui Cen
2020-12-23 9:08 ` [PATCH v3 7/8] acpi: Enable pxb unit-test for ARM virt machine Jiahui Cen
2020-12-23 9:08 ` [PATCH v3 8/8] acpi: Update addr_trans and _DSM in expected files Jiahui Cen
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