From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4249AC433E0 for ; Sat, 9 Jan 2021 21:39:45 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 67B1520E65 for ; Sat, 9 Jan 2021 21:39:44 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 67B1520E65 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:43154 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kyLxU-0005TZ-79 for qemu-devel@archiver.kernel.org; Sat, 09 Jan 2021 16:39:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51246) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kyLwe-0004tf-Fr for qemu-devel@nongnu.org; Sat, 09 Jan 2021 16:38:48 -0500 Received: from us-smtp-delivery-124.mimecast.com ([216.205.24.124]:30783) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1kyLwb-0005EA-3c for qemu-devel@nongnu.org; Sat, 09 Jan 2021 16:38:47 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1610228323; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=IduuC/aSO1DeDw5UV09B+OS8hhXTZC/Z018BCJvL1Lw=; b=iRgdiCcUclFwu5PTN7MAiE1U41yzXnY9pHP9lOrakxXebF3SGy8Zcd9Q6vW/vB7EtgPEY4 VNSrPXS5CoGxPlmEGDPb2Avv7A2zpmQ7zxNgdxcLACV/AvTmjBR5t52kNaXzmlXLfgDNqY LPQewcyhnWWH2T/KXpw/IxK4j4uTWLo= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-351-OzKPWkAbP_-bxa02-vJRTA-1; Sat, 09 Jan 2021 16:38:38 -0500 X-MC-Unique: OzKPWkAbP_-bxa02-vJRTA-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 44C3C800D53; Sat, 9 Jan 2021 21:38:36 +0000 (UTC) Received: from kamzik.brq.redhat.com (ovpn-112-243.rdu2.redhat.com [10.10.112.243]) by smtp.corp.redhat.com (Postfix) with ESMTPS id A78CA5C728; Sat, 9 Jan 2021 21:38:33 +0000 (UTC) Date: Sat, 9 Jan 2021 16:38:31 -0500 From: Andrew Jones To: Yifei Jiang Subject: Re: [PATCH v2 1/1] target-riscv: support QMP dump-guest-memory Message-ID: <20210109213831.jznse3b3xjzrkf3h@kamzik.brq.redhat.com> References: <20201218022653.654-1-jiangyifei@huawei.com> <20201218022653.654-2-jiangyifei@huawei.com> MIME-Version: 1.0 In-Reply-To: <20201218022653.654-2-jiangyifei@huawei.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=drjones@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Received-SPF: pass client-ip=216.205.24.124; envelope-from=drjones@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.251, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, zhang.zhanghailiang@huawei.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, victor.zhangxiaofeng@huawei.com, qemu-devel@nongnu.org, limingwang@huawei.com, Alistair.Francis@wdc.com, palmer@dabbelt.com, fanliang@huawei.com, wu.wubin@huawei.com, dengkai1@huawei.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Fri, Dec 18, 2020 at 10:26:53AM +0800, Yifei Jiang wrote: > Add the support needed for creating prstatus elf notes. Now elf notes > only contains user_regs. This allows us to use QMP dump-guest-memory. > > Signed-off-by: Yifei Jiang > Signed-off-by: Mingwang Li > --- > target/riscv/arch_dump.c | 189 +++++++++++++++++++++++++++++++++++++++ > target/riscv/cpu.c | 2 + > target/riscv/cpu.h | 4 + > target/riscv/cpu_bits.h | 1 + > target/riscv/meson.build | 1 + > 5 files changed, 197 insertions(+) > create mode 100644 target/riscv/arch_dump.c > > diff --git a/target/riscv/arch_dump.c b/target/riscv/arch_dump.c > new file mode 100644 > index 0000000000..b89ddf18c7 > --- /dev/null > +++ b/target/riscv/arch_dump.c > @@ -0,0 +1,189 @@ > +/* Support for writing ELF notes for RISC-V architectures > + * > + * Copyright (C) 2020 Huawei Technologies Co., Ltd > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms and conditions of the GNU General Public License, > + * version 2 or later, as published by the Free Software Foundation. > + * > + * This program is distributed in the hope it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for > + * more details. > + * > + * You should have received a copy of the GNU General Public License along with > + * this program. If not, see . > + */ > + > +#include "qemu/osdep.h" > +#include "cpu.h" > +#include "elf.h" > +#include "sysemu/dump.h" > + > +/* struct user_regs_struct from arch/riscv/include/uapi/asm/ptrace.h */ > +struct riscv_user_regs { > + target_ulong pc; > + target_ulong regs[31]; > +} QEMU_PACKED; > + > +/* struct elf_prstatus from include/uapi/linux/elfcore.h */ > +struct riscv64_elf_prstatus { > + char pad1[32]; /* 32 == offsetof(struct elf_prstatus, pr_pid) */ > + uint32_t pr_pid; > + char pad2[76]; /* 76 == offsetof(struct elf_prstatus, pr_reg) - > + offsetof(struct elf_prstatus, pr_ppid) */ > + struct riscv_user_regs pr_reg; > + char pad3[8]; > +} QEMU_PACKED; Any reason not to use the defensive build-bugs that target/arm/arch_dump.c has? > + > +struct riscv64_note { > + Elf64_Nhdr hdr; > + char name[8]; /* align_up(sizeof("CORE"), 4) */ > + struct riscv64_elf_prstatus prstatus; > +} QEMU_PACKED; > + > +#define RISCV64_NOTE_HEADER_SIZE offsetof(struct riscv64_note, prstatus) > +#define RISCV64_PRSTATUS_NOTE_SIZE \ > + (RISCV64_NOTE_HEADER_SIZE + sizeof(struct riscv64_elf_prstatus)) > + > +static void riscv64_note_init(struct riscv64_note *note, DumpState *s, > + const char *name, Elf64_Word namesz, > + Elf64_Word type, Elf64_Word descsz) > +{ > + memset(note, 0, sizeof(*note)); > + > + note->hdr.n_namesz = cpu_to_dump32(s, namesz); > + note->hdr.n_descsz = cpu_to_dump32(s, descsz); > + note->hdr.n_type = cpu_to_dump32(s, type); > + > + memcpy(note->name, name, namesz); > +} > + > +int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, > + int cpuid, void *opaque) > +{ > + struct riscv64_note note; > + RISCVCPU *cpu = RISCV_CPU(cs); > + CPURISCVState *env = &cpu->env; > + DumpState *s = opaque; > + int ret, i = 0; > + const char name[] = "CORE"; > + > + riscv64_note_init(¬e, s, name, sizeof(name), > + NT_PRSTATUS, sizeof(note.prstatus)); > + > + note.prstatus.pr_pid = cpu_to_dump32(s, cpuid); > + > + note.prstatus.pr_reg.pc = cpu_to_dump64(s, env->pc); > + > + for (i = 0; i < 31; i++) { > + note.prstatus.pr_reg.regs[i] = cpu_to_dump64(s, env->gpr[i + 1]); > + } > + > + ret = f(¬e, RISCV64_PRSTATUS_NOTE_SIZE, s); > + if (ret < 0) { > + return -1; > + } > + > + return ret; > +} > + > +struct riscv32_elf_prstatus { > + char pad1[24]; /* 24 == offsetof(struct elf_prstatus, pr_pid) */ > + uint32_t pr_pid; > + char pad2[44]; /* 44 == offsetof(struct elf_prstatus, pr_reg) - > + offsetof(struct elf_prstatus, pr_ppid) */ > + struct riscv_user_regs pr_reg; > + char pad3[4]; > +} QEMU_PACKED; > + > +struct riscv32_note { > + Elf32_Nhdr hdr; > + char name[8]; /* align_up(sizeof("CORE"), 4) */ > + struct riscv32_elf_prstatus prstatus; > +} QEMU_PACKED; > + > +#define RISCV32_NOTE_HEADER_SIZE offsetof(struct riscv32_note, prstatus) > +#define RISCV32_PRSTATUS_NOTE_SIZE \ > + (RISCV32_NOTE_HEADER_SIZE + sizeof(struct riscv32_elf_prstatus)) > + > +static void riscv32_note_init(struct riscv32_note *note, DumpState *s, > + const char *name, Elf32_Word namesz, > + Elf32_Word type, Elf32_Word descsz) > +{ > + memset(note, 0, sizeof(*note)); > + > + note->hdr.n_namesz = cpu_to_dump32(s, namesz); > + note->hdr.n_descsz = cpu_to_dump32(s, descsz); > + note->hdr.n_type = cpu_to_dump32(s, type); > + > + memcpy(note->name, name, namesz); > +} > + > +int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, > + int cpuid, void *opaque) > +{ > + struct riscv32_note note; > + RISCVCPU *cpu = RISCV_CPU(cs); > + CPURISCVState *env = &cpu->env; > + DumpState *s = opaque; > + int ret, i; > + const char name[] = "CORE"; > + > + riscv32_note_init(¬e, s, name, sizeof(name), > + NT_PRSTATUS, sizeof(note.prstatus)); > + > + note.prstatus.pr_pid = cpu_to_dump32(s, cpuid); > + > + note.prstatus.pr_reg.pc = cpu_to_dump32(s, env->pc); > + > + for (i = 0; i < 31; i++) { > + note.prstatus.pr_reg.regs[i] = cpu_to_dump32(s, env->gpr[i + 1]); > + } > + > + ret = f(¬e, RISCV32_PRSTATUS_NOTE_SIZE, s); > + if (ret < 0) { > + return -1; > + } > + > + return ret; > +} > + > +int cpu_get_dump_info(ArchDumpInfo *info, > + const GuestPhysBlockList *guest_phys_blocks) > +{ > + RISCVCPU *cpu; > + CPURISCVState *env; > + > + if (first_cpu == NULL) { > + return -1; > + } > + cpu = RISCV_CPU(first_cpu); > + env = &cpu->env; > + > + info->d_machine = EM_RISCV; > + > +#if defined(TARGET_RISCV64) > + info->d_class = ELFCLASS64; > +#else > + info->d_class = ELFCLASS32; > +#endif > + > + info->d_endian = (env->mstatus & MSTATUS_UBE) != 0 > + ? ELFDATA2MSB : ELFDATA2LSB; > + > + return 0; > +} > + > +ssize_t cpu_get_note_size(int class, int machine, int nr_cpus) > +{ > + size_t note_size; > + > + if (class == ELFCLASS64) { > + note_size = RISCV64_PRSTATUS_NOTE_SIZE; > + } else { > + note_size = RISCV32_PRSTATUS_NOTE_SIZE; > + } > + > + return note_size * nr_cpus; > +} > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 6a0264fc6b..69999af813 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -560,6 +560,8 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) > cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug; > /* For now, mark unmigratable: */ > cc->vmsd = &vmstate_riscv_cpu; > + cc->write_elf64_note = riscv_cpu_write_elf64_note; > + cc->write_elf32_note = riscv_cpu_write_elf32_note; > #endif > #ifdef CONFIG_TCG > cc->tcg_initialize = riscv_translate_init; > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index c0a326c843..4a340b0c73 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -315,6 +315,10 @@ extern const char * const riscv_intr_names[]; > > const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); > void riscv_cpu_do_interrupt(CPUState *cpu); > +int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, > + int cpuid, void *opaque); > +int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, > + int cpuid, void *opaque); > int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); > int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); > bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index 24b24c69c5..d7259561e7 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -368,6 +368,7 @@ > #define MSTATUS_MIE 0x00000008 > #define MSTATUS_UPIE 0x00000010 > #define MSTATUS_SPIE 0x00000020 > +#define MSTATUS_UBE 0x00000040 > #define MSTATUS_MPIE 0x00000080 > #define MSTATUS_SPP 0x00000100 > #define MSTATUS_MPP 0x00001800 > diff --git a/target/riscv/meson.build b/target/riscv/meson.build > index 14a5c62dac..88ab850682 100644 > --- a/target/riscv/meson.build > +++ b/target/riscv/meson.build > @@ -26,6 +26,7 @@ riscv_ss.add(files( > > riscv_softmmu_ss = ss.source_set() > riscv_softmmu_ss.add(files( > + 'arch_dump.c', > 'pmp.c', > 'monitor.c', > 'machine.c' > -- > 2.19.1 > > Besides the missing build-bug question, Reviewed-by: Andrew Jones Thanks, drew