From: frank.chang@sifive.com
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>,
Frank Chang <frank.chang@sifive.com>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Richard Henderson <richard.henderson@linaro.org>,
Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Kito Cheng <kito.cheng@sifive.com>
Subject: [RFC v4 07/16] target/riscv: rvb: sign-extend instructions
Date: Wed, 13 Jan 2021 15:13:39 +0800 [thread overview]
Message-ID: <20210113071350.24852-8-frank.chang@sifive.com> (raw)
In-Reply-To: <20210113071350.24852-1-frank.chang@sifive.com>
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvb.c.inc | 12 ++++++++++++
2 files changed, 14 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index d64326fd864..938c23088eb 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -598,6 +598,8 @@ vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
clz 011000 000000 ..... 001 ..... 0010011 @r2
ctz 011000 000001 ..... 001 ..... 0010011 @r2
cpop 011000 000010 ..... 001 ..... 0010011 @r2
+sext_b 011000 000100 ..... 001 ..... 0010011 @r2
+sext_h 011000 000101 ..... 001 ..... 0010011 @r2
andn 0100000 .......... 111 ..... 0110011 @r
orn 0100000 .......... 110 ..... 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 2aa4515fe31..1496996a660 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -95,6 +95,18 @@ static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
return gen_arith(ctx, a, tcg_gen_umax_tl);
}
+static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, tcg_gen_ext8s_tl);
+}
+
+static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, tcg_gen_ext16s_tl);
+}
+
/* RV64-only instructions */
#ifdef TARGET_RISCV64
--
2.17.1
next prev parent reply other threads:[~2021-01-13 7:31 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-13 7:13 [RFC v4 00/16] support subsets of bitmanip extension frank.chang
2021-01-13 7:13 ` [RFC v4 01/16] target/riscv: reformat @sh format encoding for B-extension frank.chang
2021-01-25 23:47 ` Alistair Francis
2021-01-13 7:13 ` [RFC v4 02/16] target/riscv: rvb: count leading/trailing zeros frank.chang
2021-01-13 7:13 ` [RFC v4 03/16] target/riscv: rvb: count bits set frank.chang
2021-01-13 7:13 ` [RFC v4 04/16] target/riscv: rvb: logic-with-negate frank.chang
2021-01-13 7:13 ` [RFC v4 05/16] target/riscv: rvb: pack two words into one register frank.chang
2021-01-13 7:13 ` [RFC v4 06/16] target/riscv: rvb: min/max instructions frank.chang
2021-01-13 7:13 ` frank.chang [this message]
2021-01-13 7:13 ` [RFC v4 08/16] target/riscv: add gen_shifti() and gen_shiftiw() helper functions frank.chang
2021-01-21 19:32 ` Richard Henderson
2021-01-13 7:13 ` [RFC v4 09/16] target/riscv: rvb: single-bit instructions frank.chang
2021-01-13 7:13 ` [RFC v4 10/16] target/riscv: rvb: shift ones frank.chang
2021-01-13 7:13 ` [RFC v4 11/16] target/riscv: rvb: rotate (left/right) frank.chang
2021-01-13 7:13 ` [RFC v4 12/16] target/riscv: rvb: generalized reverse frank.chang
2021-01-13 7:13 ` [RFC v4 13/16] target/riscv: rvb: generalized or-combine frank.chang
2021-01-13 7:13 ` [RFC v4 14/16] target/riscv: rvb: address calculation frank.chang
2021-01-13 7:13 ` [RFC v4 15/16] target/riscv: rvb: add/shift with prefix zero-extend frank.chang
2021-01-13 7:13 ` [RFC v4 16/16] target/riscv: rvb: support and turn on B-extension from command line frank.chang
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