From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
"Alistair Francis" <alistair@alistair23.me>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Jean-Christophe Dubois" <jcd@tribudubois.net>,
qemu-arm@nongnu.org, "Peter Chubb" <peter.chubb@nicta.com.au>
Subject: [PATCH v7 0/9] hw/ssi: imx_spi: Fix various bugs in the imx_spi model
Date: Fri, 15 Jan 2021 16:30:40 +0100 [thread overview]
Message-ID: <20210115153049.3353008-1-f4bug@amsat.org> (raw)
Hi,
This is how I understand the ecSPI reset works, after
looking at the IMX6DQRM.pdf datasheet.
This is a respin of Ben's v5 series [*].
Since v6:
- Dropped "Reduce 'change_mask' variable scope" patch
- Fixed inverted reset logic
- Added Juan R-b tags
- Removed 'RFC' tag as tests pass
Based-on: <1608688825-81519-1-git-send-email-bmeng.cn@gmail.com>
(queued on riscv-next).
Copy of Ben's v5 cover:
This series fixes a bunch of bugs in current implementation of the imx
spi controller, including the following issues:
- chip select signal was not lower down when spi controller is disabled
- remove imx_spi_update_irq() in imx_spi_reset()
- round up the tx burst length to be multiple of 8
- transfer incorrect data when the burst length is larger than 32 bit
- spi controller tx and rx fifo endianness is incorrect
[*] https://lists.gnu.org/archive/html/qemu-devel/2021-01/msg02333.html
Diff with v6:
Key:
[----] : patches are identical
[####] : number of functional differences between upstream/downstream patch
[down] : patch is downstream-only
The flags [FC] indicate (F)unctional and (C)ontextual differences, respective=
ly
001/9:[----] [--] 'hw/ssi: imx_spi: Use a macro for number of chip selects su=
pported'
002/9:[----] [--] 'hw/ssi: imx_spi: Remove pointless variable initialization'
003/9:[----] [-C] 'hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG reg=
ister value'
004/9:[----] [-C] 'hw/ssi: imx_spi: Rework imx_spi_read() to handle block dis=
abled'
005/9:[0003] [FC] 'hw/ssi: imx_spi: Rework imx_spi_write() to handle block di=
sabled'
006/9:[----] [--] 'hw/ssi: imx_spi: Disable chip selects when controller is d=
isabled'
007/9:[----] [--] 'hw/ssi: imx_spi: Round up the burst length to be multiple =
of 8'
008/9:[----] [--] 'hw/ssi: imx_spi: Correct the burst length > 32 bit transfe=
r logic'
009/9:[----] [--] 'hw/ssi: imx_spi: Correct tx and rx fifo endianness'
Bin Meng (4):
hw/ssi: imx_spi: Use a macro for number of chip selects supported
hw/ssi: imx_spi: Round up the burst length to be multiple of 8
hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic
hw/ssi: imx_spi: Correct tx and rx fifo endianness
Philippe Mathieu-Daud=C3=A9 (4):
hw/ssi: imx_spi: Remove pointless variable initialization
hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value
hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled
hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled
Xuzhou Cheng (1):
hw/ssi: imx_spi: Disable chip selects when controller is disabled
include/hw/ssi/imx_spi.h | 5 +-
hw/ssi/imx_spi.c | 137 +++++++++++++++++++++++----------------
2 files changed, 86 insertions(+), 56 deletions(-)
--=20
2.26.2
next reply other threads:[~2021-01-15 15:33 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-15 15:30 Philippe Mathieu-Daudé [this message]
2021-01-15 15:30 ` [PATCH v7 1/9] hw/ssi: imx_spi: Use a macro for number of chip selects supported Philippe Mathieu-Daudé
2021-01-15 15:30 ` [PATCH v7 2/9] hw/ssi: imx_spi: Remove pointless variable initialization Philippe Mathieu-Daudé
2021-01-15 15:30 ` [PATCH v7 3/9] hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value Philippe Mathieu-Daudé
2021-01-15 15:30 ` [PATCH v7 4/9] hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled Philippe Mathieu-Daudé
2021-01-16 13:35 ` Bin Meng
2021-01-16 16:04 ` Philippe Mathieu-Daudé
2021-01-15 15:30 ` [PATCH v7 5/9] hw/ssi: imx_spi: Rework imx_spi_write() " Philippe Mathieu-Daudé
2021-01-16 13:57 ` Bin Meng
2021-01-16 15:21 ` Philippe Mathieu-Daudé
2021-01-16 15:59 ` Bin Meng
2021-01-16 16:12 ` Philippe Mathieu-Daudé
2021-01-16 16:16 ` Bin Meng
2021-01-15 15:30 ` [PATCH v7 6/9] hw/ssi: imx_spi: Disable chip selects when controller is disabled Philippe Mathieu-Daudé
2021-01-15 15:30 ` [PATCH v7 7/9] hw/ssi: imx_spi: Round up the burst length to be multiple of 8 Philippe Mathieu-Daudé
2021-01-15 15:30 ` [PATCH v7 8/9] hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic Philippe Mathieu-Daudé
2021-01-15 15:30 ` [PATCH v7 9/9] hw/ssi: imx_spi: Correct tx and rx fifo endianness Philippe Mathieu-Daudé
2021-01-16 14:03 ` [PATCH v7 0/9] hw/ssi: imx_spi: Fix various bugs in the imx_spi model Bin Meng
2021-01-16 15:07 ` Philippe Mathieu-Daudé
2021-01-16 15:12 ` Bin Meng
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