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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 20/33] target/arm: Implement SCR_EL2.EEL2
Date: Tue, 19 Jan 2021 15:10:51 +0000	[thread overview]
Message-ID: <20210119151104.16264-21-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210119151104.16264-1-peter.maydell@linaro.org>

From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>

This adds handling for the SCR_EL3.EEL2 bit.

Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Message-id: 20210112104511.36576-17-remi.denis.courmont@huawei.com
[PMM: Applied fixes for review issues noted by RTH:
 - check for FEATURE_AARCH64 before checking sel2 isar feature
 - correct the commit message subject line]
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h       |  8 ++++++--
 target/arm/cpu.c       |  2 +-
 target/arm/helper.c    | 19 ++++++++++++++++---
 target/arm/translate.c | 15 +++++++++++++--
 4 files changed, 36 insertions(+), 8 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index b115da59359..df0d6778330 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2164,7 +2164,10 @@ static inline bool arm_is_secure(CPUARMState *env)
 static inline bool arm_is_el2_enabled(CPUARMState *env)
 {
     if (arm_feature(env, ARM_FEATURE_EL2)) {
-        return !arm_is_secure_below_el3(env);
+        if (arm_is_secure_below_el3(env)) {
+            return (env->cp15.scr_el3 & SCR_EEL2) != 0;
+        }
+        return true;
     }
     return false;
 }
@@ -2211,7 +2214,8 @@ static inline bool arm_el_is_aa64(CPUARMState *env, int el)
         return aa64;
     }
 
-    if (arm_feature(env, ARM_FEATURE_EL3)) {
+    if (arm_feature(env, ARM_FEATURE_EL3) &&
+        ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) {
         aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW);
     }
 
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 4ae22b2086b..40142ac141e 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -480,7 +480,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
              * masked from Secure state. The HCR and SCR settings
              * don't affect the masking logic, only the interrupt routing.
              */
-            if (target_el == 3 || !secure) {
+            if (target_el == 3 || !secure || (env->cp15.scr_el3 & SCR_EEL2)) {
                 unmasked = true;
             }
         } else {
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 79164a03e07..f3ee6d98080 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -533,6 +533,9 @@ static CPAccessResult access_trap_aa32s_el1(CPUARMState *env,
         return CP_ACCESS_OK;
     }
     if (arm_is_secure_below_el3(env)) {
+        if (env->cp15.scr_el3 & SCR_EEL2) {
+            return CP_ACCESS_TRAP_EL2;
+        }
         return CP_ACCESS_TRAP_EL3;
     }
     /* This will be EL1 NS and EL2 NS, which just UNDEF */
@@ -2030,6 +2033,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
         if (cpu_isar_feature(aa64_pauth, cpu)) {
             valid_mask |= SCR_API | SCR_APK;
         }
+        if (cpu_isar_feature(aa64_sel2, cpu)) {
+            valid_mask |= SCR_EEL2;
+        }
         if (cpu_isar_feature(aa64_mte, cpu)) {
             valid_mask |= SCR_ATA;
         }
@@ -3388,13 +3394,16 @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
                                  bool isread)
 {
     if (ri->opc2 & 4) {
-        /* The ATS12NSO* operations must trap to EL3 if executed in
+        /* The ATS12NSO* operations must trap to EL3 or EL2 if executed in
          * Secure EL1 (which can only happen if EL3 is AArch64).
          * They are simply UNDEF if executed from NS EL1.
          * They function normally from EL2 or EL3.
          */
         if (arm_current_el(env) == 1) {
             if (arm_is_secure_below_el3(env)) {
+                if (env->cp15.scr_el3 & SCR_EEL2) {
+                    return CP_ACCESS_TRAP_UNCATEGORIZED_EL2;
+                }
                 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3;
             }
             return CP_ACCESS_TRAP_UNCATEGORIZED;
@@ -3657,7 +3666,8 @@ static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri,
 static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri,
                                      bool isread)
 {
-    if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & SCR_NS)) {
+    if (arm_current_el(env) == 3 &&
+        !(env->cp15.scr_el3 & (SCR_NS | SCR_EEL2))) {
         return CP_ACCESS_TRAP;
     }
     return CP_ACCESS_OK;
@@ -5756,12 +5766,15 @@ static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
                                    bool isread)
 {
     /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
-     * At Secure EL1 it traps to EL3.
+     * At Secure EL1 it traps to EL3 or EL2.
      */
     if (arm_current_el(env) == 3) {
         return CP_ACCESS_OK;
     }
     if (arm_is_secure_below_el3(env)) {
+        if (env->cp15.scr_el3 & SCR_EEL2) {
+            return CP_ACCESS_TRAP_EL2;
+        }
         return CP_ACCESS_TRAP_EL3;
     }
     /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 614a6853ca5..1653cca1aaa 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -2832,9 +2832,20 @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
         }
         if (s->current_el == 1) {
             /* If we're in Secure EL1 (which implies that EL3 is AArch64)
-             * then accesses to Mon registers trap to EL3
+             * then accesses to Mon registers trap to Secure EL2, if it exists,
+             * otherwise EL3.
              */
-            TCGv_i32 tcg_el = tcg_const_i32(3);
+            TCGv_i32 tcg_el;
+
+            if (arm_dc_feature(s, ARM_FEATURE_AARCH64) &&
+                dc_isar_feature(aa64_sel2, s)) {
+                /* Target EL is EL<3 minus SCR_EL3.EEL2> */
+                tcg_el = load_cpu_field(cp15.scr_el3);
+                tcg_gen_sextract_i32(tcg_el, tcg_el, ctz32(SCR_EEL2), 1);
+                tcg_gen_addi_i32(tcg_el, tcg_el, 3);
+            } else {
+                tcg_el = tcg_const_i32(3);
+            }
 
             gen_exception_el(s, EXCP_UDEF, syn_uncategorized(), tcg_el);
             tcg_temp_free_i32(tcg_el);
-- 
2.20.1



  parent reply	other threads:[~2021-01-19 15:41 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-19 15:10 [PULL 00/33] target-arm queue Peter Maydell
2021-01-19 15:10 ` [PULL 01/33] target/arm: Implement an IMPDEF pauth algorithm Peter Maydell
2021-01-19 15:10 ` [PULL 02/33] target/arm: Add cpu properties to control pauth Peter Maydell
2021-01-19 15:10 ` [PULL 03/33] target/arm: Use object_property_add_bool for "sve" property Peter Maydell
2021-01-19 15:10 ` [PULL 04/33] target/arm: remove redundant tests Peter Maydell
2021-01-19 15:10 ` [PULL 05/33] target/arm: add arm_is_el2_enabled() helper Peter Maydell
2021-01-19 15:10 ` [PULL 06/33] target/arm: use arm_is_el2_enabled() where applicable Peter Maydell
2021-01-19 15:10 ` [PULL 07/33] target/arm: use arm_hcr_el2_eff() " Peter Maydell
2021-01-19 15:10 ` [PULL 08/33] target/arm: factor MDCR_EL2 common handling Peter Maydell
2021-01-19 15:10 ` [PULL 09/33] target/arm: Define isar_feature function to test for presence of SEL2 Peter Maydell
2021-01-19 15:10 ` [PULL 10/33] target/arm: add 64-bit S-EL2 to EL exception table Peter Maydell
2021-01-19 15:10 ` [PULL 11/33] target/arm: add MMU stage 1 for Secure EL2 Peter Maydell
2021-01-19 15:10 ` [PULL 12/33] target/arm: add ARMv8.4-SEL2 system registers Peter Maydell
2021-01-19 15:10 ` [PULL 13/33] target/arm: handle VMID change in secure state Peter Maydell
2021-01-19 15:10 ` [PULL 14/33] target/arm: do S1_ptw_translate() before address space lookup Peter Maydell
2021-01-19 15:10 ` [PULL 15/33] target/arm: translate NS bit in page-walks Peter Maydell
2021-01-19 15:10 ` [PULL 16/33] target/arm: generalize 2-stage page-walk condition Peter Maydell
2021-01-19 15:10 ` [PULL 17/33] target/arm: secure stage 2 translation regime Peter Maydell
2021-01-19 15:10 ` [PULL 18/33] target/arm: set HPFAR_EL2.NS on secure stage 2 faults Peter Maydell
2021-01-19 15:10 ` [PULL 19/33] target/arm: revector to run-time pick target EL Peter Maydell
2021-01-19 15:10 ` Peter Maydell [this message]
2021-01-19 15:10 ` [PULL 21/33] target/arm: enable Secure EL2 in max CPU Peter Maydell
2021-01-19 15:10 ` [PULL 22/33] target/arm: refactor vae1_tlbmask() Peter Maydell
2021-01-19 15:10 ` [PULL 23/33] target/arm: Introduce PREDDESC field definitions Peter Maydell
2021-01-19 15:10 ` [PULL 24/33] target/arm: Update PFIRST, PNEXT for pred_desc Peter Maydell
2021-01-19 15:10 ` [PULL 25/33] target/arm: Update ZIP, UZP, TRN " Peter Maydell
2021-01-19 15:10 ` [PULL 26/33] target/arm: Update REV, PUNPK " Peter Maydell
2021-01-19 15:10 ` [PULL 27/33] hw/misc/pvpanic: split-out generic and bus dependent code Peter Maydell
2021-01-19 15:10 ` [PULL 28/33] hw/misc/pvpanic: add PCI interface support Peter Maydell
2021-01-19 15:11 ` [PULL 29/33] pvpanic : update pvpanic spec document Peter Maydell
2021-01-19 15:11 ` [PULL 30/33] tests/qtest: add a test case for pvpanic-pci Peter Maydell
2021-01-19 15:11 ` [PULL 31/33] npcm7xx_adc-test: Fix memleak in adc_qom_set Peter Maydell
2021-01-19 15:11 ` [PULL 32/33] target/arm/m_helper: Silence GCC 10 maybe-uninitialized error Peter Maydell
2021-01-19 15:11 ` [PULL 33/33] docs: Build and install all the docs in a single manual Peter Maydell
2021-01-19 16:00 ` [PULL 00/33] target-arm queue no-reply

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