* [PATCH 01/25] ptimer: Add new ptimer_set_period_from_clock() function
2021-01-21 19:05 [PATCH 00/25] Convert CMSDK timer, watchdog, dualtimer to Clock framework Peter Maydell
@ 2021-01-21 19:05 ` Peter Maydell
2021-01-22 14:08 ` Luc Michel
2021-01-21 19:05 ` [PATCH 02/25] clock: Add new clock_has_source() function Peter Maydell
` (23 subsequent siblings)
24 siblings, 1 reply; 80+ messages in thread
From: Peter Maydell @ 2021-01-21 19:05 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Philippe Mathieu-Daudé
The ptimer API currently provides two methods for setting the period:
ptimer_set_period(), which takes a period in nanoseconds, and
ptimer_set_freq(), which takes a frequency in Hz. Neither of these
lines up nicely with the Clock API, because although both the Clock
and the ptimer track the frequency using a representation of whole
and fractional nanoseconds, conversion via either period-in-ns or
frequency-in-Hz will introduce a rounding error.
Add a new function ptimer_set_period_from_clock() which takes the
Clock object directly to avoid the rounding issues. This includes a
facility for the user to specify that there is a frequency divider
between the Clock proper and the timer, as some timer devices like
the CMSDK APB dualtimer need this.
To avoid having to drag in clock.h from ptimer.h we add the Clock
type to typedefs.h.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
Side note, I forget why we didn't go for 64.32 fixedpoint for the
Clock too. I kinda feel we might run into the "clocks can't handle
periods greater than 4 seconds" limit some day. Hopefully we can
backwards-compatibly expand it if that day ever comes...
The 'divisor' functionality seemed like the simplest way to get
to what I needed for the dualtimer; perhaps we should think about
whether we can have generic lightweight support for clock
frequency divider/multipliers...
---
include/hw/ptimer.h | 22 ++++++++++++++++++++++
include/qemu/typedefs.h | 1 +
hw/core/ptimer.c | 34 ++++++++++++++++++++++++++++++++++
3 files changed, 57 insertions(+)
diff --git a/include/hw/ptimer.h b/include/hw/ptimer.h
index 412763fffb2..c443218475b 100644
--- a/include/hw/ptimer.h
+++ b/include/hw/ptimer.h
@@ -165,6 +165,28 @@ void ptimer_transaction_commit(ptimer_state *s);
*/
void ptimer_set_period(ptimer_state *s, int64_t period);
+/**
+ * ptimer_set_period_from_clock - Set counter increment from a Clock
+ * @s: ptimer to configure
+ * @clk: pointer to Clock object to take period from
+ * @divisor: value to scale the clock frequency down by
+ *
+ * If the ptimer is being driven from a Clock, this is the preferred
+ * way to tell the ptimer about the period, because it avoids any
+ * possible rounding errors that might happen if the internal
+ * representation of the Clock period was converted to either a period
+ * in ns or a frequency in Hz.
+ *
+ * If the ptimer should run at the same frequency as the clock,
+ * pass 1 as the @divisor; if the ptimer should run at half the
+ * frequency, pass 2, and so on.
+ *
+ * This function will assert if it is called outside a
+ * ptimer_transaction_begin/commit block.
+ */
+void ptimer_set_period_from_clock(ptimer_state *s, const Clock *clock,
+ unsigned int divisor);
+
/**
* ptimer_set_freq - Set counter frequency in Hz
* @s: ptimer to configure
diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
index 976b529dfb5..68deb74ef6f 100644
--- a/include/qemu/typedefs.h
+++ b/include/qemu/typedefs.h
@@ -34,6 +34,7 @@ typedef struct BlockDriverState BlockDriverState;
typedef struct BusClass BusClass;
typedef struct BusState BusState;
typedef struct Chardev Chardev;
+typedef struct Clock Clock;
typedef struct CompatProperty CompatProperty;
typedef struct CoMutex CoMutex;
typedef struct CPUAddressSpace CPUAddressSpace;
diff --git a/hw/core/ptimer.c b/hw/core/ptimer.c
index 2aa97cb665c..6ba19fd9658 100644
--- a/hw/core/ptimer.c
+++ b/hw/core/ptimer.c
@@ -15,6 +15,7 @@
#include "sysemu/qtest.h"
#include "block/aio.h"
#include "sysemu/cpus.h"
+#include "hw/clock.h"
#define DELTA_ADJUST 1
#define DELTA_NO_ADJUST -1
@@ -348,6 +349,39 @@ void ptimer_set_period(ptimer_state *s, int64_t period)
}
}
+/* Set counter increment interval from a Clock */
+void ptimer_set_period_from_clock(ptimer_state *s, const Clock *clk,
+ unsigned int divisor)
+{
+ /*
+ * The raw clock period is a 64-bit value in units of 2^-32 ns;
+ * put another way it's a 32.32 fixed-point ns value. Our internal
+ * representation of the period is 64.32 fixed point ns, so
+ * the conversion is simple.
+ */
+ uint64_t raw_period = clock_get(clk);
+ uint64_t period_frac;
+
+ assert(s->in_transaction);
+ s->delta = ptimer_get_count(s);
+ s->period = extract64(raw_period, 32, 32);
+ period_frac = extract64(raw_period, 0, 32);
+ /*
+ * divisor specifies a possible frequency divisor between the
+ * clock and the timer, so it is a multiplier on the period.
+ * We do the multiply after splitting the raw period out into
+ * period and frac to avoid having to do a 32*64->96 multiply.
+ */
+ s->period *= divisor;
+ period_frac *= divisor;
+ s->period += extract64(period_frac, 32, 32);
+ s->period_frac = (uint32_t)period_frac;
+
+ if (s->enabled) {
+ s->need_reload = true;
+ }
+}
+
/* Set counter frequency in Hz. */
void ptimer_set_freq(ptimer_state *s, uint32_t freq)
{
--
2.20.1
^ permalink raw reply related [flat|nested] 80+ messages in thread* Re: [PATCH 01/25] ptimer: Add new ptimer_set_period_from_clock() function
2021-01-21 19:05 ` [PATCH 01/25] ptimer: Add new ptimer_set_period_from_clock() function Peter Maydell
@ 2021-01-22 14:08 ` Luc Michel
0 siblings, 0 replies; 80+ messages in thread
From: Luc Michel @ 2021-01-22 14:08 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, qemu-arm, qemu-devel, Philippe Mathieu-Daudé
On 19:05 Thu 21 Jan , Peter Maydell wrote:
> The ptimer API currently provides two methods for setting the period:
> ptimer_set_period(), which takes a period in nanoseconds, and
> ptimer_set_freq(), which takes a frequency in Hz. Neither of these
> lines up nicely with the Clock API, because although both the Clock
> and the ptimer track the frequency using a representation of whole
> and fractional nanoseconds, conversion via either period-in-ns or
> frequency-in-Hz will introduce a rounding error.
>
> Add a new function ptimer_set_period_from_clock() which takes the
> Clock object directly to avoid the rounding issues. This includes a
> facility for the user to specify that there is a frequency divider
> between the Clock proper and the timer, as some timer devices like
> the CMSDK APB dualtimer need this.
>
> To avoid having to drag in clock.h from ptimer.h we add the Clock
> type to typedefs.h.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
> ---
> Side note, I forget why we didn't go for 64.32 fixedpoint for the
> Clock too. I kinda feel we might run into the "clocks can't handle
> periods greater than 4 seconds" limit some day. Hopefully we can
> backwards-compatibly expand it if that day ever comes...
>
> The 'divisor' functionality seemed like the simplest way to get
> to what I needed for the dualtimer; perhaps we should think about
> whether we can have generic lightweight support for clock
> frequency divider/multipliers...
> ---
> include/hw/ptimer.h | 22 ++++++++++++++++++++++
> include/qemu/typedefs.h | 1 +
> hw/core/ptimer.c | 34 ++++++++++++++++++++++++++++++++++
> 3 files changed, 57 insertions(+)
>
> diff --git a/include/hw/ptimer.h b/include/hw/ptimer.h
> index 412763fffb2..c443218475b 100644
> --- a/include/hw/ptimer.h
> +++ b/include/hw/ptimer.h
> @@ -165,6 +165,28 @@ void ptimer_transaction_commit(ptimer_state *s);
> */
> void ptimer_set_period(ptimer_state *s, int64_t period);
>
> +/**
> + * ptimer_set_period_from_clock - Set counter increment from a Clock
> + * @s: ptimer to configure
> + * @clk: pointer to Clock object to take period from
> + * @divisor: value to scale the clock frequency down by
> + *
> + * If the ptimer is being driven from a Clock, this is the preferred
> + * way to tell the ptimer about the period, because it avoids any
> + * possible rounding errors that might happen if the internal
> + * representation of the Clock period was converted to either a period
> + * in ns or a frequency in Hz.
> + *
> + * If the ptimer should run at the same frequency as the clock,
> + * pass 1 as the @divisor; if the ptimer should run at half the
> + * frequency, pass 2, and so on.
> + *
> + * This function will assert if it is called outside a
> + * ptimer_transaction_begin/commit block.
> + */
> +void ptimer_set_period_from_clock(ptimer_state *s, const Clock *clock,
> + unsigned int divisor);
> +
> /**
> * ptimer_set_freq - Set counter frequency in Hz
> * @s: ptimer to configure
> diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
> index 976b529dfb5..68deb74ef6f 100644
> --- a/include/qemu/typedefs.h
> +++ b/include/qemu/typedefs.h
> @@ -34,6 +34,7 @@ typedef struct BlockDriverState BlockDriverState;
> typedef struct BusClass BusClass;
> typedef struct BusState BusState;
> typedef struct Chardev Chardev;
> +typedef struct Clock Clock;
> typedef struct CompatProperty CompatProperty;
> typedef struct CoMutex CoMutex;
> typedef struct CPUAddressSpace CPUAddressSpace;
> diff --git a/hw/core/ptimer.c b/hw/core/ptimer.c
> index 2aa97cb665c..6ba19fd9658 100644
> --- a/hw/core/ptimer.c
> +++ b/hw/core/ptimer.c
> @@ -15,6 +15,7 @@
> #include "sysemu/qtest.h"
> #include "block/aio.h"
> #include "sysemu/cpus.h"
> +#include "hw/clock.h"
>
> #define DELTA_ADJUST 1
> #define DELTA_NO_ADJUST -1
> @@ -348,6 +349,39 @@ void ptimer_set_period(ptimer_state *s, int64_t period)
> }
> }
>
> +/* Set counter increment interval from a Clock */
> +void ptimer_set_period_from_clock(ptimer_state *s, const Clock *clk,
> + unsigned int divisor)
> +{
> + /*
> + * The raw clock period is a 64-bit value in units of 2^-32 ns;
> + * put another way it's a 32.32 fixed-point ns value. Our internal
> + * representation of the period is 64.32 fixed point ns, so
> + * the conversion is simple.
> + */
> + uint64_t raw_period = clock_get(clk);
> + uint64_t period_frac;
> +
> + assert(s->in_transaction);
> + s->delta = ptimer_get_count(s);
> + s->period = extract64(raw_period, 32, 32);
> + period_frac = extract64(raw_period, 0, 32);
> + /*
> + * divisor specifies a possible frequency divisor between the
> + * clock and the timer, so it is a multiplier on the period.
> + * We do the multiply after splitting the raw period out into
> + * period and frac to avoid having to do a 32*64->96 multiply.
> + */
> + s->period *= divisor;
> + period_frac *= divisor;
> + s->period += extract64(period_frac, 32, 32);
> + s->period_frac = (uint32_t)period_frac;
> +
> + if (s->enabled) {
> + s->need_reload = true;
> + }
> +}
> +
> /* Set counter frequency in Hz. */
> void ptimer_set_freq(ptimer_state *s, uint32_t freq)
> {
> --
> 2.20.1
>
--
^ permalink raw reply [flat|nested] 80+ messages in thread
* [PATCH 02/25] clock: Add new clock_has_source() function
2021-01-21 19:05 [PATCH 00/25] Convert CMSDK timer, watchdog, dualtimer to Clock framework Peter Maydell
2021-01-21 19:05 ` [PATCH 01/25] ptimer: Add new ptimer_set_period_from_clock() function Peter Maydell
@ 2021-01-21 19:05 ` Peter Maydell
2021-01-22 14:15 ` Luc Michel
2021-01-27 21:56 ` Philippe Mathieu-Daudé
2021-01-21 19:06 ` [PATCH 03/25] tests: Add a simple test of the CMSDK APB timer Peter Maydell
` (22 subsequent siblings)
24 siblings, 2 replies; 80+ messages in thread
From: Peter Maydell @ 2021-01-21 19:05 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Philippe Mathieu-Daudé
Add a function for checking whether a clock has a source. This is
useful for devices which have input clocks that must be wired up by
the board as it allows them to fail in realize rather than ploughing
on with a zero-period clock.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
docs/devel/clocks.rst | 16 ++++++++++++++++
include/hw/clock.h | 15 +++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/docs/devel/clocks.rst b/docs/devel/clocks.rst
index 2548d842322..c54bbb82409 100644
--- a/docs/devel/clocks.rst
+++ b/docs/devel/clocks.rst
@@ -235,6 +235,22 @@ object during device instance init. For example:
/* set initial value to 10ns / 100MHz */
clock_set_ns(clk, 10);
+To enforce that the clock is wired up by the board code, you can
+call ``clock_has_source()`` in your device's realize method:
+
+.. code-block:: c
+
+ if (!clock_has_source(s->clk)) {
+ error_setg(errp, "MyDevice: clk input must be connected");
+ return;
+ }
+
+Note that this only checks that the clock has been wired up; it is
+still possible that the output clock connected to it is disabled
+or has not yet been configured, in which case the period will be
+zero. You should use the clock callback to find out when the clock
+period changes.
+
Fetching clock frequency/period
-------------------------------
diff --git a/include/hw/clock.h b/include/hw/clock.h
index 6382f346569..e5f45e2626d 100644
--- a/include/hw/clock.h
+++ b/include/hw/clock.h
@@ -139,6 +139,21 @@ void clock_clear_callback(Clock *clk);
*/
void clock_set_source(Clock *clk, Clock *src);
+/**
+ * clock_has_source:
+ * @clk: the clock
+ *
+ * Returns true if the clock has a source clock connected to it.
+ * This is useful for devices which have input clocks which must
+ * be connected by the board/SoC code which creates them. The
+ * device code can use this to check in its realize method that
+ * the clock has been connected.
+ */
+static inline bool clock_has_source(const Clock *clk)
+{
+ return clk->source != NULL;
+}
+
/**
* clock_set:
* @clk: the clock to initialize.
--
2.20.1
^ permalink raw reply related [flat|nested] 80+ messages in thread* Re: [PATCH 02/25] clock: Add new clock_has_source() function
2021-01-21 19:05 ` [PATCH 02/25] clock: Add new clock_has_source() function Peter Maydell
@ 2021-01-22 14:15 ` Luc Michel
2021-01-27 21:56 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 80+ messages in thread
From: Luc Michel @ 2021-01-22 14:15 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, qemu-arm, qemu-devel, Philippe Mathieu-Daudé
On 19:05 Thu 21 Jan , Peter Maydell wrote:
> Add a function for checking whether a clock has a source. This is
> useful for devices which have input clocks that must be wired up by
> the board as it allows them to fail in realize rather than ploughing
> on with a zero-period clock.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
> ---
> docs/devel/clocks.rst | 16 ++++++++++++++++
> include/hw/clock.h | 15 +++++++++++++++
> 2 files changed, 31 insertions(+)
>
> diff --git a/docs/devel/clocks.rst b/docs/devel/clocks.rst
> index 2548d842322..c54bbb82409 100644
> --- a/docs/devel/clocks.rst
> +++ b/docs/devel/clocks.rst
> @@ -235,6 +235,22 @@ object during device instance init. For example:
> /* set initial value to 10ns / 100MHz */
> clock_set_ns(clk, 10);
>
> +To enforce that the clock is wired up by the board code, you can
> +call ``clock_has_source()`` in your device's realize method:
> +
> +.. code-block:: c
> +
> + if (!clock_has_source(s->clk)) {
> + error_setg(errp, "MyDevice: clk input must be connected");
> + return;
> + }
> +
> +Note that this only checks that the clock has been wired up; it is
> +still possible that the output clock connected to it is disabled
> +or has not yet been configured, in which case the period will be
> +zero. You should use the clock callback to find out when the clock
> +period changes.
> +
> Fetching clock frequency/period
> -------------------------------
>
> diff --git a/include/hw/clock.h b/include/hw/clock.h
> index 6382f346569..e5f45e2626d 100644
> --- a/include/hw/clock.h
> +++ b/include/hw/clock.h
> @@ -139,6 +139,21 @@ void clock_clear_callback(Clock *clk);
> */
> void clock_set_source(Clock *clk, Clock *src);
>
> +/**
> + * clock_has_source:
> + * @clk: the clock
> + *
> + * Returns true if the clock has a source clock connected to it.
> + * This is useful for devices which have input clocks which must
> + * be connected by the board/SoC code which creates them. The
> + * device code can use this to check in its realize method that
> + * the clock has been connected.
> + */
> +static inline bool clock_has_source(const Clock *clk)
> +{
> + return clk->source != NULL;
> +}
> +
> /**
> * clock_set:
> * @clk: the clock to initialize.
> --
> 2.20.1
>
--
^ permalink raw reply [flat|nested] 80+ messages in thread* Re: [PATCH 02/25] clock: Add new clock_has_source() function
2021-01-21 19:05 ` [PATCH 02/25] clock: Add new clock_has_source() function Peter Maydell
2021-01-22 14:15 ` Luc Michel
@ 2021-01-27 21:56 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 80+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-27 21:56 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel; +Cc: Damien Hedde, Luc Michel
On 1/21/21 8:05 PM, Peter Maydell wrote:
> Add a function for checking whether a clock has a source. This is
> useful for devices which have input clocks that must be wired up by
> the board as it allows them to fail in realize rather than ploughing
> on with a zero-period clock.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> docs/devel/clocks.rst | 16 ++++++++++++++++
> include/hw/clock.h | 15 +++++++++++++++
> 2 files changed, 31 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 80+ messages in thread
* [PATCH 03/25] tests: Add a simple test of the CMSDK APB timer
2021-01-21 19:05 [PATCH 00/25] Convert CMSDK timer, watchdog, dualtimer to Clock framework Peter Maydell
2021-01-21 19:05 ` [PATCH 01/25] ptimer: Add new ptimer_set_period_from_clock() function Peter Maydell
2021-01-21 19:05 ` [PATCH 02/25] clock: Add new clock_has_source() function Peter Maydell
@ 2021-01-21 19:06 ` Peter Maydell
2021-01-21 19:56 ` Philippe Mathieu-Daudé
2021-01-24 12:50 ` Luc Michel
2021-01-21 19:06 ` [PATCH 04/25] tests: Add a simple test of the CMSDK APB watchdog Peter Maydell
` (21 subsequent siblings)
24 siblings, 2 replies; 80+ messages in thread
From: Peter Maydell @ 2021-01-21 19:06 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Philippe Mathieu-Daudé
Add a simple test of the CMSDK APB timer, since we're about to do
some refactoring of how it is clocked.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
tests/qtest/cmsdk-apb-timer-test.c | 76 ++++++++++++++++++++++++++++++
MAINTAINERS | 1 +
tests/qtest/meson.build | 1 +
3 files changed, 78 insertions(+)
create mode 100644 tests/qtest/cmsdk-apb-timer-test.c
diff --git a/tests/qtest/cmsdk-apb-timer-test.c b/tests/qtest/cmsdk-apb-timer-test.c
new file mode 100644
index 00000000000..085005cce99
--- /dev/null
+++ b/tests/qtest/cmsdk-apb-timer-test.c
@@ -0,0 +1,76 @@
+/*
+ * QTest testcase for the CMSDK APB timer device
+ *
+ * Copyright (c) 2021 Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+#include "libqtest-single.h"
+
+/* IoTKit/ARMSSE-200 timer0; driven at 25MHz in mps2-an385, so 40ns per tick */
+#define TIMER_BASE 0x40000000
+
+#define CTRL 0
+#define VALUE 4
+#define RELOAD 8
+#define INTSTATUS 0xc
+
+static void test_timer(void)
+{
+ g_assert_true(readl(TIMER_BASE + INTSTATUS) == 0);
+
+ /* Start timer: will fire after 40000 ns */
+ writel(TIMER_BASE + RELOAD, 1000);
+ writel(TIMER_BASE + CTRL, 9);
+
+ /* Step to just past the 500th tick and check VALUE */
+ clock_step(20001);
+ g_assert_cmpuint(readl(TIMER_BASE + INTSTATUS), ==, 0);
+ g_assert_cmpuint(readl(TIMER_BASE + VALUE), ==, 500);
+
+ /* Just past the 1000th tick: timer should have fired */
+ clock_step(20000);
+ g_assert_cmpuint(readl(TIMER_BASE + INTSTATUS), ==, 1);
+ g_assert_cmpuint(readl(TIMER_BASE + VALUE), ==, 0);
+
+ /* VALUE reloads at the following tick */
+ clock_step(40);
+ g_assert_cmpuint(readl(TIMER_BASE + VALUE), ==, 1000);
+
+ /* Check write-1-to-clear behaviour of INTSTATUS */
+ writel(TIMER_BASE + INTSTATUS, 0);
+ g_assert_cmpuint(readl(TIMER_BASE + INTSTATUS), ==, 1);
+ writel(TIMER_BASE + INTSTATUS, 1);
+ g_assert_cmpuint(readl(TIMER_BASE + INTSTATUS), ==, 0);
+
+ /* Turn off the timer */
+ writel(TIMER_BASE + CTRL, 0);
+}
+
+int main(int argc, char **argv)
+{
+ QTestState *s;
+ int r;
+
+ g_test_init(&argc, &argv, NULL);
+
+ s = qtest_start("-machine mps2-an385");
+
+ qtest_add_func("/cmsdk-apb-timer/timer", test_timer);
+
+ r = g_test_run();
+
+ qtest_end();
+
+ return r;
+}
diff --git a/MAINTAINERS b/MAINTAINERS
index 3216387521d..010405b0884 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -581,6 +581,7 @@ F: include/hw/rtc/pl031.h
F: include/hw/arm/primecell.h
F: hw/timer/cmsdk-apb-timer.c
F: include/hw/timer/cmsdk-apb-timer.h
+F: tests/qtest/cmsdk-apb-timer-test.c
F: hw/timer/cmsdk-apb-dualtimer.c
F: include/hw/timer/cmsdk-apb-dualtimer.h
F: hw/char/cmsdk-apb-uart.c
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index 16d04625b8b..74addd74868 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -141,6 +141,7 @@ qtests_npcm7xx = \
'npcm7xx_timer-test',
'npcm7xx_watchdog_timer-test']
qtests_arm = \
+ (config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-timer-test'] : []) + \
(config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] : []) + \
(config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \
['arm-cpu-features',
--
2.20.1
^ permalink raw reply related [flat|nested] 80+ messages in thread* Re: [PATCH 03/25] tests: Add a simple test of the CMSDK APB timer
2021-01-21 19:06 ` [PATCH 03/25] tests: Add a simple test of the CMSDK APB timer Peter Maydell
@ 2021-01-21 19:56 ` Philippe Mathieu-Daudé
2021-01-24 12:50 ` Luc Michel
1 sibling, 0 replies; 80+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-21 19:56 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel; +Cc: Damien Hedde, Luc Michel
On 1/21/21 8:06 PM, Peter Maydell wrote:
> Add a simple test of the CMSDK APB timer, since we're about to do
> some refactoring of how it is clocked.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> tests/qtest/cmsdk-apb-timer-test.c | 76 ++++++++++++++++++++++++++++++
> MAINTAINERS | 1 +
> tests/qtest/meson.build | 1 +
> 3 files changed, 78 insertions(+)
> create mode 100644 tests/qtest/cmsdk-apb-timer-test.c
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 03/25] tests: Add a simple test of the CMSDK APB timer
2021-01-21 19:06 ` [PATCH 03/25] tests: Add a simple test of the CMSDK APB timer Peter Maydell
2021-01-21 19:56 ` Philippe Mathieu-Daudé
@ 2021-01-24 12:50 ` Luc Michel
1 sibling, 0 replies; 80+ messages in thread
From: Luc Michel @ 2021-01-24 12:50 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, qemu-arm, qemu-devel, Philippe Mathieu-Daudé
On 19:06 Thu 21 Jan , Peter Maydell wrote:
> Add a simple test of the CMSDK APB timer, since we're about to do
> some refactoring of how it is clocked.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
> ---
> tests/qtest/cmsdk-apb-timer-test.c | 76 ++++++++++++++++++++++++++++++
> MAINTAINERS | 1 +
> tests/qtest/meson.build | 1 +
> 3 files changed, 78 insertions(+)
> create mode 100644 tests/qtest/cmsdk-apb-timer-test.c
>
> diff --git a/tests/qtest/cmsdk-apb-timer-test.c b/tests/qtest/cmsdk-apb-timer-test.c
> new file mode 100644
> index 00000000000..085005cce99
> --- /dev/null
> +++ b/tests/qtest/cmsdk-apb-timer-test.c
> @@ -0,0 +1,76 @@
> +/*
> + * QTest testcase for the CMSDK APB timer device
> + *
> + * Copyright (c) 2021 Linaro Limited
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
> + * for more details.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "libqtest-single.h"
> +
> +/* IoTKit/ARMSSE-200 timer0; driven at 25MHz in mps2-an385, so 40ns per tick */
> +#define TIMER_BASE 0x40000000
> +
> +#define CTRL 0
> +#define VALUE 4
> +#define RELOAD 8
> +#define INTSTATUS 0xc
> +
> +static void test_timer(void)
> +{
> + g_assert_true(readl(TIMER_BASE + INTSTATUS) == 0);
> +
> + /* Start timer: will fire after 40000 ns */
> + writel(TIMER_BASE + RELOAD, 1000);
> + writel(TIMER_BASE + CTRL, 9);
> +
> + /* Step to just past the 500th tick and check VALUE */
> + clock_step(20001);
> + g_assert_cmpuint(readl(TIMER_BASE + INTSTATUS), ==, 0);
> + g_assert_cmpuint(readl(TIMER_BASE + VALUE), ==, 500);
> +
> + /* Just past the 1000th tick: timer should have fired */
> + clock_step(20000);
> + g_assert_cmpuint(readl(TIMER_BASE + INTSTATUS), ==, 1);
> + g_assert_cmpuint(readl(TIMER_BASE + VALUE), ==, 0);
> +
> + /* VALUE reloads at the following tick */
> + clock_step(40);
> + g_assert_cmpuint(readl(TIMER_BASE + VALUE), ==, 1000);
> +
> + /* Check write-1-to-clear behaviour of INTSTATUS */
> + writel(TIMER_BASE + INTSTATUS, 0);
> + g_assert_cmpuint(readl(TIMER_BASE + INTSTATUS), ==, 1);
> + writel(TIMER_BASE + INTSTATUS, 1);
> + g_assert_cmpuint(readl(TIMER_BASE + INTSTATUS), ==, 0);
> +
> + /* Turn off the timer */
> + writel(TIMER_BASE + CTRL, 0);
> +}
> +
> +int main(int argc, char **argv)
> +{
> + QTestState *s;
> + int r;
> +
> + g_test_init(&argc, &argv, NULL);
> +
> + s = qtest_start("-machine mps2-an385");
> +
> + qtest_add_func("/cmsdk-apb-timer/timer", test_timer);
> +
> + r = g_test_run();
> +
> + qtest_end();
> +
> + return r;
> +}
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 3216387521d..010405b0884 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -581,6 +581,7 @@ F: include/hw/rtc/pl031.h
> F: include/hw/arm/primecell.h
> F: hw/timer/cmsdk-apb-timer.c
> F: include/hw/timer/cmsdk-apb-timer.h
> +F: tests/qtest/cmsdk-apb-timer-test.c
> F: hw/timer/cmsdk-apb-dualtimer.c
> F: include/hw/timer/cmsdk-apb-dualtimer.h
> F: hw/char/cmsdk-apb-uart.c
> diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
> index 16d04625b8b..74addd74868 100644
> --- a/tests/qtest/meson.build
> +++ b/tests/qtest/meson.build
> @@ -141,6 +141,7 @@ qtests_npcm7xx = \
> 'npcm7xx_timer-test',
> 'npcm7xx_watchdog_timer-test']
> qtests_arm = \
> + (config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-timer-test'] : []) + \
> (config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] : []) + \
> (config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \
> ['arm-cpu-features',
> --
> 2.20.1
>
--
^ permalink raw reply [flat|nested] 80+ messages in thread
* [PATCH 04/25] tests: Add a simple test of the CMSDK APB watchdog
2021-01-21 19:05 [PATCH 00/25] Convert CMSDK timer, watchdog, dualtimer to Clock framework Peter Maydell
` (2 preceding siblings ...)
2021-01-21 19:06 ` [PATCH 03/25] tests: Add a simple test of the CMSDK APB timer Peter Maydell
@ 2021-01-21 19:06 ` Peter Maydell
2021-01-24 13:10 ` Luc Michel
2021-01-27 21:54 ` Philippe Mathieu-Daudé
2021-01-21 19:06 ` [PATCH 05/25] tests: Add a simple test of the CMSDK APB dual timer Peter Maydell
` (20 subsequent siblings)
24 siblings, 2 replies; 80+ messages in thread
From: Peter Maydell @ 2021-01-21 19:06 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Philippe Mathieu-Daudé
Add a simple test of the CMSDK watchdog, since we're about to do some
refactoring of how it is clocked.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
tests/qtest/cmsdk-apb-watchdog-test.c | 80 +++++++++++++++++++++++++++
MAINTAINERS | 1 +
tests/qtest/meson.build | 1 +
3 files changed, 82 insertions(+)
create mode 100644 tests/qtest/cmsdk-apb-watchdog-test.c
diff --git a/tests/qtest/cmsdk-apb-watchdog-test.c b/tests/qtest/cmsdk-apb-watchdog-test.c
new file mode 100644
index 00000000000..c6add1fee85
--- /dev/null
+++ b/tests/qtest/cmsdk-apb-watchdog-test.c
@@ -0,0 +1,80 @@
+/*
+ * QTest testcase for the CMSDK APB watchdog device
+ *
+ * Copyright (c) 2021 Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+#include "libqtest-single.h"
+
+/*
+ * lm3s811evb watchdog; at board startup this runs at 200MHz / 16 == 12.5MHz,
+ * which is 80ns per tick.
+ */
+#define WDOG_BASE 0x40000000
+
+#define WDOGLOAD 0
+#define WDOGVALUE 4
+#define WDOGCONTROL 8
+#define WDOGINTCLR 0xc
+#define WDOGRIS 0x10
+#define WDOGMIS 0x14
+#define WDOGLOCK 0xc00
+
+static void test_watchdog(void)
+{
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
+
+ writel(WDOG_BASE + WDOGCONTROL, 1);
+ writel(WDOG_BASE + WDOGLOAD, 1000);
+
+ /* Step to just past the 500th tick */
+ clock_step(500 * 80 + 1);
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500);
+
+ /* Just past the 1000th tick: timer should have fired */
+ clock_step(500 * 80);
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1);
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 0);
+
+ /* VALUE reloads at following tick */
+ clock_step(80);
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000);
+
+ /* Writing any value to WDOGINTCLR clears the interrupt and reloads */
+ clock_step(500 * 80);
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500);
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1);
+ writel(WDOG_BASE + WDOGINTCLR, 0);
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000);
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
+}
+
+int main(int argc, char **argv)
+{
+ QTestState *s;
+ int r;
+
+ g_test_init(&argc, &argv, NULL);
+
+ s = qtest_start("-machine lm3s811evb");
+
+ qtest_add_func("/cmsdk-apb-watchdog/watchdog", test_watchdog);
+
+ r = g_test_run();
+
+ qtest_end();
+
+ return r;
+}
diff --git a/MAINTAINERS b/MAINTAINERS
index 010405b0884..58956497888 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -588,6 +588,7 @@ F: hw/char/cmsdk-apb-uart.c
F: include/hw/char/cmsdk-apb-uart.h
F: hw/watchdog/cmsdk-apb-watchdog.c
F: include/hw/watchdog/cmsdk-apb-watchdog.h
+F: tests/qtest/cmsdk-apb-watchdog-test.c
F: hw/misc/tz-ppc.c
F: include/hw/misc/tz-ppc.h
F: hw/misc/tz-mpc.c
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index 74addd74868..9e2ebc47041 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -142,6 +142,7 @@ qtests_npcm7xx = \
'npcm7xx_watchdog_timer-test']
qtests_arm = \
(config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-timer-test'] : []) + \
+ (config_all_devices.has_key('CONFIG_CMSDK_APB_WATCHDOG') ? ['cmsdk-apb-watchdog-test'] : []) + \
(config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] : []) + \
(config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \
['arm-cpu-features',
--
2.20.1
^ permalink raw reply related [flat|nested] 80+ messages in thread* Re: [PATCH 04/25] tests: Add a simple test of the CMSDK APB watchdog
2021-01-21 19:06 ` [PATCH 04/25] tests: Add a simple test of the CMSDK APB watchdog Peter Maydell
@ 2021-01-24 13:10 ` Luc Michel
2021-01-27 21:54 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 80+ messages in thread
From: Luc Michel @ 2021-01-24 13:10 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, qemu-arm, qemu-devel, Philippe Mathieu-Daudé
On 19:06 Thu 21 Jan , Peter Maydell wrote:
> Add a simple test of the CMSDK watchdog, since we're about to do some
> refactoring of how it is clocked.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
> ---
> tests/qtest/cmsdk-apb-watchdog-test.c | 80 +++++++++++++++++++++++++++
> MAINTAINERS | 1 +
> tests/qtest/meson.build | 1 +
> 3 files changed, 82 insertions(+)
> create mode 100644 tests/qtest/cmsdk-apb-watchdog-test.c
>
> diff --git a/tests/qtest/cmsdk-apb-watchdog-test.c b/tests/qtest/cmsdk-apb-watchdog-test.c
> new file mode 100644
> index 00000000000..c6add1fee85
> --- /dev/null
> +++ b/tests/qtest/cmsdk-apb-watchdog-test.c
> @@ -0,0 +1,80 @@
> +/*
> + * QTest testcase for the CMSDK APB watchdog device
> + *
> + * Copyright (c) 2021 Linaro Limited
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
> + * for more details.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "libqtest-single.h"
> +
> +/*
> + * lm3s811evb watchdog; at board startup this runs at 200MHz / 16 == 12.5MHz,
> + * which is 80ns per tick.
> + */
> +#define WDOG_BASE 0x40000000
> +
> +#define WDOGLOAD 0
> +#define WDOGVALUE 4
> +#define WDOGCONTROL 8
> +#define WDOGINTCLR 0xc
> +#define WDOGRIS 0x10
> +#define WDOGMIS 0x14
> +#define WDOGLOCK 0xc00
> +
> +static void test_watchdog(void)
> +{
> + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
> +
> + writel(WDOG_BASE + WDOGCONTROL, 1);
> + writel(WDOG_BASE + WDOGLOAD, 1000);
> +
> + /* Step to just past the 500th tick */
> + clock_step(500 * 80 + 1);
> + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
> + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500);
> +
> + /* Just past the 1000th tick: timer should have fired */
> + clock_step(500 * 80);
> + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1);
> + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 0);
> +
> + /* VALUE reloads at following tick */
> + clock_step(80);
> + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000);
> +
> + /* Writing any value to WDOGINTCLR clears the interrupt and reloads */
> + clock_step(500 * 80);
> + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500);
> + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1);
> + writel(WDOG_BASE + WDOGINTCLR, 0);
> + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000);
> + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
> +}
> +
> +int main(int argc, char **argv)
> +{
> + QTestState *s;
> + int r;
> +
> + g_test_init(&argc, &argv, NULL);
> +
> + s = qtest_start("-machine lm3s811evb");
> +
> + qtest_add_func("/cmsdk-apb-watchdog/watchdog", test_watchdog);
> +
> + r = g_test_run();
> +
> + qtest_end();
> +
> + return r;
> +}
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 010405b0884..58956497888 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -588,6 +588,7 @@ F: hw/char/cmsdk-apb-uart.c
> F: include/hw/char/cmsdk-apb-uart.h
> F: hw/watchdog/cmsdk-apb-watchdog.c
> F: include/hw/watchdog/cmsdk-apb-watchdog.h
> +F: tests/qtest/cmsdk-apb-watchdog-test.c
> F: hw/misc/tz-ppc.c
> F: include/hw/misc/tz-ppc.h
> F: hw/misc/tz-mpc.c
> diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
> index 74addd74868..9e2ebc47041 100644
> --- a/tests/qtest/meson.build
> +++ b/tests/qtest/meson.build
> @@ -142,6 +142,7 @@ qtests_npcm7xx = \
> 'npcm7xx_watchdog_timer-test']
> qtests_arm = \
> (config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-timer-test'] : []) + \
> + (config_all_devices.has_key('CONFIG_CMSDK_APB_WATCHDOG') ? ['cmsdk-apb-watchdog-test'] : []) + \
> (config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] : []) + \
> (config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \
> ['arm-cpu-features',
> --
> 2.20.1
>
--
^ permalink raw reply [flat|nested] 80+ messages in thread* Re: [PATCH 04/25] tests: Add a simple test of the CMSDK APB watchdog
2021-01-21 19:06 ` [PATCH 04/25] tests: Add a simple test of the CMSDK APB watchdog Peter Maydell
2021-01-24 13:10 ` Luc Michel
@ 2021-01-27 21:54 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 80+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-27 21:54 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel; +Cc: Damien Hedde, Luc Michel
On 1/21/21 8:06 PM, Peter Maydell wrote:
> Add a simple test of the CMSDK watchdog, since we're about to do some
> refactoring of how it is clocked.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> tests/qtest/cmsdk-apb-watchdog-test.c | 80 +++++++++++++++++++++++++++
> MAINTAINERS | 1 +
> tests/qtest/meson.build | 1 +
> 3 files changed, 82 insertions(+)
> create mode 100644 tests/qtest/cmsdk-apb-watchdog-test.c
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 80+ messages in thread
* [PATCH 05/25] tests: Add a simple test of the CMSDK APB dual timer
2021-01-21 19:05 [PATCH 00/25] Convert CMSDK timer, watchdog, dualtimer to Clock framework Peter Maydell
` (3 preceding siblings ...)
2021-01-21 19:06 ` [PATCH 04/25] tests: Add a simple test of the CMSDK APB watchdog Peter Maydell
@ 2021-01-21 19:06 ` Peter Maydell
2021-01-24 13:24 ` Luc Michel
2021-01-21 19:06 ` [PATCH 06/25] hw/timer/cmsdk-apb-timer: Rename CMSDKAPBTIMER struct to CMSDKAPBTimer Peter Maydell
` (19 subsequent siblings)
24 siblings, 1 reply; 80+ messages in thread
From: Peter Maydell @ 2021-01-21 19:06 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Philippe Mathieu-Daudé
Add a simple test of the CMSDK dual timer, since we're about to do
some refactoring of how it is clocked.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
tests/qtest/cmsdk-apb-dualtimer-test.c | 131 +++++++++++++++++++++++++
MAINTAINERS | 1 +
tests/qtest/meson.build | 1 +
3 files changed, 133 insertions(+)
create mode 100644 tests/qtest/cmsdk-apb-dualtimer-test.c
diff --git a/tests/qtest/cmsdk-apb-dualtimer-test.c b/tests/qtest/cmsdk-apb-dualtimer-test.c
new file mode 100644
index 00000000000..5a29d65fd6d
--- /dev/null
+++ b/tests/qtest/cmsdk-apb-dualtimer-test.c
@@ -0,0 +1,131 @@
+/*
+ * QTest testcase for the CMSDK APB dualtimer device
+ *
+ * Copyright (c) 2021 Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+#include "libqtest-single.h"
+
+/* IoTKit/ARMSSE dualtimer; driven at 25MHz in mps2-an385, so 40ns per tick */
+#define TIMER_BASE 0x40002000
+
+#define TIMER1LOAD 0
+#define TIMER1VALUE 4
+#define TIMER1CONTROL 8
+#define TIMER1INTCLR 0xc
+#define TIMER1RIS 0x10
+#define TIMER1MIS 0x14
+#define TIMER1BGLOAD 0x18
+
+#define TIMER2LOAD 0x20
+#define TIMER2VALUE 0x24
+#define TIMER2CONTROL 0x28
+#define TIMER2INTCLR 0x2c
+#define TIMER2RIS 0x30
+#define TIMER2MIS 0x34
+#define TIMER2BGLOAD 0x38
+
+#define CTRL_ENABLE (1 << 7)
+#define CTRL_PERIODIC (1 << 6)
+#define CTRL_INTEN (1 << 5)
+#define CTRL_PRESCALE_1 (0 << 2)
+#define CTRL_PRESCALE_16 (1 << 2)
+#define CTRL_PRESCALE_256 (2 << 2)
+#define CTRL_32BIT (1 << 1)
+#define CTRL_ONESHOT (1 << 0)
+
+static void test_dualtimer(void)
+{
+ g_assert_true(readl(TIMER_BASE + TIMER1RIS) == 0);
+
+ /* Start timer: will fire after 40000 ns */
+ writel(TIMER_BASE + TIMER1LOAD, 1000);
+ /* enable in free-running, wrapping, interrupt mode */
+ writel(TIMER_BASE + TIMER1CONTROL, CTRL_ENABLE | CTRL_INTEN);
+
+ /* Step to just past the 500th tick and check VALUE */
+ clock_step(20001);
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER1RIS), ==, 0);
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER1VALUE), ==, 500);
+
+ /* Just past the 1000th tick: timer should have fired */
+ clock_step(20000);
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER1RIS), ==, 1);
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER1VALUE), ==, 0);
+
+ /*
+ * We are in free-running wrapping 16-bit mode, so on the following
+ * tick VALUE should have wrapped round to 0xffff.
+ */
+ clock_step(40);
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER1VALUE), ==, 0xffff);
+
+ /* Check that any write to INTCLR clears interrupt */
+ writel(TIMER_BASE + TIMER1INTCLR, 1);
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER1RIS), ==, 0);
+
+ /* Turn off the timer */
+ writel(TIMER_BASE + TIMER1CONTROL, 0);
+}
+
+static void test_prescale(void)
+{
+ g_assert_true(readl(TIMER_BASE + TIMER2RIS) == 0);
+
+ /* Start timer: will fire after 40 * 256 * 1000 == 1024000 ns */
+ writel(TIMER_BASE + TIMER2LOAD, 1000);
+ /* enable in periodic, wrapping, interrupt mode, prescale 256 */
+ writel(TIMER_BASE + TIMER2CONTROL,
+ CTRL_ENABLE | CTRL_INTEN | CTRL_PERIODIC | CTRL_PRESCALE_256);
+
+ /* Step to just past the 500th tick and check VALUE */
+ clock_step(40 * 256 * 501);
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER2RIS), ==, 0);
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER2VALUE), ==, 500);
+
+ /* Just past the 1000th tick: timer should have fired */
+ clock_step(40 * 256 * 500);
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER2RIS), ==, 1);
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER2VALUE), ==, 0);
+
+ /* In periodic mode the tick VALUE now reloads */
+ clock_step(256);
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER2VALUE), ==, 1000);
+
+ /* Check that any write to INTCLR clears interrupt */
+ writel(TIMER_BASE + TIMER2INTCLR, 1);
+ g_assert_cmpuint(readl(TIMER_BASE + TIMER2RIS), ==, 0);
+
+ /* Turn off the timer */
+ writel(TIMER_BASE + TIMER2CONTROL, 0);
+}
+
+int main(int argc, char **argv)
+{
+ QTestState *s;
+ int r;
+
+ g_test_init(&argc, &argv, NULL);
+
+ s = qtest_start("-machine mps2-an385");
+
+ qtest_add_func("/cmsdk-apb-dualtimer/dualtimer", test_dualtimer);
+ qtest_add_func("/cmsdk-apb-dualtimer/prescale", test_prescale);
+
+ r = g_test_run();
+
+ qtest_end();
+
+ return r;
+}
diff --git a/MAINTAINERS b/MAINTAINERS
index 58956497888..118f70e47fb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -584,6 +584,7 @@ F: include/hw/timer/cmsdk-apb-timer.h
F: tests/qtest/cmsdk-apb-timer-test.c
F: hw/timer/cmsdk-apb-dualtimer.c
F: include/hw/timer/cmsdk-apb-dualtimer.h
+F: tests/qtest/cmsdk-apb-dualtimer-test.c
F: hw/char/cmsdk-apb-uart.c
F: include/hw/char/cmsdk-apb-uart.h
F: hw/watchdog/cmsdk-apb-watchdog.c
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index 9e2ebc47041..69dd4a8547c 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -141,6 +141,7 @@ qtests_npcm7xx = \
'npcm7xx_timer-test',
'npcm7xx_watchdog_timer-test']
qtests_arm = \
+ (config_all_devices.has_key('CONFIG_CMSDK_APB_DUALTIMER') ? ['cmsdk-apb-dualtimer-test'] : []) + \
(config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-timer-test'] : []) + \
(config_all_devices.has_key('CONFIG_CMSDK_APB_WATCHDOG') ? ['cmsdk-apb-watchdog-test'] : []) + \
(config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] : []) + \
--
2.20.1
^ permalink raw reply related [flat|nested] 80+ messages in thread* Re: [PATCH 05/25] tests: Add a simple test of the CMSDK APB dual timer
2021-01-21 19:06 ` [PATCH 05/25] tests: Add a simple test of the CMSDK APB dual timer Peter Maydell
@ 2021-01-24 13:24 ` Luc Michel
0 siblings, 0 replies; 80+ messages in thread
From: Luc Michel @ 2021-01-24 13:24 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, qemu-arm, qemu-devel, Philippe Mathieu-Daudé
On 19:06 Thu 21 Jan , Peter Maydell wrote:
> Add a simple test of the CMSDK dual timer, since we're about to do
> some refactoring of how it is clocked.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> tests/qtest/cmsdk-apb-dualtimer-test.c | 131 +++++++++++++++++++++++++
> MAINTAINERS | 1 +
> tests/qtest/meson.build | 1 +
> 3 files changed, 133 insertions(+)
> create mode 100644 tests/qtest/cmsdk-apb-dualtimer-test.c
>
> diff --git a/tests/qtest/cmsdk-apb-dualtimer-test.c b/tests/qtest/cmsdk-apb-dualtimer-test.c
> new file mode 100644
> index 00000000000..5a29d65fd6d
> --- /dev/null
> +++ b/tests/qtest/cmsdk-apb-dualtimer-test.c
> @@ -0,0 +1,131 @@
> +/*
> + * QTest testcase for the CMSDK APB dualtimer device
> + *
> + * Copyright (c) 2021 Linaro Limited
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
> + * for more details.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "libqtest-single.h"
> +
> +/* IoTKit/ARMSSE dualtimer; driven at 25MHz in mps2-an385, so 40ns per tick */
> +#define TIMER_BASE 0x40002000
> +
> +#define TIMER1LOAD 0
> +#define TIMER1VALUE 4
> +#define TIMER1CONTROL 8
> +#define TIMER1INTCLR 0xc
> +#define TIMER1RIS 0x10
> +#define TIMER1MIS 0x14
> +#define TIMER1BGLOAD 0x18
> +
> +#define TIMER2LOAD 0x20
> +#define TIMER2VALUE 0x24
> +#define TIMER2CONTROL 0x28
> +#define TIMER2INTCLR 0x2c
> +#define TIMER2RIS 0x30
> +#define TIMER2MIS 0x34
> +#define TIMER2BGLOAD 0x38
> +
> +#define CTRL_ENABLE (1 << 7)
> +#define CTRL_PERIODIC (1 << 6)
> +#define CTRL_INTEN (1 << 5)
> +#define CTRL_PRESCALE_1 (0 << 2)
> +#define CTRL_PRESCALE_16 (1 << 2)
> +#define CTRL_PRESCALE_256 (2 << 2)
> +#define CTRL_32BIT (1 << 1)
> +#define CTRL_ONESHOT (1 << 0)
> +
> +static void test_dualtimer(void)
> +{
> + g_assert_true(readl(TIMER_BASE + TIMER1RIS) == 0);
> +
> + /* Start timer: will fire after 40000 ns */
> + writel(TIMER_BASE + TIMER1LOAD, 1000);
> + /* enable in free-running, wrapping, interrupt mode */
> + writel(TIMER_BASE + TIMER1CONTROL, CTRL_ENABLE | CTRL_INTEN);
> +
> + /* Step to just past the 500th tick and check VALUE */
> + clock_step(20001);
> + g_assert_cmpuint(readl(TIMER_BASE + TIMER1RIS), ==, 0);
> + g_assert_cmpuint(readl(TIMER_BASE + TIMER1VALUE), ==, 500);
> +
> + /* Just past the 1000th tick: timer should have fired */
> + clock_step(20000);
> + g_assert_cmpuint(readl(TIMER_BASE + TIMER1RIS), ==, 1);
> + g_assert_cmpuint(readl(TIMER_BASE + TIMER1VALUE), ==, 0);
> +
> + /*
> + * We are in free-running wrapping 16-bit mode, so on the following
> + * tick VALUE should have wrapped round to 0xffff.
> + */
> + clock_step(40);
> + g_assert_cmpuint(readl(TIMER_BASE + TIMER1VALUE), ==, 0xffff);
> +
> + /* Check that any write to INTCLR clears interrupt */
> + writel(TIMER_BASE + TIMER1INTCLR, 1);
> + g_assert_cmpuint(readl(TIMER_BASE + TIMER1RIS), ==, 0);
> +
> + /* Turn off the timer */
> + writel(TIMER_BASE + TIMER1CONTROL, 0);
> +}
> +
> +static void test_prescale(void)
> +{
> + g_assert_true(readl(TIMER_BASE + TIMER2RIS) == 0);
> +
> + /* Start timer: will fire after 40 * 256 * 1000 == 1024000 ns */
> + writel(TIMER_BASE + TIMER2LOAD, 1000);
> + /* enable in periodic, wrapping, interrupt mode, prescale 256 */
> + writel(TIMER_BASE + TIMER2CONTROL,
> + CTRL_ENABLE | CTRL_INTEN | CTRL_PERIODIC | CTRL_PRESCALE_256);
> +
> + /* Step to just past the 500th tick and check VALUE */
> + clock_step(40 * 256 * 501);
> + g_assert_cmpuint(readl(TIMER_BASE + TIMER2RIS), ==, 0);
> + g_assert_cmpuint(readl(TIMER_BASE + TIMER2VALUE), ==, 500);
> +
> + /* Just past the 1000th tick: timer should have fired */
> + clock_step(40 * 256 * 500);
> + g_assert_cmpuint(readl(TIMER_BASE + TIMER2RIS), ==, 1);
> + g_assert_cmpuint(readl(TIMER_BASE + TIMER2VALUE), ==, 0);
> +
> + /* In periodic mode the tick VALUE now reloads */
> + clock_step(256);
Shouldn't it be "clock_step(40 * 256)", i.e. 1 tick?
> + g_assert_cmpuint(readl(TIMER_BASE + TIMER2VALUE), ==, 1000);
> +
> + /* Check that any write to INTCLR clears interrupt */
> + writel(TIMER_BASE + TIMER2INTCLR, 1);
> + g_assert_cmpuint(readl(TIMER_BASE + TIMER2RIS), ==, 0);
> +
> + /* Turn off the timer */
> + writel(TIMER_BASE + TIMER2CONTROL, 0);
> +}
> +
> +int main(int argc, char **argv)
> +{
> + QTestState *s;
> + int r;
> +
> + g_test_init(&argc, &argv, NULL);
> +
> + s = qtest_start("-machine mps2-an385");
> +
> + qtest_add_func("/cmsdk-apb-dualtimer/dualtimer", test_dualtimer);
> + qtest_add_func("/cmsdk-apb-dualtimer/prescale", test_prescale);
> +
> + r = g_test_run();
> +
> + qtest_end();
> +
> + return r;
> +}
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 58956497888..118f70e47fb 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -584,6 +584,7 @@ F: include/hw/timer/cmsdk-apb-timer.h
> F: tests/qtest/cmsdk-apb-timer-test.c
> F: hw/timer/cmsdk-apb-dualtimer.c
> F: include/hw/timer/cmsdk-apb-dualtimer.h
> +F: tests/qtest/cmsdk-apb-dualtimer-test.c
> F: hw/char/cmsdk-apb-uart.c
> F: include/hw/char/cmsdk-apb-uart.h
> F: hw/watchdog/cmsdk-apb-watchdog.c
> diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
> index 9e2ebc47041..69dd4a8547c 100644
> --- a/tests/qtest/meson.build
> +++ b/tests/qtest/meson.build
> @@ -141,6 +141,7 @@ qtests_npcm7xx = \
> 'npcm7xx_timer-test',
> 'npcm7xx_watchdog_timer-test']
> qtests_arm = \
> + (config_all_devices.has_key('CONFIG_CMSDK_APB_DUALTIMER') ? ['cmsdk-apb-dualtimer-test'] : []) + \
> (config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-timer-test'] : []) + \
> (config_all_devices.has_key('CONFIG_CMSDK_APB_WATCHDOG') ? ['cmsdk-apb-watchdog-test'] : []) + \
> (config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] : []) + \
> --
> 2.20.1
>
--
^ permalink raw reply [flat|nested] 80+ messages in thread
* [PATCH 06/25] hw/timer/cmsdk-apb-timer: Rename CMSDKAPBTIMER struct to CMSDKAPBTimer
2021-01-21 19:05 [PATCH 00/25] Convert CMSDK timer, watchdog, dualtimer to Clock framework Peter Maydell
` (4 preceding siblings ...)
2021-01-21 19:06 ` [PATCH 05/25] tests: Add a simple test of the CMSDK APB dual timer Peter Maydell
@ 2021-01-21 19:06 ` Peter Maydell
2021-01-21 20:21 ` Philippe Mathieu-Daudé
2021-01-22 14:22 ` Luc Michel
2021-01-21 19:06 ` [PATCH 07/25] hw/timer/cmsdk-apb-timer: Add Clock input Peter Maydell
` (18 subsequent siblings)
24 siblings, 2 replies; 80+ messages in thread
From: Peter Maydell @ 2021-01-21 19:06 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Philippe Mathieu-Daudé
The state struct for the CMSDK APB timer device doesn't follow our
usual naming convention of camelcase -- "CMSDK" and "APB" are both
acronyms, but "TIMER" is not so should not be all-uppercase.
Globally rename the struct to "CMSDKAPBTimer" (bringing it into line
with CMSDKAPBWatchdog and CMSDKAPBDualTimer; CMSDKAPBUART remains
as-is because "UART" is an acronym).
Commit created with:
perl -p -i -e 's/CMSDKAPBTIMER/CMSDKAPBTimer/g' hw/timer/cmsdk-apb-timer.c include/hw/arm/armsse.h include/hw/timer/cmsdk-apb-timer.h
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/armsse.h | 6 +++---
include/hw/timer/cmsdk-apb-timer.h | 4 ++--
hw/timer/cmsdk-apb-timer.c | 28 ++++++++++++++--------------
3 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
index 77f86771c30..83f5e28c16e 100644
--- a/include/hw/arm/armsse.h
+++ b/include/hw/arm/armsse.h
@@ -153,9 +153,9 @@ struct ARMSSE {
TZPPC apb_ppc0;
TZPPC apb_ppc1;
TZMPC mpc[IOTS_NUM_MPC];
- CMSDKAPBTIMER timer0;
- CMSDKAPBTIMER timer1;
- CMSDKAPBTIMER s32ktimer;
+ CMSDKAPBTimer timer0;
+ CMSDKAPBTimer timer1;
+ CMSDKAPBTimer s32ktimer;
qemu_or_irq ppc_irq_orgate;
SplitIRQ sec_resp_splitter;
SplitIRQ ppc_irq_splitter[NUM_PPCS];
diff --git a/include/hw/timer/cmsdk-apb-timer.h b/include/hw/timer/cmsdk-apb-timer.h
index 0d80b2a48cd..baa009bb2da 100644
--- a/include/hw/timer/cmsdk-apb-timer.h
+++ b/include/hw/timer/cmsdk-apb-timer.h
@@ -18,9 +18,9 @@
#include "qom/object.h"
#define TYPE_CMSDK_APB_TIMER "cmsdk-apb-timer"
-OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBTIMER, CMSDK_APB_TIMER)
+OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBTimer, CMSDK_APB_TIMER)
-struct CMSDKAPBTIMER {
+struct CMSDKAPBTimer {
/*< private >*/
SysBusDevice parent_obj;
diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c
index f85f1309f37..ae9c5422540 100644
--- a/hw/timer/cmsdk-apb-timer.c
+++ b/hw/timer/cmsdk-apb-timer.c
@@ -67,14 +67,14 @@ static const int timer_id[] = {
0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
};
-static void cmsdk_apb_timer_update(CMSDKAPBTIMER *s)
+static void cmsdk_apb_timer_update(CMSDKAPBTimer *s)
{
qemu_set_irq(s->timerint, !!(s->intstatus & R_INTSTATUS_IRQ_MASK));
}
static uint64_t cmsdk_apb_timer_read(void *opaque, hwaddr offset, unsigned size)
{
- CMSDKAPBTIMER *s = CMSDK_APB_TIMER(opaque);
+ CMSDKAPBTimer *s = CMSDK_APB_TIMER(opaque);
uint64_t r;
switch (offset) {
@@ -106,7 +106,7 @@ static uint64_t cmsdk_apb_timer_read(void *opaque, hwaddr offset, unsigned size)
static void cmsdk_apb_timer_write(void *opaque, hwaddr offset, uint64_t value,
unsigned size)
{
- CMSDKAPBTIMER *s = CMSDK_APB_TIMER(opaque);
+ CMSDKAPBTimer *s = CMSDK_APB_TIMER(opaque);
trace_cmsdk_apb_timer_write(offset, value, size);
@@ -181,7 +181,7 @@ static const MemoryRegionOps cmsdk_apb_timer_ops = {
static void cmsdk_apb_timer_tick(void *opaque)
{
- CMSDKAPBTIMER *s = CMSDK_APB_TIMER(opaque);
+ CMSDKAPBTimer *s = CMSDK_APB_TIMER(opaque);
if (s->ctrl & R_CTRL_IRQEN_MASK) {
s->intstatus |= R_INTSTATUS_IRQ_MASK;
@@ -191,7 +191,7 @@ static void cmsdk_apb_timer_tick(void *opaque)
static void cmsdk_apb_timer_reset(DeviceState *dev)
{
- CMSDKAPBTIMER *s = CMSDK_APB_TIMER(dev);
+ CMSDKAPBTimer *s = CMSDK_APB_TIMER(dev);
trace_cmsdk_apb_timer_reset();
s->ctrl = 0;
@@ -206,7 +206,7 @@ static void cmsdk_apb_timer_reset(DeviceState *dev)
static void cmsdk_apb_timer_init(Object *obj)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
- CMSDKAPBTIMER *s = CMSDK_APB_TIMER(obj);
+ CMSDKAPBTimer *s = CMSDK_APB_TIMER(obj);
memory_region_init_io(&s->iomem, obj, &cmsdk_apb_timer_ops,
s, "cmsdk-apb-timer", 0x1000);
@@ -216,7 +216,7 @@ static void cmsdk_apb_timer_init(Object *obj)
static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp)
{
- CMSDKAPBTIMER *s = CMSDK_APB_TIMER(dev);
+ CMSDKAPBTimer *s = CMSDK_APB_TIMER(dev);
if (s->pclk_frq == 0) {
error_setg(errp, "CMSDK APB timer: pclk-frq property must be set");
@@ -239,17 +239,17 @@ static const VMStateDescription cmsdk_apb_timer_vmstate = {
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
- VMSTATE_PTIMER(timer, CMSDKAPBTIMER),
- VMSTATE_UINT32(ctrl, CMSDKAPBTIMER),
- VMSTATE_UINT32(value, CMSDKAPBTIMER),
- VMSTATE_UINT32(reload, CMSDKAPBTIMER),
- VMSTATE_UINT32(intstatus, CMSDKAPBTIMER),
+ VMSTATE_PTIMER(timer, CMSDKAPBTimer),
+ VMSTATE_UINT32(ctrl, CMSDKAPBTimer),
+ VMSTATE_UINT32(value, CMSDKAPBTimer),
+ VMSTATE_UINT32(reload, CMSDKAPBTimer),
+ VMSTATE_UINT32(intstatus, CMSDKAPBTimer),
VMSTATE_END_OF_LIST()
}
};
static Property cmsdk_apb_timer_properties[] = {
- DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBTIMER, pclk_frq, 0),
+ DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBTimer, pclk_frq, 0),
DEFINE_PROP_END_OF_LIST(),
};
@@ -266,7 +266,7 @@ static void cmsdk_apb_timer_class_init(ObjectClass *klass, void *data)
static const TypeInfo cmsdk_apb_timer_info = {
.name = TYPE_CMSDK_APB_TIMER,
.parent = TYPE_SYS_BUS_DEVICE,
- .instance_size = sizeof(CMSDKAPBTIMER),
+ .instance_size = sizeof(CMSDKAPBTimer),
.instance_init = cmsdk_apb_timer_init,
.class_init = cmsdk_apb_timer_class_init,
};
--
2.20.1
^ permalink raw reply related [flat|nested] 80+ messages in thread* Re: [PATCH 06/25] hw/timer/cmsdk-apb-timer: Rename CMSDKAPBTIMER struct to CMSDKAPBTimer
2021-01-21 19:06 ` [PATCH 06/25] hw/timer/cmsdk-apb-timer: Rename CMSDKAPBTIMER struct to CMSDKAPBTimer Peter Maydell
@ 2021-01-21 20:21 ` Philippe Mathieu-Daudé
2021-01-22 14:22 ` Luc Michel
1 sibling, 0 replies; 80+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-21 20:21 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel; +Cc: Damien Hedde, Luc Michel
On 1/21/21 8:06 PM, Peter Maydell wrote:
> The state struct for the CMSDK APB timer device doesn't follow our
> usual naming convention of camelcase -- "CMSDK" and "APB" are both
> acronyms, but "TIMER" is not so should not be all-uppercase.
> Globally rename the struct to "CMSDKAPBTimer" (bringing it into line
> with CMSDKAPBWatchdog and CMSDKAPBDualTimer; CMSDKAPBUART remains
> as-is because "UART" is an acronym).
>
> Commit created with:
> perl -p -i -e 's/CMSDKAPBTIMER/CMSDKAPBTimer/g' hw/timer/cmsdk-apb-timer.c include/hw/arm/armsse.h include/hw/timer/cmsdk-apb-timer.h
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> include/hw/arm/armsse.h | 6 +++---
> include/hw/timer/cmsdk-apb-timer.h | 4 ++--
> hw/timer/cmsdk-apb-timer.c | 28 ++++++++++++++--------------
> 3 files changed, 19 insertions(+), 19 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 06/25] hw/timer/cmsdk-apb-timer: Rename CMSDKAPBTIMER struct to CMSDKAPBTimer
2021-01-21 19:06 ` [PATCH 06/25] hw/timer/cmsdk-apb-timer: Rename CMSDKAPBTIMER struct to CMSDKAPBTimer Peter Maydell
2021-01-21 20:21 ` Philippe Mathieu-Daudé
@ 2021-01-22 14:22 ` Luc Michel
1 sibling, 0 replies; 80+ messages in thread
From: Luc Michel @ 2021-01-22 14:22 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, qemu-arm, qemu-devel, Philippe Mathieu-Daudé
On 19:06 Thu 21 Jan , Peter Maydell wrote:
> The state struct for the CMSDK APB timer device doesn't follow our
> usual naming convention of camelcase -- "CMSDK" and "APB" are both
> acronyms, but "TIMER" is not so should not be all-uppercase.
> Globally rename the struct to "CMSDKAPBTimer" (bringing it into line
> with CMSDKAPBWatchdog and CMSDKAPBDualTimer; CMSDKAPBUART remains
> as-is because "UART" is an acronym).
>
> Commit created with:
> perl -p -i -e 's/CMSDKAPBTIMER/CMSDKAPBTimer/g' hw/timer/cmsdk-apb-timer.c include/hw/arm/armsse.h include/hw/timer/cmsdk-apb-timer.h
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
> ---
> include/hw/arm/armsse.h | 6 +++---
> include/hw/timer/cmsdk-apb-timer.h | 4 ++--
> hw/timer/cmsdk-apb-timer.c | 28 ++++++++++++++--------------
> 3 files changed, 19 insertions(+), 19 deletions(-)
>
> diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
> index 77f86771c30..83f5e28c16e 100644
> --- a/include/hw/arm/armsse.h
> +++ b/include/hw/arm/armsse.h
> @@ -153,9 +153,9 @@ struct ARMSSE {
> TZPPC apb_ppc0;
> TZPPC apb_ppc1;
> TZMPC mpc[IOTS_NUM_MPC];
> - CMSDKAPBTIMER timer0;
> - CMSDKAPBTIMER timer1;
> - CMSDKAPBTIMER s32ktimer;
> + CMSDKAPBTimer timer0;
> + CMSDKAPBTimer timer1;
> + CMSDKAPBTimer s32ktimer;
> qemu_or_irq ppc_irq_orgate;
> SplitIRQ sec_resp_splitter;
> SplitIRQ ppc_irq_splitter[NUM_PPCS];
> diff --git a/include/hw/timer/cmsdk-apb-timer.h b/include/hw/timer/cmsdk-apb-timer.h
> index 0d80b2a48cd..baa009bb2da 100644
> --- a/include/hw/timer/cmsdk-apb-timer.h
> +++ b/include/hw/timer/cmsdk-apb-timer.h
> @@ -18,9 +18,9 @@
> #include "qom/object.h"
>
> #define TYPE_CMSDK_APB_TIMER "cmsdk-apb-timer"
> -OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBTIMER, CMSDK_APB_TIMER)
> +OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBTimer, CMSDK_APB_TIMER)
>
> -struct CMSDKAPBTIMER {
> +struct CMSDKAPBTimer {
> /*< private >*/
> SysBusDevice parent_obj;
>
> diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c
> index f85f1309f37..ae9c5422540 100644
> --- a/hw/timer/cmsdk-apb-timer.c
> +++ b/hw/timer/cmsdk-apb-timer.c
> @@ -67,14 +67,14 @@ static const int timer_id[] = {
> 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
> };
>
> -static void cmsdk_apb_timer_update(CMSDKAPBTIMER *s)
> +static void cmsdk_apb_timer_update(CMSDKAPBTimer *s)
> {
> qemu_set_irq(s->timerint, !!(s->intstatus & R_INTSTATUS_IRQ_MASK));
> }
>
> static uint64_t cmsdk_apb_timer_read(void *opaque, hwaddr offset, unsigned size)
> {
> - CMSDKAPBTIMER *s = CMSDK_APB_TIMER(opaque);
> + CMSDKAPBTimer *s = CMSDK_APB_TIMER(opaque);
> uint64_t r;
>
> switch (offset) {
> @@ -106,7 +106,7 @@ static uint64_t cmsdk_apb_timer_read(void *opaque, hwaddr offset, unsigned size)
> static void cmsdk_apb_timer_write(void *opaque, hwaddr offset, uint64_t value,
> unsigned size)
> {
> - CMSDKAPBTIMER *s = CMSDK_APB_TIMER(opaque);
> + CMSDKAPBTimer *s = CMSDK_APB_TIMER(opaque);
>
> trace_cmsdk_apb_timer_write(offset, value, size);
>
> @@ -181,7 +181,7 @@ static const MemoryRegionOps cmsdk_apb_timer_ops = {
>
> static void cmsdk_apb_timer_tick(void *opaque)
> {
> - CMSDKAPBTIMER *s = CMSDK_APB_TIMER(opaque);
> + CMSDKAPBTimer *s = CMSDK_APB_TIMER(opaque);
>
> if (s->ctrl & R_CTRL_IRQEN_MASK) {
> s->intstatus |= R_INTSTATUS_IRQ_MASK;
> @@ -191,7 +191,7 @@ static void cmsdk_apb_timer_tick(void *opaque)
>
> static void cmsdk_apb_timer_reset(DeviceState *dev)
> {
> - CMSDKAPBTIMER *s = CMSDK_APB_TIMER(dev);
> + CMSDKAPBTimer *s = CMSDK_APB_TIMER(dev);
>
> trace_cmsdk_apb_timer_reset();
> s->ctrl = 0;
> @@ -206,7 +206,7 @@ static void cmsdk_apb_timer_reset(DeviceState *dev)
> static void cmsdk_apb_timer_init(Object *obj)
> {
> SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
> - CMSDKAPBTIMER *s = CMSDK_APB_TIMER(obj);
> + CMSDKAPBTimer *s = CMSDK_APB_TIMER(obj);
>
> memory_region_init_io(&s->iomem, obj, &cmsdk_apb_timer_ops,
> s, "cmsdk-apb-timer", 0x1000);
> @@ -216,7 +216,7 @@ static void cmsdk_apb_timer_init(Object *obj)
>
> static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp)
> {
> - CMSDKAPBTIMER *s = CMSDK_APB_TIMER(dev);
> + CMSDKAPBTimer *s = CMSDK_APB_TIMER(dev);
>
> if (s->pclk_frq == 0) {
> error_setg(errp, "CMSDK APB timer: pclk-frq property must be set");
> @@ -239,17 +239,17 @@ static const VMStateDescription cmsdk_apb_timer_vmstate = {
> .version_id = 1,
> .minimum_version_id = 1,
> .fields = (VMStateField[]) {
> - VMSTATE_PTIMER(timer, CMSDKAPBTIMER),
> - VMSTATE_UINT32(ctrl, CMSDKAPBTIMER),
> - VMSTATE_UINT32(value, CMSDKAPBTIMER),
> - VMSTATE_UINT32(reload, CMSDKAPBTIMER),
> - VMSTATE_UINT32(intstatus, CMSDKAPBTIMER),
> + VMSTATE_PTIMER(timer, CMSDKAPBTimer),
> + VMSTATE_UINT32(ctrl, CMSDKAPBTimer),
> + VMSTATE_UINT32(value, CMSDKAPBTimer),
> + VMSTATE_UINT32(reload, CMSDKAPBTimer),
> + VMSTATE_UINT32(intstatus, CMSDKAPBTimer),
> VMSTATE_END_OF_LIST()
> }
> };
>
> static Property cmsdk_apb_timer_properties[] = {
> - DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBTIMER, pclk_frq, 0),
> + DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBTimer, pclk_frq, 0),
> DEFINE_PROP_END_OF_LIST(),
> };
>
> @@ -266,7 +266,7 @@ static void cmsdk_apb_timer_class_init(ObjectClass *klass, void *data)
> static const TypeInfo cmsdk_apb_timer_info = {
> .name = TYPE_CMSDK_APB_TIMER,
> .parent = TYPE_SYS_BUS_DEVICE,
> - .instance_size = sizeof(CMSDKAPBTIMER),
> + .instance_size = sizeof(CMSDKAPBTimer),
> .instance_init = cmsdk_apb_timer_init,
> .class_init = cmsdk_apb_timer_class_init,
> };
> --
> 2.20.1
>
--
^ permalink raw reply [flat|nested] 80+ messages in thread
* [PATCH 07/25] hw/timer/cmsdk-apb-timer: Add Clock input
2021-01-21 19:05 [PATCH 00/25] Convert CMSDK timer, watchdog, dualtimer to Clock framework Peter Maydell
` (5 preceding siblings ...)
2021-01-21 19:06 ` [PATCH 06/25] hw/timer/cmsdk-apb-timer: Rename CMSDKAPBTIMER struct to CMSDKAPBTimer Peter Maydell
@ 2021-01-21 19:06 ` Peter Maydell
2021-01-21 20:22 ` Philippe Mathieu-Daudé
2021-01-22 15:11 ` Luc Michel
2021-01-21 19:06 ` [PATCH 08/25] hw/timer/cmsdk-apb-dualtimer: " Peter Maydell
` (17 subsequent siblings)
24 siblings, 2 replies; 80+ messages in thread
From: Peter Maydell @ 2021-01-21 19:06 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Philippe Mathieu-Daudé
As the first step in converting the CMSDK_APB_TIMER device to the
Clock framework, add a Clock input. For the moment we do nothing
with this clock; we will change the behaviour from using the pclk-frq
property to using the Clock once all the users of this device have
been converted to wire up the Clock.
Since the device doesn't already have a doc comment for its "QEMU
interface", we add one including the new Clock.
This is a migration compatibility break for machines mps2-an505,
mps2-an521, musca-a, musca-b1.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/timer/cmsdk-apb-timer.h | 9 +++++++++
hw/timer/cmsdk-apb-timer.c | 7 +++++--
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/include/hw/timer/cmsdk-apb-timer.h b/include/hw/timer/cmsdk-apb-timer.h
index baa009bb2da..fc2aa97acac 100644
--- a/include/hw/timer/cmsdk-apb-timer.h
+++ b/include/hw/timer/cmsdk-apb-timer.h
@@ -15,11 +15,19 @@
#include "hw/qdev-properties.h"
#include "hw/sysbus.h"
#include "hw/ptimer.h"
+#include "hw/clock.h"
#include "qom/object.h"
#define TYPE_CMSDK_APB_TIMER "cmsdk-apb-timer"
OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBTimer, CMSDK_APB_TIMER)
+/*
+ * QEMU interface:
+ * + QOM property "pclk-frq": frequency at which the timer is clocked
+ * + Clock input "pclk": clock for the timer
+ * + sysbus MMIO region 0: the register bank
+ * + sysbus IRQ 0: timer interrupt TIMERINT
+ */
struct CMSDKAPBTimer {
/*< private >*/
SysBusDevice parent_obj;
@@ -29,6 +37,7 @@ struct CMSDKAPBTimer {
qemu_irq timerint;
uint32_t pclk_frq;
struct ptimer_state *timer;
+ Clock *pclk;
uint32_t ctrl;
uint32_t value;
diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c
index ae9c5422540..c63145ff553 100644
--- a/hw/timer/cmsdk-apb-timer.c
+++ b/hw/timer/cmsdk-apb-timer.c
@@ -35,6 +35,7 @@
#include "hw/sysbus.h"
#include "hw/irq.h"
#include "hw/registerfields.h"
+#include "hw/qdev-clock.h"
#include "hw/timer/cmsdk-apb-timer.h"
#include "migration/vmstate.h"
@@ -212,6 +213,7 @@ static void cmsdk_apb_timer_init(Object *obj)
s, "cmsdk-apb-timer", 0x1000);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->timerint);
+ s->pclk = qdev_init_clock_in(DEVICE(s), "pclk", NULL, NULL);
}
static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp)
@@ -236,10 +238,11 @@ static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp)
static const VMStateDescription cmsdk_apb_timer_vmstate = {
.name = "cmsdk-apb-timer",
- .version_id = 1,
- .minimum_version_id = 1,
+ .version_id = 2,
+ .minimum_version_id = 2,
.fields = (VMStateField[]) {
VMSTATE_PTIMER(timer, CMSDKAPBTimer),
+ VMSTATE_CLOCK(pclk, CMSDKAPBTimer),
VMSTATE_UINT32(ctrl, CMSDKAPBTimer),
VMSTATE_UINT32(value, CMSDKAPBTimer),
VMSTATE_UINT32(reload, CMSDKAPBTimer),
--
2.20.1
^ permalink raw reply related [flat|nested] 80+ messages in thread* Re: [PATCH 07/25] hw/timer/cmsdk-apb-timer: Add Clock input
2021-01-21 19:06 ` [PATCH 07/25] hw/timer/cmsdk-apb-timer: Add Clock input Peter Maydell
@ 2021-01-21 20:22 ` Philippe Mathieu-Daudé
2021-01-22 15:11 ` Luc Michel
1 sibling, 0 replies; 80+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-21 20:22 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel; +Cc: Damien Hedde, Luc Michel
On 1/21/21 8:06 PM, Peter Maydell wrote:
> As the first step in converting the CMSDK_APB_TIMER device to the
> Clock framework, add a Clock input. For the moment we do nothing
> with this clock; we will change the behaviour from using the pclk-frq
> property to using the Clock once all the users of this device have
> been converted to wire up the Clock.
>
> Since the device doesn't already have a doc comment for its "QEMU
> interface", we add one including the new Clock.
>
> This is a migration compatibility break for machines mps2-an505,
> mps2-an521, musca-a, musca-b1.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> include/hw/timer/cmsdk-apb-timer.h | 9 +++++++++
> hw/timer/cmsdk-apb-timer.c | 7 +++++--
> 2 files changed, 14 insertions(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 07/25] hw/timer/cmsdk-apb-timer: Add Clock input
2021-01-21 19:06 ` [PATCH 07/25] hw/timer/cmsdk-apb-timer: Add Clock input Peter Maydell
2021-01-21 20:22 ` Philippe Mathieu-Daudé
@ 2021-01-22 15:11 ` Luc Michel
1 sibling, 0 replies; 80+ messages in thread
From: Luc Michel @ 2021-01-22 15:11 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, qemu-arm, qemu-devel, Philippe Mathieu-Daudé
On 19:06 Thu 21 Jan , Peter Maydell wrote:
> As the first step in converting the CMSDK_APB_TIMER device to the
> Clock framework, add a Clock input. For the moment we do nothing
> with this clock; we will change the behaviour from using the pclk-frq
> property to using the Clock once all the users of this device have
> been converted to wire up the Clock.
>
> Since the device doesn't already have a doc comment for its "QEMU
> interface", we add one including the new Clock.
>
> This is a migration compatibility break for machines mps2-an505,
> mps2-an521, musca-a, musca-b1.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
> ---
> include/hw/timer/cmsdk-apb-timer.h | 9 +++++++++
> hw/timer/cmsdk-apb-timer.c | 7 +++++--
> 2 files changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/include/hw/timer/cmsdk-apb-timer.h b/include/hw/timer/cmsdk-apb-timer.h
> index baa009bb2da..fc2aa97acac 100644
> --- a/include/hw/timer/cmsdk-apb-timer.h
> +++ b/include/hw/timer/cmsdk-apb-timer.h
> @@ -15,11 +15,19 @@
> #include "hw/qdev-properties.h"
> #include "hw/sysbus.h"
> #include "hw/ptimer.h"
> +#include "hw/clock.h"
> #include "qom/object.h"
>
> #define TYPE_CMSDK_APB_TIMER "cmsdk-apb-timer"
> OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBTimer, CMSDK_APB_TIMER)
>
> +/*
> + * QEMU interface:
> + * + QOM property "pclk-frq": frequency at which the timer is clocked
> + * + Clock input "pclk": clock for the timer
> + * + sysbus MMIO region 0: the register bank
> + * + sysbus IRQ 0: timer interrupt TIMERINT
> + */
> struct CMSDKAPBTimer {
> /*< private >*/
> SysBusDevice parent_obj;
> @@ -29,6 +37,7 @@ struct CMSDKAPBTimer {
> qemu_irq timerint;
> uint32_t pclk_frq;
> struct ptimer_state *timer;
> + Clock *pclk;
>
> uint32_t ctrl;
> uint32_t value;
> diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c
> index ae9c5422540..c63145ff553 100644
> --- a/hw/timer/cmsdk-apb-timer.c
> +++ b/hw/timer/cmsdk-apb-timer.c
> @@ -35,6 +35,7 @@
> #include "hw/sysbus.h"
> #include "hw/irq.h"
> #include "hw/registerfields.h"
> +#include "hw/qdev-clock.h"
> #include "hw/timer/cmsdk-apb-timer.h"
> #include "migration/vmstate.h"
>
> @@ -212,6 +213,7 @@ static void cmsdk_apb_timer_init(Object *obj)
> s, "cmsdk-apb-timer", 0x1000);
> sysbus_init_mmio(sbd, &s->iomem);
> sysbus_init_irq(sbd, &s->timerint);
> + s->pclk = qdev_init_clock_in(DEVICE(s), "pclk", NULL, NULL);
> }
>
> static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp)
> @@ -236,10 +238,11 @@ static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp)
>
> static const VMStateDescription cmsdk_apb_timer_vmstate = {
> .name = "cmsdk-apb-timer",
> - .version_id = 1,
> - .minimum_version_id = 1,
> + .version_id = 2,
> + .minimum_version_id = 2,
> .fields = (VMStateField[]) {
> VMSTATE_PTIMER(timer, CMSDKAPBTimer),
> + VMSTATE_CLOCK(pclk, CMSDKAPBTimer),
> VMSTATE_UINT32(ctrl, CMSDKAPBTimer),
> VMSTATE_UINT32(value, CMSDKAPBTimer),
> VMSTATE_UINT32(reload, CMSDKAPBTimer),
> --
> 2.20.1
>
--
^ permalink raw reply [flat|nested] 80+ messages in thread
* [PATCH 08/25] hw/timer/cmsdk-apb-dualtimer: Add Clock input
2021-01-21 19:05 [PATCH 00/25] Convert CMSDK timer, watchdog, dualtimer to Clock framework Peter Maydell
` (6 preceding siblings ...)
2021-01-21 19:06 ` [PATCH 07/25] hw/timer/cmsdk-apb-timer: Add Clock input Peter Maydell
@ 2021-01-21 19:06 ` Peter Maydell
2021-01-21 21:49 ` Philippe Mathieu-Daudé
2021-01-22 15:17 ` Luc Michel
2021-01-21 19:06 ` [PATCH 09/25] hw/watchdog/cmsdk-apb-watchdog: " Peter Maydell
` (16 subsequent siblings)
24 siblings, 2 replies; 80+ messages in thread
From: Peter Maydell @ 2021-01-21 19:06 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Philippe Mathieu-Daudé
As the first step in converting the CMSDK_APB_DUALTIMER device to the
Clock framework, add a Clock input. For the moment we do nothing
with this clock; we will change the behaviour from using the pclk-frq
property to using the Clock once all the users of this device have
been converted to wire up the Clock.
We take the opportunity to correct the name of the clock input to
match the hardware -- the dual timer names the clock which drives the
timers TIMCLK. (It does also have a 'pclk' input, which is used only
for the register and APB bus logic; on the SSE-200 these clocks are
both connected together.)
This is a migration compatibility break for machines mps2-an385,
mps2-an386, mps2-an500, mps2-an511, mps2-an505, mps2-an521, musca-a,
musca-b1.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/timer/cmsdk-apb-dualtimer.h | 3 +++
hw/timer/cmsdk-apb-dualtimer.c | 7 +++++--
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/include/hw/timer/cmsdk-apb-dualtimer.h b/include/hw/timer/cmsdk-apb-dualtimer.h
index 08d9e6fa3d5..3adbb01dd34 100644
--- a/include/hw/timer/cmsdk-apb-dualtimer.h
+++ b/include/hw/timer/cmsdk-apb-dualtimer.h
@@ -17,6 +17,7 @@
*
* QEMU interface:
* + QOM property "pclk-frq": frequency at which the timer is clocked
+ * + Clock input "TIMCLK": clock (for both timers)
* + sysbus MMIO region 0: the register bank
* + sysbus IRQ 0: combined timer interrupt TIMINTC
* + sysbus IRO 1: timer block 1 interrupt TIMINT1
@@ -28,6 +29,7 @@
#include "hw/sysbus.h"
#include "hw/ptimer.h"
+#include "hw/clock.h"
#include "qom/object.h"
#define TYPE_CMSDK_APB_DUALTIMER "cmsdk-apb-dualtimer"
@@ -62,6 +64,7 @@ struct CMSDKAPBDualTimer {
MemoryRegion iomem;
qemu_irq timerintc;
uint32_t pclk_frq;
+ Clock *timclk;
CMSDKAPBDualTimerModule timermod[CMSDK_APB_DUALTIMER_NUM_MODULES];
uint32_t timeritcr;
diff --git a/hw/timer/cmsdk-apb-dualtimer.c b/hw/timer/cmsdk-apb-dualtimer.c
index f6534241b94..781b496037b 100644
--- a/hw/timer/cmsdk-apb-dualtimer.c
+++ b/hw/timer/cmsdk-apb-dualtimer.c
@@ -25,6 +25,7 @@
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "hw/registerfields.h"
+#include "hw/qdev-clock.h"
#include "hw/timer/cmsdk-apb-dualtimer.h"
#include "migration/vmstate.h"
@@ -445,6 +446,7 @@ static void cmsdk_apb_dualtimer_init(Object *obj)
for (i = 0; i < ARRAY_SIZE(s->timermod); i++) {
sysbus_init_irq(sbd, &s->timermod[i].timerint);
}
+ s->timclk = qdev_init_clock_in(DEVICE(s), "TIMCLK", NULL, NULL);
}
static void cmsdk_apb_dualtimer_realize(DeviceState *dev, Error **errp)
@@ -485,9 +487,10 @@ static const VMStateDescription cmsdk_dualtimermod_vmstate = {
static const VMStateDescription cmsdk_apb_dualtimer_vmstate = {
.name = "cmsdk-apb-dualtimer",
- .version_id = 1,
- .minimum_version_id = 1,
+ .version_id = 2,
+ .minimum_version_id = 2,
.fields = (VMStateField[]) {
+ VMSTATE_CLOCK(timclk, CMSDKAPBDualTimer),
VMSTATE_STRUCT_ARRAY(timermod, CMSDKAPBDualTimer,
CMSDK_APB_DUALTIMER_NUM_MODULES,
1, cmsdk_dualtimermod_vmstate,
--
2.20.1
^ permalink raw reply related [flat|nested] 80+ messages in thread* Re: [PATCH 08/25] hw/timer/cmsdk-apb-dualtimer: Add Clock input
2021-01-21 19:06 ` [PATCH 08/25] hw/timer/cmsdk-apb-dualtimer: " Peter Maydell
@ 2021-01-21 21:49 ` Philippe Mathieu-Daudé
2021-01-22 15:17 ` Luc Michel
1 sibling, 0 replies; 80+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-21 21:49 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel; +Cc: Damien Hedde, Luc Michel
On 1/21/21 8:06 PM, Peter Maydell wrote:
> As the first step in converting the CMSDK_APB_DUALTIMER device to the
> Clock framework, add a Clock input. For the moment we do nothing
> with this clock; we will change the behaviour from using the pclk-frq
> property to using the Clock once all the users of this device have
> been converted to wire up the Clock.
>
> We take the opportunity to correct the name of the clock input to
> match the hardware -- the dual timer names the clock which drives the
> timers TIMCLK. (It does also have a 'pclk' input, which is used only
> for the register and APB bus logic; on the SSE-200 these clocks are
> both connected together.)
>
> This is a migration compatibility break for machines mps2-an385,
> mps2-an386, mps2-an500, mps2-an511, mps2-an505, mps2-an521, musca-a,
> musca-b1.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> include/hw/timer/cmsdk-apb-dualtimer.h | 3 +++
> hw/timer/cmsdk-apb-dualtimer.c | 7 +++++--
> 2 files changed, 8 insertions(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 08/25] hw/timer/cmsdk-apb-dualtimer: Add Clock input
2021-01-21 19:06 ` [PATCH 08/25] hw/timer/cmsdk-apb-dualtimer: " Peter Maydell
2021-01-21 21:49 ` Philippe Mathieu-Daudé
@ 2021-01-22 15:17 ` Luc Michel
1 sibling, 0 replies; 80+ messages in thread
From: Luc Michel @ 2021-01-22 15:17 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, qemu-arm, qemu-devel, Philippe Mathieu-Daudé
On 19:06 Thu 21 Jan , Peter Maydell wrote:
> As the first step in converting the CMSDK_APB_DUALTIMER device to the
> Clock framework, add a Clock input. For the moment we do nothing
> with this clock; we will change the behaviour from using the pclk-frq
> property to using the Clock once all the users of this device have
> been converted to wire up the Clock.
>
> We take the opportunity to correct the name of the clock input to
> match the hardware -- the dual timer names the clock which drives the
> timers TIMCLK. (It does also have a 'pclk' input, which is used only
> for the register and APB bus logic; on the SSE-200 these clocks are
> both connected together.)
>
> This is a migration compatibility break for machines mps2-an385,
> mps2-an386, mps2-an500, mps2-an511, mps2-an505, mps2-an521, musca-a,
> musca-b1.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
> ---
> include/hw/timer/cmsdk-apb-dualtimer.h | 3 +++
> hw/timer/cmsdk-apb-dualtimer.c | 7 +++++--
> 2 files changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/include/hw/timer/cmsdk-apb-dualtimer.h b/include/hw/timer/cmsdk-apb-dualtimer.h
> index 08d9e6fa3d5..3adbb01dd34 100644
> --- a/include/hw/timer/cmsdk-apb-dualtimer.h
> +++ b/include/hw/timer/cmsdk-apb-dualtimer.h
> @@ -17,6 +17,7 @@
> *
> * QEMU interface:
> * + QOM property "pclk-frq": frequency at which the timer is clocked
> + * + Clock input "TIMCLK": clock (for both timers)
> * + sysbus MMIO region 0: the register bank
> * + sysbus IRQ 0: combined timer interrupt TIMINTC
> * + sysbus IRO 1: timer block 1 interrupt TIMINT1
> @@ -28,6 +29,7 @@
>
> #include "hw/sysbus.h"
> #include "hw/ptimer.h"
> +#include "hw/clock.h"
> #include "qom/object.h"
>
> #define TYPE_CMSDK_APB_DUALTIMER "cmsdk-apb-dualtimer"
> @@ -62,6 +64,7 @@ struct CMSDKAPBDualTimer {
> MemoryRegion iomem;
> qemu_irq timerintc;
> uint32_t pclk_frq;
> + Clock *timclk;
>
> CMSDKAPBDualTimerModule timermod[CMSDK_APB_DUALTIMER_NUM_MODULES];
> uint32_t timeritcr;
> diff --git a/hw/timer/cmsdk-apb-dualtimer.c b/hw/timer/cmsdk-apb-dualtimer.c
> index f6534241b94..781b496037b 100644
> --- a/hw/timer/cmsdk-apb-dualtimer.c
> +++ b/hw/timer/cmsdk-apb-dualtimer.c
> @@ -25,6 +25,7 @@
> #include "hw/irq.h"
> #include "hw/qdev-properties.h"
> #include "hw/registerfields.h"
> +#include "hw/qdev-clock.h"
> #include "hw/timer/cmsdk-apb-dualtimer.h"
> #include "migration/vmstate.h"
>
> @@ -445,6 +446,7 @@ static void cmsdk_apb_dualtimer_init(Object *obj)
> for (i = 0; i < ARRAY_SIZE(s->timermod); i++) {
> sysbus_init_irq(sbd, &s->timermod[i].timerint);
> }
> + s->timclk = qdev_init_clock_in(DEVICE(s), "TIMCLK", NULL, NULL);
> }
>
> static void cmsdk_apb_dualtimer_realize(DeviceState *dev, Error **errp)
> @@ -485,9 +487,10 @@ static const VMStateDescription cmsdk_dualtimermod_vmstate = {
>
> static const VMStateDescription cmsdk_apb_dualtimer_vmstate = {
> .name = "cmsdk-apb-dualtimer",
> - .version_id = 1,
> - .minimum_version_id = 1,
> + .version_id = 2,
> + .minimum_version_id = 2,
> .fields = (VMStateField[]) {
> + VMSTATE_CLOCK(timclk, CMSDKAPBDualTimer),
> VMSTATE_STRUCT_ARRAY(timermod, CMSDKAPBDualTimer,
> CMSDK_APB_DUALTIMER_NUM_MODULES,
> 1, cmsdk_dualtimermod_vmstate,
> --
> 2.20.1
>
--
^ permalink raw reply [flat|nested] 80+ messages in thread
* [PATCH 09/25] hw/watchdog/cmsdk-apb-watchdog: Add Clock input
2021-01-21 19:05 [PATCH 00/25] Convert CMSDK timer, watchdog, dualtimer to Clock framework Peter Maydell
` (7 preceding siblings ...)
2021-01-21 19:06 ` [PATCH 08/25] hw/timer/cmsdk-apb-dualtimer: " Peter Maydell
@ 2021-01-21 19:06 ` Peter Maydell
2021-01-21 20:27 ` Philippe Mathieu-Daudé
2021-01-22 15:18 ` Luc Michel
2021-01-21 19:06 ` [PATCH 10/25] hw/arm/armsse: Rename "MAINCLK" property to "MAINCLK_FRQ" Peter Maydell
` (15 subsequent siblings)
24 siblings, 2 replies; 80+ messages in thread
From: Peter Maydell @ 2021-01-21 19:06 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Philippe Mathieu-Daudé
As the first step in converting the CMSDK_APB_TIMER device to the
Clock framework, add a Clock input. For the moment we do nothing
with this clock; we will change the behaviour from using the
wdogclk-frq property to using the Clock once all the users of this
device have been converted to wire up the Clock.
This is a migration compatibility break for machines mps2-an385,
mps2-an386, mps2-an500, mps2-an511, mps2-an505, mps2-an521, musca-a,
musca-b1, lm3s811evb, lm3s6965evb.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/watchdog/cmsdk-apb-watchdog.h | 3 +++
hw/watchdog/cmsdk-apb-watchdog.c | 7 +++++--
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/include/hw/watchdog/cmsdk-apb-watchdog.h b/include/hw/watchdog/cmsdk-apb-watchdog.h
index 3da0d43e355..34069ca6969 100644
--- a/include/hw/watchdog/cmsdk-apb-watchdog.h
+++ b/include/hw/watchdog/cmsdk-apb-watchdog.h
@@ -17,6 +17,7 @@
*
* QEMU interface:
* + QOM property "wdogclk-frq": frequency at which the watchdog is clocked
+ * + Clock input "WDOGCLK": clock for the watchdog's timer
* + sysbus MMIO region 0: the register bank
* + sysbus IRQ 0: watchdog interrupt
*
@@ -33,6 +34,7 @@
#include "hw/sysbus.h"
#include "hw/ptimer.h"
+#include "hw/clock.h"
#include "qom/object.h"
#define TYPE_CMSDK_APB_WATCHDOG "cmsdk-apb-watchdog"
@@ -54,6 +56,7 @@ struct CMSDKAPBWatchdog {
uint32_t wdogclk_frq;
bool is_luminary;
struct ptimer_state *timer;
+ Clock *wdogclk;
uint32_t control;
uint32_t intstatus;
diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watchdog.c
index 5bbadadfa68..b03bcb73628 100644
--- a/hw/watchdog/cmsdk-apb-watchdog.c
+++ b/hw/watchdog/cmsdk-apb-watchdog.c
@@ -30,6 +30,7 @@
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "hw/registerfields.h"
+#include "hw/qdev-clock.h"
#include "hw/watchdog/cmsdk-apb-watchdog.h"
#include "migration/vmstate.h"
@@ -318,6 +319,7 @@ static void cmsdk_apb_watchdog_init(Object *obj)
s, "cmsdk-apb-watchdog", 0x1000);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->wdogint);
+ s->wdogclk = qdev_init_clock_in(DEVICE(s), "WDOGCLK", NULL, NULL);
s->is_luminary = false;
s->id = cmsdk_apb_watchdog_id;
@@ -346,9 +348,10 @@ static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp)
static const VMStateDescription cmsdk_apb_watchdog_vmstate = {
.name = "cmsdk-apb-watchdog",
- .version_id = 1,
- .minimum_version_id = 1,
+ .version_id = 2,
+ .minimum_version_id = 2,
.fields = (VMStateField[]) {
+ VMSTATE_CLOCK(wdogclk, CMSDKAPBWatchdog),
VMSTATE_PTIMER(timer, CMSDKAPBWatchdog),
VMSTATE_UINT32(control, CMSDKAPBWatchdog),
VMSTATE_UINT32(intstatus, CMSDKAPBWatchdog),
--
2.20.1
^ permalink raw reply related [flat|nested] 80+ messages in thread* Re: [PATCH 09/25] hw/watchdog/cmsdk-apb-watchdog: Add Clock input
2021-01-21 19:06 ` [PATCH 09/25] hw/watchdog/cmsdk-apb-watchdog: " Peter Maydell
@ 2021-01-21 20:27 ` Philippe Mathieu-Daudé
2021-01-22 15:18 ` Luc Michel
1 sibling, 0 replies; 80+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-21 20:27 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel; +Cc: Damien Hedde, Luc Michel
On 1/21/21 8:06 PM, Peter Maydell wrote:
> As the first step in converting the CMSDK_APB_TIMER device to the
> Clock framework, add a Clock input. For the moment we do nothing
> with this clock; we will change the behaviour from using the
> wdogclk-frq property to using the Clock once all the users of this
> device have been converted to wire up the Clock.
>
> This is a migration compatibility break for machines mps2-an385,
> mps2-an386, mps2-an500, mps2-an511, mps2-an505, mps2-an521, musca-a,
> musca-b1, lm3s811evb, lm3s6965evb.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> include/hw/watchdog/cmsdk-apb-watchdog.h | 3 +++
> hw/watchdog/cmsdk-apb-watchdog.c | 7 +++++--
> 2 files changed, 8 insertions(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 09/25] hw/watchdog/cmsdk-apb-watchdog: Add Clock input
2021-01-21 19:06 ` [PATCH 09/25] hw/watchdog/cmsdk-apb-watchdog: " Peter Maydell
2021-01-21 20:27 ` Philippe Mathieu-Daudé
@ 2021-01-22 15:18 ` Luc Michel
1 sibling, 0 replies; 80+ messages in thread
From: Luc Michel @ 2021-01-22 15:18 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, qemu-arm, qemu-devel, Philippe Mathieu-Daudé
On 19:06 Thu 21 Jan , Peter Maydell wrote:
> As the first step in converting the CMSDK_APB_TIMER device to the
> Clock framework, add a Clock input. For the moment we do nothing
> with this clock; we will change the behaviour from using the
> wdogclk-frq property to using the Clock once all the users of this
> device have been converted to wire up the Clock.
>
> This is a migration compatibility break for machines mps2-an385,
> mps2-an386, mps2-an500, mps2-an511, mps2-an505, mps2-an521, musca-a,
> musca-b1, lm3s811evb, lm3s6965evb.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
> ---
> include/hw/watchdog/cmsdk-apb-watchdog.h | 3 +++
> hw/watchdog/cmsdk-apb-watchdog.c | 7 +++++--
> 2 files changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/include/hw/watchdog/cmsdk-apb-watchdog.h b/include/hw/watchdog/cmsdk-apb-watchdog.h
> index 3da0d43e355..34069ca6969 100644
> --- a/include/hw/watchdog/cmsdk-apb-watchdog.h
> +++ b/include/hw/watchdog/cmsdk-apb-watchdog.h
> @@ -17,6 +17,7 @@
> *
> * QEMU interface:
> * + QOM property "wdogclk-frq": frequency at which the watchdog is clocked
> + * + Clock input "WDOGCLK": clock for the watchdog's timer
> * + sysbus MMIO region 0: the register bank
> * + sysbus IRQ 0: watchdog interrupt
> *
> @@ -33,6 +34,7 @@
>
> #include "hw/sysbus.h"
> #include "hw/ptimer.h"
> +#include "hw/clock.h"
> #include "qom/object.h"
>
> #define TYPE_CMSDK_APB_WATCHDOG "cmsdk-apb-watchdog"
> @@ -54,6 +56,7 @@ struct CMSDKAPBWatchdog {
> uint32_t wdogclk_frq;
> bool is_luminary;
> struct ptimer_state *timer;
> + Clock *wdogclk;
>
> uint32_t control;
> uint32_t intstatus;
> diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watchdog.c
> index 5bbadadfa68..b03bcb73628 100644
> --- a/hw/watchdog/cmsdk-apb-watchdog.c
> +++ b/hw/watchdog/cmsdk-apb-watchdog.c
> @@ -30,6 +30,7 @@
> #include "hw/irq.h"
> #include "hw/qdev-properties.h"
> #include "hw/registerfields.h"
> +#include "hw/qdev-clock.h"
> #include "hw/watchdog/cmsdk-apb-watchdog.h"
> #include "migration/vmstate.h"
>
> @@ -318,6 +319,7 @@ static void cmsdk_apb_watchdog_init(Object *obj)
> s, "cmsdk-apb-watchdog", 0x1000);
> sysbus_init_mmio(sbd, &s->iomem);
> sysbus_init_irq(sbd, &s->wdogint);
> + s->wdogclk = qdev_init_clock_in(DEVICE(s), "WDOGCLK", NULL, NULL);
>
> s->is_luminary = false;
> s->id = cmsdk_apb_watchdog_id;
> @@ -346,9 +348,10 @@ static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp)
>
> static const VMStateDescription cmsdk_apb_watchdog_vmstate = {
> .name = "cmsdk-apb-watchdog",
> - .version_id = 1,
> - .minimum_version_id = 1,
> + .version_id = 2,
> + .minimum_version_id = 2,
> .fields = (VMStateField[]) {
> + VMSTATE_CLOCK(wdogclk, CMSDKAPBWatchdog),
> VMSTATE_PTIMER(timer, CMSDKAPBWatchdog),
> VMSTATE_UINT32(control, CMSDKAPBWatchdog),
> VMSTATE_UINT32(intstatus, CMSDKAPBWatchdog),
> --
> 2.20.1
>
--
^ permalink raw reply [flat|nested] 80+ messages in thread
* [PATCH 10/25] hw/arm/armsse: Rename "MAINCLK" property to "MAINCLK_FRQ"
2021-01-21 19:05 [PATCH 00/25] Convert CMSDK timer, watchdog, dualtimer to Clock framework Peter Maydell
` (8 preceding siblings ...)
2021-01-21 19:06 ` [PATCH 09/25] hw/watchdog/cmsdk-apb-watchdog: " Peter Maydell
@ 2021-01-21 19:06 ` Peter Maydell
2021-01-21 20:28 ` Philippe Mathieu-Daudé
2021-01-22 15:22 ` Luc Michel
2021-01-21 19:06 ` [PATCH 11/25] hw/arm/armsse: Wire up clocks Peter Maydell
` (14 subsequent siblings)
24 siblings, 2 replies; 80+ messages in thread
From: Peter Maydell @ 2021-01-21 19:06 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Philippe Mathieu-Daudé
While we transition the ARMSSE code from integer properties
specifying clock frequencies to Clock objects, we want to have the
device provide both at once. We want the final name of the main
input Clock to be "MAINCLK", following the hardware name.
Unfortunately creating an input Clock with a name X creates an
under-the-hood QOM property X; for "MAINCLK" this clashes with the
existing UINT32 property of that name.
Rename the UINT32 property to MAINCLK_FRQ so it can coexist with the
MAINCLK Clock; once the transition is complete MAINCLK_FRQ will be
deleted.
Commit created with:
perl -p -i -e 's/MAINCLK/MAINCLK_FRQ/g' hw/arm/{armsse,mps2-tz,musca}.c include/hw/arm/armsse.h
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/armsse.h | 2 +-
hw/arm/armsse.c | 6 +++---
hw/arm/mps2-tz.c | 2 +-
hw/arm/musca.c | 2 +-
4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
index 83f5e28c16e..4860a793f4b 100644
--- a/include/hw/arm/armsse.h
+++ b/include/hw/arm/armsse.h
@@ -39,7 +39,7 @@
* QEMU interface:
* + QOM property "memory" is a MemoryRegion containing the devices provided
* by the board model.
- * + QOM property "MAINCLK" is the frequency of the main system clock
+ * + QOM property "MAINCLK_FRQ" is the frequency of the main system clock
* + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts.
* (In hardware, the SSE-200 permits the number of expansion interrupts
* for the two CPUs to be configured separately, but we restrict it to
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
index baac027659d..d2ba0459c44 100644
--- a/hw/arm/armsse.c
+++ b/hw/arm/armsse.c
@@ -47,7 +47,7 @@ static Property iotkit_properties[] = {
DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION,
MemoryRegion *),
DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64),
- DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0),
+ DEFINE_PROP_UINT32("MAINCLK_FRQ", ARMSSE, mainclk_frq, 0),
DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15),
DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
@@ -59,7 +59,7 @@ static Property armsse_properties[] = {
DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION,
MemoryRegion *),
DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64),
- DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0),
+ DEFINE_PROP_UINT32("MAINCLK_FRQ", ARMSSE, mainclk_frq, 0),
DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15),
DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false),
@@ -448,7 +448,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
}
if (!s->mainclk_frq) {
- error_setg(errp, "MAINCLK property was not set");
+ error_setg(errp, "MAINCLK_FRQ property was not set");
return;
}
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index 3707876d6d4..6a9eed9022a 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -402,7 +402,7 @@ static void mps2tz_common_init(MachineState *machine)
object_property_set_link(OBJECT(&mms->iotkit), "memory",
OBJECT(system_memory), &error_abort);
qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ);
- qdev_prop_set_uint32(iotkitdev, "MAINCLK", SYSCLK_FRQ);
+ qdev_prop_set_uint32(iotkitdev, "MAINCLK_FRQ", SYSCLK_FRQ);
sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal);
/*
diff --git a/hw/arm/musca.c b/hw/arm/musca.c
index b50157f63a6..d82bef11cf2 100644
--- a/hw/arm/musca.c
+++ b/hw/arm/musca.c
@@ -375,7 +375,7 @@ static void musca_init(MachineState *machine)
qdev_prop_set_uint32(ssedev, "EXP_NUMIRQ", mmc->num_irqs);
qdev_prop_set_uint32(ssedev, "init-svtor", mmc->init_svtor);
qdev_prop_set_uint32(ssedev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width);
- qdev_prop_set_uint32(ssedev, "MAINCLK", SYSCLK_FRQ);
+ qdev_prop_set_uint32(ssedev, "MAINCLK_FRQ", SYSCLK_FRQ);
/*
* Musca-A takes the default SSE-200 FPU/DSP settings (ie no for
* CPU0 and yes for CPU1); Musca-B1 explicitly enables them for CPU0.
--
2.20.1
^ permalink raw reply related [flat|nested] 80+ messages in thread* Re: [PATCH 10/25] hw/arm/armsse: Rename "MAINCLK" property to "MAINCLK_FRQ"
2021-01-21 19:06 ` [PATCH 10/25] hw/arm/armsse: Rename "MAINCLK" property to "MAINCLK_FRQ" Peter Maydell
@ 2021-01-21 20:28 ` Philippe Mathieu-Daudé
2021-01-22 15:22 ` Luc Michel
1 sibling, 0 replies; 80+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-21 20:28 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel; +Cc: Damien Hedde, Luc Michel
On 1/21/21 8:06 PM, Peter Maydell wrote:
> While we transition the ARMSSE code from integer properties
> specifying clock frequencies to Clock objects, we want to have the
> device provide both at once. We want the final name of the main
> input Clock to be "MAINCLK", following the hardware name.
> Unfortunately creating an input Clock with a name X creates an
> under-the-hood QOM property X; for "MAINCLK" this clashes with the
> existing UINT32 property of that name.
>
> Rename the UINT32 property to MAINCLK_FRQ so it can coexist with the
> MAINCLK Clock; once the transition is complete MAINCLK_FRQ will be
> deleted.
>
> Commit created with:
> perl -p -i -e 's/MAINCLK/MAINCLK_FRQ/g' hw/arm/{armsse,mps2-tz,musca}.c include/hw/arm/armsse.h
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> include/hw/arm/armsse.h | 2 +-
> hw/arm/armsse.c | 6 +++---
> hw/arm/mps2-tz.c | 2 +-
> hw/arm/musca.c | 2 +-
> 4 files changed, 6 insertions(+), 6 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 80+ messages in thread* Re: [PATCH 10/25] hw/arm/armsse: Rename "MAINCLK" property to "MAINCLK_FRQ"
2021-01-21 19:06 ` [PATCH 10/25] hw/arm/armsse: Rename "MAINCLK" property to "MAINCLK_FRQ" Peter Maydell
2021-01-21 20:28 ` Philippe Mathieu-Daudé
@ 2021-01-22 15:22 ` Luc Michel
1 sibling, 0 replies; 80+ messages in thread
From: Luc Michel @ 2021-01-22 15:22 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, qemu-arm, qemu-devel, Philippe Mathieu-Daudé
On 19:06 Thu 21 Jan , Peter Maydell wrote:
> While we transition the ARMSSE code from integer properties
> specifying clock frequencies to Clock objects, we want to have the
> device provide both at once. We want the final name of the main
> input Clock to be "MAINCLK", following the hardware name.
> Unfortunately creating an input Clock with a name X creates an
> under-the-hood QOM property X; for "MAINCLK" this clashes with the
> existing UINT32 property of that name.
>
> Rename the UINT32 property to MAINCLK_FRQ so it can coexist with the
> MAINCLK Clock; once the transition is complete MAINCLK_FRQ will be
> deleted.
>
> Commit created with:
> perl -p -i -e 's/MAINCLK/MAINCLK_FRQ/g' hw/arm/{armsse,mps2-tz,musca}.c include/hw/arm/armsse.h
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
> ---
> include/hw/arm/armsse.h | 2 +-
> hw/arm/armsse.c | 6 +++---
> hw/arm/mps2-tz.c | 2 +-
> hw/arm/musca.c | 2 +-
> 4 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
> index 83f5e28c16e..4860a793f4b 100644
> --- a/include/hw/arm/armsse.h
> +++ b/include/hw/arm/armsse.h
> @@ -39,7 +39,7 @@
> * QEMU interface:
> * + QOM property "memory" is a MemoryRegion containing the devices provided
> * by the board model.
> - * + QOM property "MAINCLK" is the frequency of the main system clock
> + * + QOM property "MAINCLK_FRQ" is the frequency of the main system clock
> * + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts.
> * (In hardware, the SSE-200 permits the number of expansion interrupts
> * for the two CPUs to be configured separately, but we restrict it to
> diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
> index baac027659d..d2ba0459c44 100644
> --- a/hw/arm/armsse.c
> +++ b/hw/arm/armsse.c
> @@ -47,7 +47,7 @@ static Property iotkit_properties[] = {
> DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION,
> MemoryRegion *),
> DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64),
> - DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0),
> + DEFINE_PROP_UINT32("MAINCLK_FRQ", ARMSSE, mainclk_frq, 0),
> DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15),
> DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
> DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
> @@ -59,7 +59,7 @@ static Property armsse_properties[] = {
> DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION,
> MemoryRegion *),
> DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64),
> - DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0),
> + DEFINE_PROP_UINT32("MAINCLK_FRQ", ARMSSE, mainclk_frq, 0),
> DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15),
> DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
> DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false),
> @@ -448,7 +448,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
> }
>
> if (!s->mainclk_frq) {
> - error_setg(errp, "MAINCLK property was not set");
> + error_setg(errp, "MAINCLK_FRQ property was not set");
> return;
> }
>
> diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
> index 3707876d6d4..6a9eed9022a 100644
> --- a/hw/arm/mps2-tz.c
> +++ b/hw/arm/mps2-tz.c
> @@ -402,7 +402,7 @@ static void mps2tz_common_init(MachineState *machine)
> object_property_set_link(OBJECT(&mms->iotkit), "memory",
> OBJECT(system_memory), &error_abort);
> qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ);
> - qdev_prop_set_uint32(iotkitdev, "MAINCLK", SYSCLK_FRQ);
> + qdev_prop_set_uint32(iotkitdev, "MAINCLK_FRQ", SYSCLK_FRQ);
> sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal);
>
> /*
> diff --git a/hw/arm/musca.c b/hw/arm/musca.c
> index b50157f63a6..d82bef11cf2 100644
> --- a/hw/arm/musca.c
> +++ b/hw/arm/musca.c
> @@ -375,7 +375,7 @@ static void musca_init(MachineState *machine)
> qdev_prop_set_uint32(ssedev, "EXP_NUMIRQ", mmc->num_irqs);
> qdev_prop_set_uint32(ssedev, "init-svtor", mmc->init_svtor);
> qdev_prop_set_uint32(ssedev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width);
> - qdev_prop_set_uint32(ssedev, "MAINCLK", SYSCLK_FRQ);
> + qdev_prop_set_uint32(ssedev, "MAINCLK_FRQ", SYSCLK_FRQ);
> /*
> * Musca-A takes the default SSE-200 FPU/DSP settings (ie no for
> * CPU0 and yes for CPU1); Musca-B1 explicitly enables them for CPU0.
> --
> 2.20.1
>
--
^ permalink raw reply [flat|nested] 80+ messages in thread
* [PATCH 11/25] hw/arm/armsse: Wire up clocks
2021-01-21 19:05 [PATCH 00/25] Convert CMSDK timer, watchdog, dualtimer to Clock framework Peter Maydell
` (9 preceding siblings ...)
2021-01-21 19:06 ` [PATCH 10/25] hw/arm/armsse: Rename "MAINCLK" property to "MAINCLK_FRQ" Peter Maydell
@ 2021-01-21 19:06 ` Peter Maydell
2021-01-21 20:30 ` Philippe Mathieu-Daudé
2021-01-22 15:34 ` Luc Michel
2021-01-21 19:06 ` [PATCH 12/25] hw/arm/mps2: Inline CMSDK_APB_TIMER creation Peter Maydell
` (13 subsequent siblings)
24 siblings, 2 replies; 80+ messages in thread
From: Peter Maydell @ 2021-01-21 19:06 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Philippe Mathieu-Daudé
Create two input clocks on the ARMSSE devices, one for the normal
MAINCLK, and one for the 32KHz S32KCLK, and wire these up to the
appropriate devices. The old property-based clock frequency setting
will remain in place until conversion is complete.
This is a migration compatibility break for machines mps2-an505,
mps2-an521, musca-a, musca-b1.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/armsse.h | 6 ++++++
hw/arm/armsse.c | 17 +++++++++++++++--
2 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
index 4860a793f4b..bfa1e79c4fe 100644
--- a/include/hw/arm/armsse.h
+++ b/include/hw/arm/armsse.h
@@ -37,6 +37,8 @@
* per-CPU identity and control register blocks
*
* QEMU interface:
+ * + Clock input "MAINCLK": clock for CPUs and most peripherals
+ * + Clock input "S32KCLK": slow 32KHz clock used for a few peripherals
* + QOM property "memory" is a MemoryRegion containing the devices provided
* by the board model.
* + QOM property "MAINCLK_FRQ" is the frequency of the main system clock
@@ -103,6 +105,7 @@
#include "hw/misc/armsse-mhu.h"
#include "hw/misc/unimp.h"
#include "hw/or-irq.h"
+#include "hw/clock.h"
#include "hw/core/split-irq.h"
#include "hw/cpu/cluster.h"
#include "qom/object.h"
@@ -209,6 +212,9 @@ struct ARMSSE {
uint32_t nsccfg;
+ Clock *mainclk;
+ Clock *s32kclk;
+
/* Properties */
MemoryRegion *board_memory;
uint32_t exp_numirq;
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
index d2ba0459c44..4349ce9bfdb 100644
--- a/hw/arm/armsse.c
+++ b/hw/arm/armsse.c
@@ -21,6 +21,7 @@
#include "hw/arm/armsse.h"
#include "hw/arm/boot.h"
#include "hw/irq.h"
+#include "hw/qdev-clock.h"
/* Format of the System Information block SYS_CONFIG register */
typedef enum SysConfigFormat {
@@ -241,6 +242,9 @@ static void armsse_init(Object *obj)
assert(info->sram_banks <= MAX_SRAM_BANKS);
assert(info->num_cpus <= SSE_MAX_CPUS);
+ s->mainclk = qdev_init_clock_in(DEVICE(s), "MAINCLK", NULL, NULL);
+ s->s32kclk = qdev_init_clock_in(DEVICE(s), "S32KCLK", NULL, NULL);
+
memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX);
for (i = 0; i < info->num_cpus; i++) {
@@ -711,6 +715,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
* map its upstream ends to the right place in the container.
*/
qdev_prop_set_uint32(DEVICE(&s->timer0), "pclk-frq", s->mainclk_frq);
+ qdev_connect_clock_in(DEVICE(&s->timer0), "pclk", s->mainclk);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer0), errp)) {
return;
}
@@ -721,6 +726,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
&error_abort);
qdev_prop_set_uint32(DEVICE(&s->timer1), "pclk-frq", s->mainclk_frq);
+ qdev_connect_clock_in(DEVICE(&s->timer1), "pclk", s->mainclk);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer1), errp)) {
return;
}
@@ -731,6 +737,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
&error_abort);
qdev_prop_set_uint32(DEVICE(&s->dualtimer), "pclk-frq", s->mainclk_frq);
+ qdev_connect_clock_in(DEVICE(&s->dualtimer), "TIMCLK", s->mainclk);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->dualtimer), errp)) {
return;
}
@@ -889,6 +896,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
* 0x4002f000: S32K timer
*/
qdev_prop_set_uint32(DEVICE(&s->s32ktimer), "pclk-frq", S32KCLK);
+ qdev_connect_clock_in(DEVICE(&s->s32ktimer), "pclk", s->s32kclk);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32ktimer), errp)) {
return;
}
@@ -982,6 +990,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI", 0));
qdev_prop_set_uint32(DEVICE(&s->s32kwatchdog), "wdogclk-frq", S32KCLK);
+ qdev_connect_clock_in(DEVICE(&s->s32kwatchdog), "WDOGCLK", s->s32kclk);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32kwatchdog), errp)) {
return;
}
@@ -992,6 +1001,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
/* 0x40080000 .. 0x4008ffff : ARMSSE second Base peripheral region */
qdev_prop_set_uint32(DEVICE(&s->nswatchdog), "wdogclk-frq", s->mainclk_frq);
+ qdev_connect_clock_in(DEVICE(&s->nswatchdog), "WDOGCLK", s->mainclk);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->nswatchdog), errp)) {
return;
}
@@ -1000,6 +1010,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->nswatchdog), 0, 0x40081000);
qdev_prop_set_uint32(DEVICE(&s->swatchdog), "wdogclk-frq", s->mainclk_frq);
+ qdev_connect_clock_in(DEVICE(&s->swatchdog), "WDOGCLK", s->mainclk);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->swatchdog), errp)) {
return;
}
@@ -1127,9 +1138,11 @@ static void armsse_idau_check(IDAUInterface *ii, uint32_t address,
static const VMStateDescription armsse_vmstate = {
.name = "iotkit",
- .version_id = 1,
- .minimum_version_id = 1,
+ .version_id = 2,
+ .minimum_version_id = 2,
.fields = (VMStateField[]) {
+ VMSTATE_CLOCK(mainclk, ARMSSE),
+ VMSTATE_CLOCK(s32kclk, ARMSSE),
VMSTATE_UINT32(nsccfg, ARMSSE),
VMSTATE_END_OF_LIST()
}
--
2.20.1
^ permalink raw reply related [flat|nested] 80+ messages in thread* Re: [PATCH 11/25] hw/arm/armsse: Wire up clocks
2021-01-21 19:06 ` [PATCH 11/25] hw/arm/armsse: Wire up clocks Peter Maydell
@ 2021-01-21 20:30 ` Philippe Mathieu-Daudé
2021-01-22 15:34 ` Luc Michel
1 sibling, 0 replies; 80+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-21 20:30 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel; +Cc: Damien Hedde, Luc Michel
On 1/21/21 8:06 PM, Peter Maydell wrote:
> Create two input clocks on the ARMSSE devices, one for the normal
> MAINCLK, and one for the 32KHz S32KCLK, and wire these up to the
> appropriate devices. The old property-based clock frequency setting
> will remain in place until conversion is complete.
>
> This is a migration compatibility break for machines mps2-an505,
> mps2-an521, musca-a, musca-b1.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> include/hw/arm/armsse.h | 6 ++++++
> hw/arm/armsse.c | 17 +++++++++++++++--
> 2 files changed, 21 insertions(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 11/25] hw/arm/armsse: Wire up clocks
2021-01-21 19:06 ` [PATCH 11/25] hw/arm/armsse: Wire up clocks Peter Maydell
2021-01-21 20:30 ` Philippe Mathieu-Daudé
@ 2021-01-22 15:34 ` Luc Michel
1 sibling, 0 replies; 80+ messages in thread
From: Luc Michel @ 2021-01-22 15:34 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, qemu-arm, qemu-devel, Philippe Mathieu-Daudé
On 19:06 Thu 21 Jan , Peter Maydell wrote:
> Create two input clocks on the ARMSSE devices, one for the normal
> MAINCLK, and one for the 32KHz S32KCLK, and wire these up to the
> appropriate devices. The old property-based clock frequency setting
> will remain in place until conversion is complete.
>
> This is a migration compatibility break for machines mps2-an505,
> mps2-an521, musca-a, musca-b1.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
> ---
> include/hw/arm/armsse.h | 6 ++++++
> hw/arm/armsse.c | 17 +++++++++++++++--
> 2 files changed, 21 insertions(+), 2 deletions(-)
>
> diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
> index 4860a793f4b..bfa1e79c4fe 100644
> --- a/include/hw/arm/armsse.h
> +++ b/include/hw/arm/armsse.h
> @@ -37,6 +37,8 @@
> * per-CPU identity and control register blocks
> *
> * QEMU interface:
> + * + Clock input "MAINCLK": clock for CPUs and most peripherals
> + * + Clock input "S32KCLK": slow 32KHz clock used for a few peripherals
> * + QOM property "memory" is a MemoryRegion containing the devices provided
> * by the board model.
> * + QOM property "MAINCLK_FRQ" is the frequency of the main system clock
> @@ -103,6 +105,7 @@
> #include "hw/misc/armsse-mhu.h"
> #include "hw/misc/unimp.h"
> #include "hw/or-irq.h"
> +#include "hw/clock.h"
> #include "hw/core/split-irq.h"
> #include "hw/cpu/cluster.h"
> #include "qom/object.h"
> @@ -209,6 +212,9 @@ struct ARMSSE {
>
> uint32_t nsccfg;
>
> + Clock *mainclk;
> + Clock *s32kclk;
> +
> /* Properties */
> MemoryRegion *board_memory;
> uint32_t exp_numirq;
> diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
> index d2ba0459c44..4349ce9bfdb 100644
> --- a/hw/arm/armsse.c
> +++ b/hw/arm/armsse.c
> @@ -21,6 +21,7 @@
> #include "hw/arm/armsse.h"
> #include "hw/arm/boot.h"
> #include "hw/irq.h"
> +#include "hw/qdev-clock.h"
>
> /* Format of the System Information block SYS_CONFIG register */
> typedef enum SysConfigFormat {
> @@ -241,6 +242,9 @@ static void armsse_init(Object *obj)
> assert(info->sram_banks <= MAX_SRAM_BANKS);
> assert(info->num_cpus <= SSE_MAX_CPUS);
>
> + s->mainclk = qdev_init_clock_in(DEVICE(s), "MAINCLK", NULL, NULL);
> + s->s32kclk = qdev_init_clock_in(DEVICE(s), "S32KCLK", NULL, NULL);
> +
> memory_region_init(&s->container, obj, "armsse-container", UINT64_MAX);
>
> for (i = 0; i < info->num_cpus; i++) {
> @@ -711,6 +715,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
> * map its upstream ends to the right place in the container.
> */
> qdev_prop_set_uint32(DEVICE(&s->timer0), "pclk-frq", s->mainclk_frq);
> + qdev_connect_clock_in(DEVICE(&s->timer0), "pclk", s->mainclk);
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer0), errp)) {
> return;
> }
> @@ -721,6 +726,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
> &error_abort);
>
> qdev_prop_set_uint32(DEVICE(&s->timer1), "pclk-frq", s->mainclk_frq);
> + qdev_connect_clock_in(DEVICE(&s->timer1), "pclk", s->mainclk);
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer1), errp)) {
> return;
> }
> @@ -731,6 +737,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
> &error_abort);
>
> qdev_prop_set_uint32(DEVICE(&s->dualtimer), "pclk-frq", s->mainclk_frq);
> + qdev_connect_clock_in(DEVICE(&s->dualtimer), "TIMCLK", s->mainclk);
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->dualtimer), errp)) {
> return;
> }
> @@ -889,6 +896,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
> * 0x4002f000: S32K timer
> */
> qdev_prop_set_uint32(DEVICE(&s->s32ktimer), "pclk-frq", S32KCLK);
> + qdev_connect_clock_in(DEVICE(&s->s32ktimer), "pclk", s->s32kclk);
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32ktimer), errp)) {
> return;
> }
> @@ -982,6 +990,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
> qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI", 0));
>
> qdev_prop_set_uint32(DEVICE(&s->s32kwatchdog), "wdogclk-frq", S32KCLK);
> + qdev_connect_clock_in(DEVICE(&s->s32kwatchdog), "WDOGCLK", s->s32kclk);
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32kwatchdog), errp)) {
> return;
> }
> @@ -992,6 +1001,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
> /* 0x40080000 .. 0x4008ffff : ARMSSE second Base peripheral region */
>
> qdev_prop_set_uint32(DEVICE(&s->nswatchdog), "wdogclk-frq", s->mainclk_frq);
> + qdev_connect_clock_in(DEVICE(&s->nswatchdog), "WDOGCLK", s->mainclk);
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->nswatchdog), errp)) {
> return;
> }
> @@ -1000,6 +1010,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
> sysbus_mmio_map(SYS_BUS_DEVICE(&s->nswatchdog), 0, 0x40081000);
>
> qdev_prop_set_uint32(DEVICE(&s->swatchdog), "wdogclk-frq", s->mainclk_frq);
> + qdev_connect_clock_in(DEVICE(&s->swatchdog), "WDOGCLK", s->mainclk);
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->swatchdog), errp)) {
> return;
> }
> @@ -1127,9 +1138,11 @@ static void armsse_idau_check(IDAUInterface *ii, uint32_t address,
>
> static const VMStateDescription armsse_vmstate = {
> .name = "iotkit",
> - .version_id = 1,
> - .minimum_version_id = 1,
> + .version_id = 2,
> + .minimum_version_id = 2,
> .fields = (VMStateField[]) {
> + VMSTATE_CLOCK(mainclk, ARMSSE),
> + VMSTATE_CLOCK(s32kclk, ARMSSE),
> VMSTATE_UINT32(nsccfg, ARMSSE),
> VMSTATE_END_OF_LIST()
> }
> --
> 2.20.1
>
--
^ permalink raw reply [flat|nested] 80+ messages in thread
* [PATCH 12/25] hw/arm/mps2: Inline CMSDK_APB_TIMER creation
2021-01-21 19:05 [PATCH 00/25] Convert CMSDK timer, watchdog, dualtimer to Clock framework Peter Maydell
` (10 preceding siblings ...)
2021-01-21 19:06 ` [PATCH 11/25] hw/arm/armsse: Wire up clocks Peter Maydell
@ 2021-01-21 19:06 ` Peter Maydell
2021-01-21 22:14 ` Philippe Mathieu-Daudé
2021-01-22 15:33 ` Luc Michel
2021-01-21 19:06 ` [PATCH 13/25] hw/arm/mps2: Create and connect SYSCLK Clock Peter Maydell
` (12 subsequent siblings)
24 siblings, 2 replies; 80+ messages in thread
From: Peter Maydell @ 2021-01-21 19:06 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Philippe Mathieu-Daudé
The old-style convenience function cmsdk_apb_timer_create() for
creating CMSDK_APB_TIMER objects is used in only two places in
mps2.c. Most of the rest of the code in that file uses the new
"initialize in place" coding style.
We want to connect up a Clock object which should be done between the
object creation and realization; rather than adding a Clock* argument
to the convenience function, convert the timer creation code in
mps2.c to the same style as is used already for the watchdog,
dualtimer and other devices, and delete the now-unused convenience
function.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/timer/cmsdk-apb-timer.h | 21 ---------------------
hw/arm/mps2.c | 18 ++++++++++++++++--
2 files changed, 16 insertions(+), 23 deletions(-)
diff --git a/include/hw/timer/cmsdk-apb-timer.h b/include/hw/timer/cmsdk-apb-timer.h
index fc2aa97acac..54f7ec8c502 100644
--- a/include/hw/timer/cmsdk-apb-timer.h
+++ b/include/hw/timer/cmsdk-apb-timer.h
@@ -45,25 +45,4 @@ struct CMSDKAPBTimer {
uint32_t intstatus;
};
-/**
- * cmsdk_apb_timer_create - convenience function to create TYPE_CMSDK_APB_TIMER
- * @addr: location in system memory to map registers
- * @pclk_frq: frequency in Hz of the PCLK clock (used for calculating baud rate)
- */
-static inline DeviceState *cmsdk_apb_timer_create(hwaddr addr,
- qemu_irq timerint,
- uint32_t pclk_frq)
-{
- DeviceState *dev;
- SysBusDevice *s;
-
- dev = qdev_new(TYPE_CMSDK_APB_TIMER);
- s = SYS_BUS_DEVICE(dev);
- qdev_prop_set_uint32(dev, "pclk-frq", pclk_frq);
- sysbus_realize_and_unref(s, &error_fatal);
- sysbus_mmio_map(s, 0, addr);
- sysbus_connect_irq(s, 0, timerint);
- return dev;
-}
-
#endif
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index 9a8b23c64ce..f762d1b46af 100644
--- a/hw/arm/mps2.c
+++ b/hw/arm/mps2.c
@@ -83,6 +83,7 @@ struct MPS2MachineState {
/* CMSDK APB subsystem */
CMSDKAPBDualTimer dualtimer;
CMSDKAPBWatchdog watchdog;
+ CMSDKAPBTimer timer[2];
};
#define TYPE_MPS2_MACHINE "mps2"
@@ -330,8 +331,21 @@ static void mps2_common_init(MachineState *machine)
}
/* CMSDK APB subsystem */
- cmsdk_apb_timer_create(0x40000000, qdev_get_gpio_in(armv7m, 8), SYSCLK_FRQ);
- cmsdk_apb_timer_create(0x40001000, qdev_get_gpio_in(armv7m, 9), SYSCLK_FRQ);
+ for (i = 0; i < ARRAY_SIZE(mms->timer); i++) {
+ g_autofree char *name = g_strdup_printf("timer%d", i);
+ hwaddr base = 0x40000000 + i * 0x1000;
+ int irqno = 8 + i;
+ SysBusDevice *sbd;
+
+ object_initialize_child(OBJECT(mms), name, &mms->timer[i],
+ TYPE_CMSDK_APB_TIMER);
+ sbd = SYS_BUS_DEVICE(&mms->timer[i]);
+ qdev_prop_set_uint32(DEVICE(&mms->timer[i]), "pclk-frq", SYSCLK_FRQ);
+ sysbus_realize_and_unref(sbd, &error_fatal);
+ sysbus_mmio_map(sbd, 0, base);
+ sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(armv7m, irqno));
+ }
+
object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer,
TYPE_CMSDK_APB_DUALTIMER);
qdev_prop_set_uint32(DEVICE(&mms->dualtimer), "pclk-frq", SYSCLK_FRQ);
--
2.20.1
^ permalink raw reply related [flat|nested] 80+ messages in thread* Re: [PATCH 12/25] hw/arm/mps2: Inline CMSDK_APB_TIMER creation
2021-01-21 19:06 ` [PATCH 12/25] hw/arm/mps2: Inline CMSDK_APB_TIMER creation Peter Maydell
@ 2021-01-21 22:14 ` Philippe Mathieu-Daudé
2021-01-22 15:33 ` Luc Michel
1 sibling, 0 replies; 80+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-21 22:14 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel; +Cc: Damien Hedde, Luc Michel
On 1/21/21 8:06 PM, Peter Maydell wrote:
> The old-style convenience function cmsdk_apb_timer_create() for
> creating CMSDK_APB_TIMER objects is used in only two places in
> mps2.c. Most of the rest of the code in that file uses the new
> "initialize in place" coding style.
>
> We want to connect up a Clock object which should be done between the
> object creation and realization; rather than adding a Clock* argument
> to the convenience function, convert the timer creation code in
> mps2.c to the same style as is used already for the watchdog,
> dualtimer and other devices, and delete the now-unused convenience
> function.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> include/hw/timer/cmsdk-apb-timer.h | 21 ---------------------
> hw/arm/mps2.c | 18 ++++++++++++++++--
> 2 files changed, 16 insertions(+), 23 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 12/25] hw/arm/mps2: Inline CMSDK_APB_TIMER creation
2021-01-21 19:06 ` [PATCH 12/25] hw/arm/mps2: Inline CMSDK_APB_TIMER creation Peter Maydell
2021-01-21 22:14 ` Philippe Mathieu-Daudé
@ 2021-01-22 15:33 ` Luc Michel
1 sibling, 0 replies; 80+ messages in thread
From: Luc Michel @ 2021-01-22 15:33 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, qemu-arm, qemu-devel, Philippe Mathieu-Daudé
On 19:06 Thu 21 Jan , Peter Maydell wrote:
> The old-style convenience function cmsdk_apb_timer_create() for
> creating CMSDK_APB_TIMER objects is used in only two places in
> mps2.c. Most of the rest of the code in that file uses the new
> "initialize in place" coding style.
>
> We want to connect up a Clock object which should be done between the
> object creation and realization; rather than adding a Clock* argument
> to the convenience function, convert the timer creation code in
> mps2.c to the same style as is used already for the watchdog,
> dualtimer and other devices, and delete the now-unused convenience
> function.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
> ---
> include/hw/timer/cmsdk-apb-timer.h | 21 ---------------------
> hw/arm/mps2.c | 18 ++++++++++++++++--
> 2 files changed, 16 insertions(+), 23 deletions(-)
>
> diff --git a/include/hw/timer/cmsdk-apb-timer.h b/include/hw/timer/cmsdk-apb-timer.h
> index fc2aa97acac..54f7ec8c502 100644
> --- a/include/hw/timer/cmsdk-apb-timer.h
> +++ b/include/hw/timer/cmsdk-apb-timer.h
> @@ -45,25 +45,4 @@ struct CMSDKAPBTimer {
> uint32_t intstatus;
> };
>
> -/**
> - * cmsdk_apb_timer_create - convenience function to create TYPE_CMSDK_APB_TIMER
> - * @addr: location in system memory to map registers
> - * @pclk_frq: frequency in Hz of the PCLK clock (used for calculating baud rate)
> - */
> -static inline DeviceState *cmsdk_apb_timer_create(hwaddr addr,
> - qemu_irq timerint,
> - uint32_t pclk_frq)
> -{
> - DeviceState *dev;
> - SysBusDevice *s;
> -
> - dev = qdev_new(TYPE_CMSDK_APB_TIMER);
> - s = SYS_BUS_DEVICE(dev);
> - qdev_prop_set_uint32(dev, "pclk-frq", pclk_frq);
> - sysbus_realize_and_unref(s, &error_fatal);
> - sysbus_mmio_map(s, 0, addr);
> - sysbus_connect_irq(s, 0, timerint);
> - return dev;
> -}
> -
> #endif
> diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
> index 9a8b23c64ce..f762d1b46af 100644
> --- a/hw/arm/mps2.c
> +++ b/hw/arm/mps2.c
> @@ -83,6 +83,7 @@ struct MPS2MachineState {
> /* CMSDK APB subsystem */
> CMSDKAPBDualTimer dualtimer;
> CMSDKAPBWatchdog watchdog;
> + CMSDKAPBTimer timer[2];
> };
>
> #define TYPE_MPS2_MACHINE "mps2"
> @@ -330,8 +331,21 @@ static void mps2_common_init(MachineState *machine)
> }
>
> /* CMSDK APB subsystem */
> - cmsdk_apb_timer_create(0x40000000, qdev_get_gpio_in(armv7m, 8), SYSCLK_FRQ);
> - cmsdk_apb_timer_create(0x40001000, qdev_get_gpio_in(armv7m, 9), SYSCLK_FRQ);
> + for (i = 0; i < ARRAY_SIZE(mms->timer); i++) {
> + g_autofree char *name = g_strdup_printf("timer%d", i);
> + hwaddr base = 0x40000000 + i * 0x1000;
> + int irqno = 8 + i;
> + SysBusDevice *sbd;
> +
> + object_initialize_child(OBJECT(mms), name, &mms->timer[i],
> + TYPE_CMSDK_APB_TIMER);
> + sbd = SYS_BUS_DEVICE(&mms->timer[i]);
> + qdev_prop_set_uint32(DEVICE(&mms->timer[i]), "pclk-frq", SYSCLK_FRQ);
> + sysbus_realize_and_unref(sbd, &error_fatal);
> + sysbus_mmio_map(sbd, 0, base);
> + sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(armv7m, irqno));
> + }
> +
> object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer,
> TYPE_CMSDK_APB_DUALTIMER);
> qdev_prop_set_uint32(DEVICE(&mms->dualtimer), "pclk-frq", SYSCLK_FRQ);
> --
> 2.20.1
>
--
^ permalink raw reply [flat|nested] 80+ messages in thread
* [PATCH 13/25] hw/arm/mps2: Create and connect SYSCLK Clock
2021-01-21 19:05 [PATCH 00/25] Convert CMSDK timer, watchdog, dualtimer to Clock framework Peter Maydell
` (11 preceding siblings ...)
2021-01-21 19:06 ` [PATCH 12/25] hw/arm/mps2: Inline CMSDK_APB_TIMER creation Peter Maydell
@ 2021-01-21 19:06 ` Peter Maydell
2021-01-21 21:24 ` Philippe Mathieu-Daudé
2021-01-22 19:52 ` Luc Michel
2021-01-21 19:06 ` [PATCH 14/25] hw/arm/mps2-tz: Create and connect ARMSSE Clocks Peter Maydell
` (11 subsequent siblings)
24 siblings, 2 replies; 80+ messages in thread
From: Peter Maydell @ 2021-01-21 19:06 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Philippe Mathieu-Daudé
Create a fixed-frequency Clock object to be the SYSCLK, and wire it
up to the devices that require it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/mps2.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index f762d1b46af..cd1c215f941 100644
--- a/hw/arm/mps2.c
+++ b/hw/arm/mps2.c
@@ -46,6 +46,7 @@
#include "hw/net/lan9118.h"
#include "net/net.h"
#include "hw/watchdog/cmsdk-apb-watchdog.h"
+#include "hw/qdev-clock.h"
#include "qom/object.h"
typedef enum MPS2FPGAType {
@@ -84,6 +85,7 @@ struct MPS2MachineState {
CMSDKAPBDualTimer dualtimer;
CMSDKAPBWatchdog watchdog;
CMSDKAPBTimer timer[2];
+ Clock *sysclk;
};
#define TYPE_MPS2_MACHINE "mps2"
@@ -140,6 +142,10 @@ static void mps2_common_init(MachineState *machine)
exit(EXIT_FAILURE);
}
+ /* This clock doesn't need migration because it is fixed-frequency */
+ mms->sysclk = clock_new(OBJECT(machine), "SYSCLK");
+ clock_set_hz(mms->sysclk, SYSCLK_FRQ);
+
/* The FPGA images have an odd combination of different RAMs,
* because in hardware they are different implementations and
* connected to different buses, giving varying performance/size
@@ -341,6 +347,7 @@ static void mps2_common_init(MachineState *machine)
TYPE_CMSDK_APB_TIMER);
sbd = SYS_BUS_DEVICE(&mms->timer[i]);
qdev_prop_set_uint32(DEVICE(&mms->timer[i]), "pclk-frq", SYSCLK_FRQ);
+ qdev_connect_clock_in(DEVICE(&mms->timer[i]), "pclk", mms->sysclk);
sysbus_realize_and_unref(sbd, &error_fatal);
sysbus_mmio_map(sbd, 0, base);
sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(armv7m, irqno));
@@ -349,6 +356,7 @@ static void mps2_common_init(MachineState *machine)
object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer,
TYPE_CMSDK_APB_DUALTIMER);
qdev_prop_set_uint32(DEVICE(&mms->dualtimer), "pclk-frq", SYSCLK_FRQ);
+ qdev_connect_clock_in(DEVICE(&mms->dualtimer), "TIMCLK", mms->sysclk);
sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal);
sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0,
qdev_get_gpio_in(armv7m, 10));
@@ -356,6 +364,7 @@ static void mps2_common_init(MachineState *machine)
object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog,
TYPE_CMSDK_APB_WATCHDOG);
qdev_prop_set_uint32(DEVICE(&mms->watchdog), "wdogclk-frq", SYSCLK_FRQ);
+ qdev_connect_clock_in(DEVICE(&mms->watchdog), "WDOGCLK", mms->sysclk);
sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal);
sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0,
qdev_get_gpio_in_named(armv7m, "NMI", 0));
--
2.20.1
^ permalink raw reply related [flat|nested] 80+ messages in thread* Re: [PATCH 13/25] hw/arm/mps2: Create and connect SYSCLK Clock
2021-01-21 19:06 ` [PATCH 13/25] hw/arm/mps2: Create and connect SYSCLK Clock Peter Maydell
@ 2021-01-21 21:24 ` Philippe Mathieu-Daudé
2021-01-22 19:52 ` Luc Michel
1 sibling, 0 replies; 80+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-21 21:24 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel; +Cc: Damien Hedde, Luc Michel
On 1/21/21 8:06 PM, Peter Maydell wrote:
> Create a fixed-frequency Clock object to be the SYSCLK, and wire it
> up to the devices that require it.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> hw/arm/mps2.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 13/25] hw/arm/mps2: Create and connect SYSCLK Clock
2021-01-21 19:06 ` [PATCH 13/25] hw/arm/mps2: Create and connect SYSCLK Clock Peter Maydell
2021-01-21 21:24 ` Philippe Mathieu-Daudé
@ 2021-01-22 19:52 ` Luc Michel
1 sibling, 0 replies; 80+ messages in thread
From: Luc Michel @ 2021-01-22 19:52 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, qemu-arm, qemu-devel, Philippe Mathieu-Daudé
On 19:06 Thu 21 Jan , Peter Maydell wrote:
> Create a fixed-frequency Clock object to be the SYSCLK, and wire it
> up to the devices that require it.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
> ---
> hw/arm/mps2.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
> index f762d1b46af..cd1c215f941 100644
> --- a/hw/arm/mps2.c
> +++ b/hw/arm/mps2.c
> @@ -46,6 +46,7 @@
> #include "hw/net/lan9118.h"
> #include "net/net.h"
> #include "hw/watchdog/cmsdk-apb-watchdog.h"
> +#include "hw/qdev-clock.h"
> #include "qom/object.h"
>
> typedef enum MPS2FPGAType {
> @@ -84,6 +85,7 @@ struct MPS2MachineState {
> CMSDKAPBDualTimer dualtimer;
> CMSDKAPBWatchdog watchdog;
> CMSDKAPBTimer timer[2];
> + Clock *sysclk;
> };
>
> #define TYPE_MPS2_MACHINE "mps2"
> @@ -140,6 +142,10 @@ static void mps2_common_init(MachineState *machine)
> exit(EXIT_FAILURE);
> }
>
> + /* This clock doesn't need migration because it is fixed-frequency */
> + mms->sysclk = clock_new(OBJECT(machine), "SYSCLK");
> + clock_set_hz(mms->sysclk, SYSCLK_FRQ);
> +
> /* The FPGA images have an odd combination of different RAMs,
> * because in hardware they are different implementations and
> * connected to different buses, giving varying performance/size
> @@ -341,6 +347,7 @@ static void mps2_common_init(MachineState *machine)
> TYPE_CMSDK_APB_TIMER);
> sbd = SYS_BUS_DEVICE(&mms->timer[i]);
> qdev_prop_set_uint32(DEVICE(&mms->timer[i]), "pclk-frq", SYSCLK_FRQ);
> + qdev_connect_clock_in(DEVICE(&mms->timer[i]), "pclk", mms->sysclk);
> sysbus_realize_and_unref(sbd, &error_fatal);
> sysbus_mmio_map(sbd, 0, base);
> sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(armv7m, irqno));
> @@ -349,6 +356,7 @@ static void mps2_common_init(MachineState *machine)
> object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer,
> TYPE_CMSDK_APB_DUALTIMER);
> qdev_prop_set_uint32(DEVICE(&mms->dualtimer), "pclk-frq", SYSCLK_FRQ);
> + qdev_connect_clock_in(DEVICE(&mms->dualtimer), "TIMCLK", mms->sysclk);
> sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal);
> sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0,
> qdev_get_gpio_in(armv7m, 10));
> @@ -356,6 +364,7 @@ static void mps2_common_init(MachineState *machine)
> object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog,
> TYPE_CMSDK_APB_WATCHDOG);
> qdev_prop_set_uint32(DEVICE(&mms->watchdog), "wdogclk-frq", SYSCLK_FRQ);
> + qdev_connect_clock_in(DEVICE(&mms->watchdog), "WDOGCLK", mms->sysclk);
> sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal);
> sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0,
> qdev_get_gpio_in_named(armv7m, "NMI", 0));
> --
> 2.20.1
>
--
^ permalink raw reply [flat|nested] 80+ messages in thread
* [PATCH 14/25] hw/arm/mps2-tz: Create and connect ARMSSE Clocks
2021-01-21 19:05 [PATCH 00/25] Convert CMSDK timer, watchdog, dualtimer to Clock framework Peter Maydell
` (12 preceding siblings ...)
2021-01-21 19:06 ` [PATCH 13/25] hw/arm/mps2: Create and connect SYSCLK Clock Peter Maydell
@ 2021-01-21 19:06 ` Peter Maydell
2021-01-21 21:30 ` Philippe Mathieu-Daudé
2021-01-22 19:52 ` Luc Michel
2021-01-21 19:06 ` [PATCH 15/25] hw/arm/musca: " Peter Maydell
` (10 subsequent siblings)
24 siblings, 2 replies; 80+ messages in thread
From: Peter Maydell @ 2021-01-21 19:06 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Philippe Mathieu-Daudé
Create and connect the two clocks needed by the ARMSSE.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/mps2-tz.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index 6a9eed9022a..7acdf490f28 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -62,6 +62,7 @@
#include "hw/net/lan9118.h"
#include "net/net.h"
#include "hw/core/split-irq.h"
+#include "hw/qdev-clock.h"
#include "qom/object.h"
#define MPS2TZ_NUMIRQ 92
@@ -100,6 +101,8 @@ struct MPS2TZMachineState {
qemu_or_irq uart_irq_orgate;
DeviceState *lan9118;
SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ];
+ Clock *sysclk;
+ Clock *s32kclk;
};
#define TYPE_MPS2TZ_MACHINE "mps2tz"
@@ -110,6 +113,8 @@ OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE)
/* Main SYSCLK frequency in Hz */
#define SYSCLK_FRQ 20000000
+/* Slow 32Khz S32KCLK frequency in Hz */
+#define S32KCLK_FRQ (32 * 1000)
/* Create an alias of an entire original MemoryRegion @orig
* located at @base in the memory map.
@@ -396,6 +401,12 @@ static void mps2tz_common_init(MachineState *machine)
exit(EXIT_FAILURE);
}
+ /* These clocks don't need migration because they are fixed-frequency */
+ mms->sysclk = clock_new(OBJECT(machine), "SYSCLK");
+ clock_set_hz(mms->sysclk, SYSCLK_FRQ);
+ mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK");
+ clock_set_hz(mms->s32kclk, S32KCLK_FRQ);
+
object_initialize_child(OBJECT(machine), TYPE_IOTKIT, &mms->iotkit,
mmc->armsse_type);
iotkitdev = DEVICE(&mms->iotkit);
@@ -403,6 +414,8 @@ static void mps2tz_common_init(MachineState *machine)
OBJECT(system_memory), &error_abort);
qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ);
qdev_prop_set_uint32(iotkitdev, "MAINCLK_FRQ", SYSCLK_FRQ);
+ qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk);
+ qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk);
sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal);
/*
--
2.20.1
^ permalink raw reply related [flat|nested] 80+ messages in thread* Re: [PATCH 14/25] hw/arm/mps2-tz: Create and connect ARMSSE Clocks
2021-01-21 19:06 ` [PATCH 14/25] hw/arm/mps2-tz: Create and connect ARMSSE Clocks Peter Maydell
@ 2021-01-21 21:30 ` Philippe Mathieu-Daudé
2021-01-22 19:52 ` Luc Michel
1 sibling, 0 replies; 80+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-21 21:30 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel; +Cc: Damien Hedde, Luc Michel
On 1/21/21 8:06 PM, Peter Maydell wrote:
> Create and connect the two clocks needed by the ARMSSE.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> hw/arm/mps2-tz.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 14/25] hw/arm/mps2-tz: Create and connect ARMSSE Clocks
2021-01-21 19:06 ` [PATCH 14/25] hw/arm/mps2-tz: Create and connect ARMSSE Clocks Peter Maydell
2021-01-21 21:30 ` Philippe Mathieu-Daudé
@ 2021-01-22 19:52 ` Luc Michel
1 sibling, 0 replies; 80+ messages in thread
From: Luc Michel @ 2021-01-22 19:52 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, qemu-arm, qemu-devel, Philippe Mathieu-Daudé
On 19:06 Thu 21 Jan , Peter Maydell wrote:
> Create and connect the two clocks needed by the ARMSSE.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
> ---
> hw/arm/mps2-tz.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
> index 6a9eed9022a..7acdf490f28 100644
> --- a/hw/arm/mps2-tz.c
> +++ b/hw/arm/mps2-tz.c
> @@ -62,6 +62,7 @@
> #include "hw/net/lan9118.h"
> #include "net/net.h"
> #include "hw/core/split-irq.h"
> +#include "hw/qdev-clock.h"
> #include "qom/object.h"
>
> #define MPS2TZ_NUMIRQ 92
> @@ -100,6 +101,8 @@ struct MPS2TZMachineState {
> qemu_or_irq uart_irq_orgate;
> DeviceState *lan9118;
> SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ];
> + Clock *sysclk;
> + Clock *s32kclk;
> };
>
> #define TYPE_MPS2TZ_MACHINE "mps2tz"
> @@ -110,6 +113,8 @@ OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE)
>
> /* Main SYSCLK frequency in Hz */
> #define SYSCLK_FRQ 20000000
> +/* Slow 32Khz S32KCLK frequency in Hz */
> +#define S32KCLK_FRQ (32 * 1000)
>
> /* Create an alias of an entire original MemoryRegion @orig
> * located at @base in the memory map.
> @@ -396,6 +401,12 @@ static void mps2tz_common_init(MachineState *machine)
> exit(EXIT_FAILURE);
> }
>
> + /* These clocks don't need migration because they are fixed-frequency */
> + mms->sysclk = clock_new(OBJECT(machine), "SYSCLK");
> + clock_set_hz(mms->sysclk, SYSCLK_FRQ);
> + mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK");
> + clock_set_hz(mms->s32kclk, S32KCLK_FRQ);
> +
> object_initialize_child(OBJECT(machine), TYPE_IOTKIT, &mms->iotkit,
> mmc->armsse_type);
> iotkitdev = DEVICE(&mms->iotkit);
> @@ -403,6 +414,8 @@ static void mps2tz_common_init(MachineState *machine)
> OBJECT(system_memory), &error_abort);
> qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ);
> qdev_prop_set_uint32(iotkitdev, "MAINCLK_FRQ", SYSCLK_FRQ);
> + qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk);
> + qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk);
> sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal);
>
> /*
> --
> 2.20.1
>
--
^ permalink raw reply [flat|nested] 80+ messages in thread
* [PATCH 15/25] hw/arm/musca: Create and connect ARMSSE Clocks
2021-01-21 19:05 [PATCH 00/25] Convert CMSDK timer, watchdog, dualtimer to Clock framework Peter Maydell
` (13 preceding siblings ...)
2021-01-21 19:06 ` [PATCH 14/25] hw/arm/mps2-tz: Create and connect ARMSSE Clocks Peter Maydell
@ 2021-01-21 19:06 ` Peter Maydell
2021-01-21 21:30 ` Philippe Mathieu-Daudé
2021-01-22 20:01 ` Luc Michel
2021-01-21 19:06 ` [PATCH 16/25] hw/arm/stellaris: Convert SSYS to QOM device Peter Maydell
` (9 subsequent siblings)
24 siblings, 2 replies; 80+ messages in thread
From: Peter Maydell @ 2021-01-21 19:06 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Philippe Mathieu-Daudé
Create and connect the two clocks needed by the ARMSSE.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/musca.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/hw/arm/musca.c b/hw/arm/musca.c
index d82bef11cf2..a9292482a06 100644
--- a/hw/arm/musca.c
+++ b/hw/arm/musca.c
@@ -33,6 +33,7 @@
#include "hw/misc/tz-ppc.h"
#include "hw/misc/unimp.h"
#include "hw/rtc/pl031.h"
+#include "hw/qdev-clock.h"
#include "qom/object.h"
#define MUSCA_NUMIRQ_MAX 96
@@ -82,6 +83,8 @@ struct MuscaMachineState {
UnimplementedDeviceState sdio;
UnimplementedDeviceState gpio;
UnimplementedDeviceState cryptoisland;
+ Clock *sysclk;
+ Clock *s32kclk;
};
#define TYPE_MUSCA_MACHINE "musca"
@@ -96,6 +99,8 @@ OBJECT_DECLARE_TYPE(MuscaMachineState, MuscaMachineClass, MUSCA_MACHINE)
* don't model that in our SSE-200 model yet.
*/
#define SYSCLK_FRQ 40000000
+/* Slow 32Khz S32KCLK frequency in Hz */
+#define S32KCLK_FRQ (32 * 1000)
static qemu_irq get_sse_irq_in(MuscaMachineState *mms, int irqno)
{
@@ -367,6 +372,11 @@ static void musca_init(MachineState *machine)
exit(1);
}
+ mms->sysclk = clock_new(OBJECT(machine), "SYSCLK");
+ clock_set_hz(mms->sysclk, SYSCLK_FRQ);
+ mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK");
+ clock_set_hz(mms->s32kclk, S32KCLK_FRQ);
+
object_initialize_child(OBJECT(machine), "sse-200", &mms->sse,
TYPE_SSE200);
ssedev = DEVICE(&mms->sse);
@@ -376,6 +386,8 @@ static void musca_init(MachineState *machine)
qdev_prop_set_uint32(ssedev, "init-svtor", mmc->init_svtor);
qdev_prop_set_uint32(ssedev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width);
qdev_prop_set_uint32(ssedev, "MAINCLK_FRQ", SYSCLK_FRQ);
+ qdev_connect_clock_in(ssedev, "MAINCLK", mms->sysclk);
+ qdev_connect_clock_in(ssedev, "S32KCLK", mms->s32kclk);
/*
* Musca-A takes the default SSE-200 FPU/DSP settings (ie no for
* CPU0 and yes for CPU1); Musca-B1 explicitly enables them for CPU0.
--
2.20.1
^ permalink raw reply related [flat|nested] 80+ messages in thread* Re: [PATCH 15/25] hw/arm/musca: Create and connect ARMSSE Clocks
2021-01-21 19:06 ` [PATCH 15/25] hw/arm/musca: " Peter Maydell
@ 2021-01-21 21:30 ` Philippe Mathieu-Daudé
2021-01-22 20:01 ` Luc Michel
1 sibling, 0 replies; 80+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-21 21:30 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel; +Cc: Damien Hedde, Luc Michel
On 1/21/21 8:06 PM, Peter Maydell wrote:
> Create and connect the two clocks needed by the ARMSSE.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> hw/arm/musca.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 15/25] hw/arm/musca: Create and connect ARMSSE Clocks
2021-01-21 19:06 ` [PATCH 15/25] hw/arm/musca: " Peter Maydell
2021-01-21 21:30 ` Philippe Mathieu-Daudé
@ 2021-01-22 20:01 ` Luc Michel
1 sibling, 0 replies; 80+ messages in thread
From: Luc Michel @ 2021-01-22 20:01 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, qemu-arm, qemu-devel, Philippe Mathieu-Daudé
On 19:06 Thu 21 Jan , Peter Maydell wrote:
> Create and connect the two clocks needed by the ARMSSE.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
> ---
> hw/arm/musca.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/hw/arm/musca.c b/hw/arm/musca.c
> index d82bef11cf2..a9292482a06 100644
> --- a/hw/arm/musca.c
> +++ b/hw/arm/musca.c
> @@ -33,6 +33,7 @@
> #include "hw/misc/tz-ppc.h"
> #include "hw/misc/unimp.h"
> #include "hw/rtc/pl031.h"
> +#include "hw/qdev-clock.h"
> #include "qom/object.h"
>
> #define MUSCA_NUMIRQ_MAX 96
> @@ -82,6 +83,8 @@ struct MuscaMachineState {
> UnimplementedDeviceState sdio;
> UnimplementedDeviceState gpio;
> UnimplementedDeviceState cryptoisland;
> + Clock *sysclk;
> + Clock *s32kclk;
> };
>
> #define TYPE_MUSCA_MACHINE "musca"
> @@ -96,6 +99,8 @@ OBJECT_DECLARE_TYPE(MuscaMachineState, MuscaMachineClass, MUSCA_MACHINE)
> * don't model that in our SSE-200 model yet.
> */
> #define SYSCLK_FRQ 40000000
> +/* Slow 32Khz S32KCLK frequency in Hz */
> +#define S32KCLK_FRQ (32 * 1000)
>
> static qemu_irq get_sse_irq_in(MuscaMachineState *mms, int irqno)
> {
> @@ -367,6 +372,11 @@ static void musca_init(MachineState *machine)
> exit(1);
> }
>
> + mms->sysclk = clock_new(OBJECT(machine), "SYSCLK");
> + clock_set_hz(mms->sysclk, SYSCLK_FRQ);
> + mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK");
> + clock_set_hz(mms->s32kclk, S32KCLK_FRQ);
> +
> object_initialize_child(OBJECT(machine), "sse-200", &mms->sse,
> TYPE_SSE200);
> ssedev = DEVICE(&mms->sse);
> @@ -376,6 +386,8 @@ static void musca_init(MachineState *machine)
> qdev_prop_set_uint32(ssedev, "init-svtor", mmc->init_svtor);
> qdev_prop_set_uint32(ssedev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width);
> qdev_prop_set_uint32(ssedev, "MAINCLK_FRQ", SYSCLK_FRQ);
> + qdev_connect_clock_in(ssedev, "MAINCLK", mms->sysclk);
> + qdev_connect_clock_in(ssedev, "S32KCLK", mms->s32kclk);
> /*
> * Musca-A takes the default SSE-200 FPU/DSP settings (ie no for
> * CPU0 and yes for CPU1); Musca-B1 explicitly enables them for CPU0.
> --
> 2.20.1
>
--
^ permalink raw reply [flat|nested] 80+ messages in thread
* [PATCH 16/25] hw/arm/stellaris: Convert SSYS to QOM device
2021-01-21 19:05 [PATCH 00/25] Convert CMSDK timer, watchdog, dualtimer to Clock framework Peter Maydell
` (14 preceding siblings ...)
2021-01-21 19:06 ` [PATCH 15/25] hw/arm/musca: " Peter Maydell
@ 2021-01-21 19:06 ` Peter Maydell
2021-01-21 22:13 ` Philippe Mathieu-Daudé
2021-01-22 20:26 ` Luc Michel
2021-01-21 19:06 ` [PATCH 17/25] hw/arm/stellaris: Create Clock input for watchdog Peter Maydell
` (8 subsequent siblings)
24 siblings, 2 replies; 80+ messages in thread
From: Peter Maydell @ 2021-01-21 19:06 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Philippe Mathieu-Daudé
Convert the SSYS code in the Stellaris boards (which encapsulates the
system registers) to a proper QOM device. This will provide us with
somewhere to put the output Clock whose frequency depends on the
setting of the PLL configuration registers.
This is a migration compatibility break for lm3s811evb, lm3s6965evb.
We use 3-phase reset here because the Clock will need to propagate
its value in the hold phase.
For the moment we reset the device during the board creation so that
the system_clock_scale global gets set; this will be removed in a
subsequent commit.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/stellaris.c | 132 ++++++++++++++++++++++++++++++++++++---------
1 file changed, 107 insertions(+), 25 deletions(-)
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index 652823195b1..0194ede2fe0 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -357,7 +357,12 @@ static void stellaris_gptm_realize(DeviceState *dev, Error **errp)
/* System controller. */
-typedef struct {
+#define TYPE_STELLARIS_SYS "stellaris-sys"
+OBJECT_DECLARE_SIMPLE_TYPE(ssys_state, STELLARIS_SYS)
+
+struct ssys_state {
+ SysBusDevice parent_obj;
+
MemoryRegion iomem;
uint32_t pborctl;
uint32_t ldopctl;
@@ -371,11 +376,18 @@ typedef struct {
uint32_t dcgc[3];
uint32_t clkvclr;
uint32_t ldoarst;
+ qemu_irq irq;
+ /* Properties (all read-only registers) */
uint32_t user0;
uint32_t user1;
- qemu_irq irq;
- stellaris_board_info *board;
-} ssys_state;
+ uint32_t did0;
+ uint32_t did1;
+ uint32_t dc0;
+ uint32_t dc1;
+ uint32_t dc2;
+ uint32_t dc3;
+ uint32_t dc4;
+};
static void ssys_update(ssys_state *s)
{
@@ -430,7 +442,7 @@ static uint32_t pllcfg_fury[16] = {
static int ssys_board_class(const ssys_state *s)
{
- uint32_t did0 = s->board->did0;
+ uint32_t did0 = s->did0;
switch (did0 & DID0_VER_MASK) {
case DID0_VER_0:
return DID0_CLASS_SANDSTORM;
@@ -456,19 +468,19 @@ static uint64_t ssys_read(void *opaque, hwaddr offset,
switch (offset) {
case 0x000: /* DID0 */
- return s->board->did0;
+ return s->did0;
case 0x004: /* DID1 */
- return s->board->did1;
+ return s->did1;
case 0x008: /* DC0 */
- return s->board->dc0;
+ return s->dc0;
case 0x010: /* DC1 */
- return s->board->dc1;
+ return s->dc1;
case 0x014: /* DC2 */
- return s->board->dc2;
+ return s->dc2;
case 0x018: /* DC3 */
- return s->board->dc3;
+ return s->dc3;
case 0x01c: /* DC4 */
- return s->board->dc4;
+ return s->dc4;
case 0x030: /* PBORCTL */
return s->pborctl;
case 0x034: /* LDOPCTL */
@@ -646,9 +658,9 @@ static const MemoryRegionOps ssys_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static void ssys_reset(void *opaque)
+static void stellaris_sys_reset_enter(Object *obj, ResetType type)
{
- ssys_state *s = (ssys_state *)opaque;
+ ssys_state *s = STELLARIS_SYS(obj);
s->pborctl = 0x7ffd;
s->rcc = 0x078e3ac0;
@@ -661,9 +673,19 @@ static void ssys_reset(void *opaque)
s->rcgc[0] = 1;
s->scgc[0] = 1;
s->dcgc[0] = 1;
+}
+
+static void stellaris_sys_reset_hold(Object *obj)
+{
+ ssys_state *s = STELLARIS_SYS(obj);
+
ssys_calculate_system_clock(s);
}
+static void stellaris_sys_reset_exit(Object *obj)
+{
+}
+
static int stellaris_sys_post_load(void *opaque, int version_id)
{
ssys_state *s = opaque;
@@ -695,27 +717,66 @@ static const VMStateDescription vmstate_stellaris_sys = {
}
};
+static Property stellaris_sys_properties[] = {
+ DEFINE_PROP_UINT32("user0", ssys_state, user0, 0),
+ DEFINE_PROP_UINT32("user1", ssys_state, user1, 0),
+ DEFINE_PROP_UINT32("did0", ssys_state, did0, 0),
+ DEFINE_PROP_UINT32("did1", ssys_state, did1, 0),
+ DEFINE_PROP_UINT32("dc0", ssys_state, dc0, 0),
+ DEFINE_PROP_UINT32("dc1", ssys_state, dc1, 0),
+ DEFINE_PROP_UINT32("dc2", ssys_state, dc2, 0),
+ DEFINE_PROP_UINT32("dc3", ssys_state, dc3, 0),
+ DEFINE_PROP_UINT32("dc4", ssys_state, dc4, 0),
+ DEFINE_PROP_END_OF_LIST()
+};
+
+static void stellaris_sys_instance_init(Object *obj)
+{
+ ssys_state *s = STELLARIS_SYS(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(s);
+
+ memory_region_init_io(&s->iomem, obj, &ssys_ops, s, "ssys", 0x00001000);
+ sysbus_init_mmio(sbd, &s->iomem);
+ sysbus_init_irq(sbd, &s->irq);
+}
+
static int stellaris_sys_init(uint32_t base, qemu_irq irq,
stellaris_board_info * board,
uint8_t *macaddr)
{
- ssys_state *s;
+ DeviceState *dev = qdev_new(TYPE_STELLARIS_SYS);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
- s = g_new0(ssys_state, 1);
- s->irq = irq;
- s->board = board;
/* Most devices come preprogrammed with a MAC address in the user data. */
- s->user0 = macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16);
- s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16);
+ qdev_prop_set_uint32(dev, "user0",
+ macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16));
+ qdev_prop_set_uint32(dev, "user1",
+ macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16));
+ qdev_prop_set_uint32(dev, "did0", board->did0);
+ qdev_prop_set_uint32(dev, "did1", board->did1);
+ qdev_prop_set_uint32(dev, "dc0", board->dc0);
+ qdev_prop_set_uint32(dev, "dc1", board->dc1);
+ qdev_prop_set_uint32(dev, "dc2", board->dc2);
+ qdev_prop_set_uint32(dev, "dc3", board->dc3);
+ qdev_prop_set_uint32(dev, "dc4", board->dc4);
+
+ sysbus_realize_and_unref(sbd, &error_fatal);
+ sysbus_mmio_map(sbd, 0, base);
+ sysbus_connect_irq(sbd, 0, irq);
+
+ /*
+ * Normally we should not be resetting devices like this during
+ * board creation. For the moment we need to do so, because
+ * system_clock_scale will only get set when the STELLARIS_SYS
+ * device is reset, and we need its initial value to pass to
+ * the watchdog device. This hack can be removed once the
+ * watchdog has been converted to use a Clock input instead.
+ */
+ device_cold_reset(dev);
- memory_region_init_io(&s->iomem, NULL, &ssys_ops, s, "ssys", 0x00001000);
- memory_region_add_subregion(get_system_memory(), base, &s->iomem);
- ssys_reset(s);
- vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_stellaris_sys, s);
return 0;
}
-
/* I2C controller. */
#define TYPE_STELLARIS_I2C "stellaris-i2c"
@@ -1553,11 +1614,32 @@ static const TypeInfo stellaris_adc_info = {
.class_init = stellaris_adc_class_init,
};
+static void stellaris_sys_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
+
+ dc->vmsd = &vmstate_stellaris_sys;
+ rc->phases.enter = stellaris_sys_reset_enter;
+ rc->phases.hold = stellaris_sys_reset_hold;
+ rc->phases.exit = stellaris_sys_reset_exit;
+ device_class_set_props(dc, stellaris_sys_properties);
+}
+
+static const TypeInfo stellaris_sys_info = {
+ .name = TYPE_STELLARIS_SYS,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(ssys_state),
+ .instance_init = stellaris_sys_instance_init,
+ .class_init = stellaris_sys_class_init,
+};
+
static void stellaris_register_types(void)
{
type_register_static(&stellaris_i2c_info);
type_register_static(&stellaris_gptm_info);
type_register_static(&stellaris_adc_info);
+ type_register_static(&stellaris_sys_info);
}
type_init(stellaris_register_types)
--
2.20.1
^ permalink raw reply related [flat|nested] 80+ messages in thread* Re: [PATCH 16/25] hw/arm/stellaris: Convert SSYS to QOM device
2021-01-21 19:06 ` [PATCH 16/25] hw/arm/stellaris: Convert SSYS to QOM device Peter Maydell
@ 2021-01-21 22:13 ` Philippe Mathieu-Daudé
2021-01-25 11:48 ` Peter Maydell
2021-01-22 20:26 ` Luc Michel
1 sibling, 1 reply; 80+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-21 22:13 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel; +Cc: Damien Hedde, Luc Michel
Hi Peter,
On 1/21/21 8:06 PM, Peter Maydell wrote:
> Convert the SSYS code in the Stellaris boards (which encapsulates the
> system registers) to a proper QOM device. This will provide us with
> somewhere to put the output Clock whose frequency depends on the
> setting of the PLL configuration registers.
>
> This is a migration compatibility break for lm3s811evb, lm3s6965evb.
>
> We use 3-phase reset here because the Clock will need to propagate
> its value in the hold phase.
>
> For the moment we reset the device during the board creation so that
> the system_clock_scale global gets set; this will be removed in a
> subsequent commit.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> hw/arm/stellaris.c | 132 ++++++++++++++++++++++++++++++++++++---------
> 1 file changed, 107 insertions(+), 25 deletions(-)
>
> diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
> index 652823195b1..0194ede2fe0 100644
> --- a/hw/arm/stellaris.c
> +++ b/hw/arm/stellaris.c
> @@ -357,7 +357,12 @@ static void stellaris_gptm_realize(DeviceState *dev, Error **errp)
>
> /* System controller. */
>
> -typedef struct {
> +#define TYPE_STELLARIS_SYS "stellaris-sys"
> +OBJECT_DECLARE_SIMPLE_TYPE(ssys_state, STELLARIS_SYS)
> +
> +struct ssys_state {
> + SysBusDevice parent_obj;
> +
> MemoryRegion iomem;
> uint32_t pborctl;
> uint32_t ldopctl;
> @@ -371,11 +376,18 @@ typedef struct {
> uint32_t dcgc[3];
> uint32_t clkvclr;
> uint32_t ldoarst;
> + qemu_irq irq;
> + /* Properties (all read-only registers) */
> uint32_t user0;
> uint32_t user1;
> - qemu_irq irq;
> - stellaris_board_info *board;
> -} ssys_state;
> + uint32_t did0;
> + uint32_t did1;
> + uint32_t dc0;
> + uint32_t dc1;
> + uint32_t dc2;
> + uint32_t dc3;
> + uint32_t dc4;
Shouldn't these be class properties?
> +};
^ permalink raw reply [flat|nested] 80+ messages in thread* Re: [PATCH 16/25] hw/arm/stellaris: Convert SSYS to QOM device
2021-01-21 22:13 ` Philippe Mathieu-Daudé
@ 2021-01-25 11:48 ` Peter Maydell
2021-01-27 22:10 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 80+ messages in thread
From: Peter Maydell @ 2021-01-25 11:48 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Damien Hedde, qemu-arm, Luc Michel, QEMU Developers
On Thu, 21 Jan 2021 at 22:13, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> Hi Peter,
>
> On 1/21/21 8:06 PM, Peter Maydell wrote:
> > Convert the SSYS code in the Stellaris boards (which encapsulates the
> > system registers) to a proper QOM device. This will provide us with
> > somewhere to put the output Clock whose frequency depends on the
> > setting of the PLL configuration registers.
> >
> > This is a migration compatibility break for lm3s811evb, lm3s6965evb.
> >
> > We use 3-phase reset here because the Clock will need to propagate
> > its value in the hold phase.
> >
> > For the moment we reset the device during the board creation so that
> > the system_clock_scale global gets set; this will be removed in a
> > subsequent commit.
> > +
> > +struct ssys_state {
> > + SysBusDevice parent_obj;
> > +
> > MemoryRegion iomem;
> > uint32_t pborctl;
> > uint32_t ldopctl;
> > @@ -371,11 +376,18 @@ typedef struct {
> > uint32_t dcgc[3];
> > uint32_t clkvclr;
> > uint32_t ldoarst;
> > + qemu_irq irq;
> > + /* Properties (all read-only registers) */
> > uint32_t user0;
> > uint32_t user1;
> > - qemu_irq irq;
> > - stellaris_board_info *board;
> > -} ssys_state;
> > + uint32_t did0;
> > + uint32_t did1;
> > + uint32_t dc0;
> > + uint32_t dc1;
> > + uint32_t dc2;
> > + uint32_t dc3;
> > + uint32_t dc4;
>
> Shouldn't these be class properties?
Could you elaborate on what you think the code ought to look like?
I just used the usual thing of defining uint32 qdev properties so we
can set these values when we create the device, as a replacement
for the existing code which either reaches directly into the
state struct to set the user0/user1 values or sets the
stellaris_board_info pointer in the state struct.
thanks
-- PMM
^ permalink raw reply [flat|nested] 80+ messages in thread* Re: [PATCH 16/25] hw/arm/stellaris: Convert SSYS to QOM device
2021-01-25 11:48 ` Peter Maydell
@ 2021-01-27 22:10 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 80+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-27 22:10 UTC (permalink / raw)
To: Peter Maydell; +Cc: Damien Hedde, qemu-arm, Luc Michel, QEMU Developers
On 1/25/21 12:48 PM, Peter Maydell wrote:
> On Thu, 21 Jan 2021 at 22:13, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>> On 1/21/21 8:06 PM, Peter Maydell wrote:
>>> Convert the SSYS code in the Stellaris boards (which encapsulates the
>>> system registers) to a proper QOM device. This will provide us with
>>> somewhere to put the output Clock whose frequency depends on the
>>> setting of the PLL configuration registers.
>>>
>>> This is a migration compatibility break for lm3s811evb, lm3s6965evb.
>>>
>>> We use 3-phase reset here because the Clock will need to propagate
>>> its value in the hold phase.
>>>
>>> For the moment we reset the device during the board creation so that
>>> the system_clock_scale global gets set; this will be removed in a
>>> subsequent commit.
>
>>> +
>>> +struct ssys_state {
>>> + SysBusDevice parent_obj;
>>> +
>>> MemoryRegion iomem;
>>> uint32_t pborctl;
>>> uint32_t ldopctl;
>>> @@ -371,11 +376,18 @@ typedef struct {
>>> uint32_t dcgc[3];
>>> uint32_t clkvclr;
>>> uint32_t ldoarst;
>>> + qemu_irq irq;
>>> + /* Properties (all read-only registers) */
>>> uint32_t user0;
>>> uint32_t user1;
>>> - qemu_irq irq;
>>> - stellaris_board_info *board;
>>> -} ssys_state;
>>> + uint32_t did0;
>>> + uint32_t did1;
>>> + uint32_t dc0;
>>> + uint32_t dc1;
>>> + uint32_t dc2;
>>> + uint32_t dc3;
>>> + uint32_t dc4;
>>
>> Shouldn't these be class properties?
>
> Could you elaborate on what you think the code ought to look like?
I am thinking something similar how Igor asked me to implement
RaspiMachineClass::board_rev in hw/arm/raspi.c, as the did/dc registers
are read-only. Anyhow this is 1/ probably not necessary and 2/ out of
the scope of this series, this patch is already complex enough, and
the work is done.
> I just used the usual thing of defining uint32 qdev properties so we
> can set these values when we create the device, as a replacement
> for the existing code which either reaches directly into the
> state struct to set the user0/user1 values or sets the
> stellaris_board_info pointer in the state struct.
No problem.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 16/25] hw/arm/stellaris: Convert SSYS to QOM device
2021-01-21 19:06 ` [PATCH 16/25] hw/arm/stellaris: Convert SSYS to QOM device Peter Maydell
2021-01-21 22:13 ` Philippe Mathieu-Daudé
@ 2021-01-22 20:26 ` Luc Michel
1 sibling, 0 replies; 80+ messages in thread
From: Luc Michel @ 2021-01-22 20:26 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, qemu-arm, qemu-devel, Philippe Mathieu-Daudé
On 19:06 Thu 21 Jan , Peter Maydell wrote:
> Convert the SSYS code in the Stellaris boards (which encapsulates the
> system registers) to a proper QOM device. This will provide us with
> somewhere to put the output Clock whose frequency depends on the
> setting of the PLL configuration registers.
>
> This is a migration compatibility break for lm3s811evb, lm3s6965evb.
>
> We use 3-phase reset here because the Clock will need to propagate
> its value in the hold phase.
>
> For the moment we reset the device during the board creation so that
> the system_clock_scale global gets set; this will be removed in a
> subsequent commit.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
> ---
> hw/arm/stellaris.c | 132 ++++++++++++++++++++++++++++++++++++---------
> 1 file changed, 107 insertions(+), 25 deletions(-)
>
> diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
> index 652823195b1..0194ede2fe0 100644
> --- a/hw/arm/stellaris.c
> +++ b/hw/arm/stellaris.c
> @@ -357,7 +357,12 @@ static void stellaris_gptm_realize(DeviceState *dev, Error **errp)
>
> /* System controller. */
>
> -typedef struct {
> +#define TYPE_STELLARIS_SYS "stellaris-sys"
> +OBJECT_DECLARE_SIMPLE_TYPE(ssys_state, STELLARIS_SYS)
> +
> +struct ssys_state {
> + SysBusDevice parent_obj;
> +
> MemoryRegion iomem;
> uint32_t pborctl;
> uint32_t ldopctl;
> @@ -371,11 +376,18 @@ typedef struct {
> uint32_t dcgc[3];
> uint32_t clkvclr;
> uint32_t ldoarst;
> + qemu_irq irq;
> + /* Properties (all read-only registers) */
> uint32_t user0;
> uint32_t user1;
> - qemu_irq irq;
> - stellaris_board_info *board;
> -} ssys_state;
> + uint32_t did0;
> + uint32_t did1;
> + uint32_t dc0;
> + uint32_t dc1;
> + uint32_t dc2;
> + uint32_t dc3;
> + uint32_t dc4;
> +};
>
> static void ssys_update(ssys_state *s)
> {
> @@ -430,7 +442,7 @@ static uint32_t pllcfg_fury[16] = {
>
> static int ssys_board_class(const ssys_state *s)
> {
> - uint32_t did0 = s->board->did0;
> + uint32_t did0 = s->did0;
> switch (did0 & DID0_VER_MASK) {
> case DID0_VER_0:
> return DID0_CLASS_SANDSTORM;
> @@ -456,19 +468,19 @@ static uint64_t ssys_read(void *opaque, hwaddr offset,
>
> switch (offset) {
> case 0x000: /* DID0 */
> - return s->board->did0;
> + return s->did0;
> case 0x004: /* DID1 */
> - return s->board->did1;
> + return s->did1;
> case 0x008: /* DC0 */
> - return s->board->dc0;
> + return s->dc0;
> case 0x010: /* DC1 */
> - return s->board->dc1;
> + return s->dc1;
> case 0x014: /* DC2 */
> - return s->board->dc2;
> + return s->dc2;
> case 0x018: /* DC3 */
> - return s->board->dc3;
> + return s->dc3;
> case 0x01c: /* DC4 */
> - return s->board->dc4;
> + return s->dc4;
> case 0x030: /* PBORCTL */
> return s->pborctl;
> case 0x034: /* LDOPCTL */
> @@ -646,9 +658,9 @@ static const MemoryRegionOps ssys_ops = {
> .endianness = DEVICE_NATIVE_ENDIAN,
> };
>
> -static void ssys_reset(void *opaque)
> +static void stellaris_sys_reset_enter(Object *obj, ResetType type)
> {
> - ssys_state *s = (ssys_state *)opaque;
> + ssys_state *s = STELLARIS_SYS(obj);
>
> s->pborctl = 0x7ffd;
> s->rcc = 0x078e3ac0;
> @@ -661,9 +673,19 @@ static void ssys_reset(void *opaque)
> s->rcgc[0] = 1;
> s->scgc[0] = 1;
> s->dcgc[0] = 1;
> +}
> +
> +static void stellaris_sys_reset_hold(Object *obj)
> +{
> + ssys_state *s = STELLARIS_SYS(obj);
> +
> ssys_calculate_system_clock(s);
> }
>
> +static void stellaris_sys_reset_exit(Object *obj)
> +{
> +}
> +
> static int stellaris_sys_post_load(void *opaque, int version_id)
> {
> ssys_state *s = opaque;
> @@ -695,27 +717,66 @@ static const VMStateDescription vmstate_stellaris_sys = {
> }
> };
>
> +static Property stellaris_sys_properties[] = {
> + DEFINE_PROP_UINT32("user0", ssys_state, user0, 0),
> + DEFINE_PROP_UINT32("user1", ssys_state, user1, 0),
> + DEFINE_PROP_UINT32("did0", ssys_state, did0, 0),
> + DEFINE_PROP_UINT32("did1", ssys_state, did1, 0),
> + DEFINE_PROP_UINT32("dc0", ssys_state, dc0, 0),
> + DEFINE_PROP_UINT32("dc1", ssys_state, dc1, 0),
> + DEFINE_PROP_UINT32("dc2", ssys_state, dc2, 0),
> + DEFINE_PROP_UINT32("dc3", ssys_state, dc3, 0),
> + DEFINE_PROP_UINT32("dc4", ssys_state, dc4, 0),
> + DEFINE_PROP_END_OF_LIST()
> +};
> +
> +static void stellaris_sys_instance_init(Object *obj)
> +{
> + ssys_state *s = STELLARIS_SYS(obj);
> + SysBusDevice *sbd = SYS_BUS_DEVICE(s);
> +
> + memory_region_init_io(&s->iomem, obj, &ssys_ops, s, "ssys", 0x00001000);
> + sysbus_init_mmio(sbd, &s->iomem);
> + sysbus_init_irq(sbd, &s->irq);
> +}
> +
> static int stellaris_sys_init(uint32_t base, qemu_irq irq,
> stellaris_board_info * board,
> uint8_t *macaddr)
> {
> - ssys_state *s;
> + DeviceState *dev = qdev_new(TYPE_STELLARIS_SYS);
> + SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
>
> - s = g_new0(ssys_state, 1);
> - s->irq = irq;
> - s->board = board;
> /* Most devices come preprogrammed with a MAC address in the user data. */
> - s->user0 = macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16);
> - s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16);
> + qdev_prop_set_uint32(dev, "user0",
> + macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16));
> + qdev_prop_set_uint32(dev, "user1",
> + macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16));
> + qdev_prop_set_uint32(dev, "did0", board->did0);
> + qdev_prop_set_uint32(dev, "did1", board->did1);
> + qdev_prop_set_uint32(dev, "dc0", board->dc0);
> + qdev_prop_set_uint32(dev, "dc1", board->dc1);
> + qdev_prop_set_uint32(dev, "dc2", board->dc2);
> + qdev_prop_set_uint32(dev, "dc3", board->dc3);
> + qdev_prop_set_uint32(dev, "dc4", board->dc4);
> +
> + sysbus_realize_and_unref(sbd, &error_fatal);
> + sysbus_mmio_map(sbd, 0, base);
> + sysbus_connect_irq(sbd, 0, irq);
> +
> + /*
> + * Normally we should not be resetting devices like this during
> + * board creation. For the moment we need to do so, because
> + * system_clock_scale will only get set when the STELLARIS_SYS
> + * device is reset, and we need its initial value to pass to
> + * the watchdog device. This hack can be removed once the
> + * watchdog has been converted to use a Clock input instead.
> + */
> + device_cold_reset(dev);
>
> - memory_region_init_io(&s->iomem, NULL, &ssys_ops, s, "ssys", 0x00001000);
> - memory_region_add_subregion(get_system_memory(), base, &s->iomem);
> - ssys_reset(s);
> - vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_stellaris_sys, s);
> return 0;
> }
>
> -
> /* I2C controller. */
>
> #define TYPE_STELLARIS_I2C "stellaris-i2c"
> @@ -1553,11 +1614,32 @@ static const TypeInfo stellaris_adc_info = {
> .class_init = stellaris_adc_class_init,
> };
>
> +static void stellaris_sys_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + ResettableClass *rc = RESETTABLE_CLASS(klass);
> +
> + dc->vmsd = &vmstate_stellaris_sys;
> + rc->phases.enter = stellaris_sys_reset_enter;
> + rc->phases.hold = stellaris_sys_reset_hold;
> + rc->phases.exit = stellaris_sys_reset_exit;
> + device_class_set_props(dc, stellaris_sys_properties);
> +}
> +
> +static const TypeInfo stellaris_sys_info = {
> + .name = TYPE_STELLARIS_SYS,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(ssys_state),
> + .instance_init = stellaris_sys_instance_init,
> + .class_init = stellaris_sys_class_init,
> +};
> +
> static void stellaris_register_types(void)
> {
> type_register_static(&stellaris_i2c_info);
> type_register_static(&stellaris_gptm_info);
> type_register_static(&stellaris_adc_info);
> + type_register_static(&stellaris_sys_info);
> }
>
> type_init(stellaris_register_types)
> --
> 2.20.1
>
--
^ permalink raw reply [flat|nested] 80+ messages in thread
* [PATCH 17/25] hw/arm/stellaris: Create Clock input for watchdog
2021-01-21 19:05 [PATCH 00/25] Convert CMSDK timer, watchdog, dualtimer to Clock framework Peter Maydell
` (15 preceding siblings ...)
2021-01-21 19:06 ` [PATCH 16/25] hw/arm/stellaris: Convert SSYS to QOM device Peter Maydell
@ 2021-01-21 19:06 ` Peter Maydell
2021-01-21 21:59 ` Philippe Mathieu-Daudé
2021-01-22 20:30 ` Luc Michel
2021-01-21 19:06 ` [PATCH 18/25] hw/timer/cmsdk-apb-timer: Convert to use Clock input Peter Maydell
` (7 subsequent siblings)
24 siblings, 2 replies; 80+ messages in thread
From: Peter Maydell @ 2021-01-21 19:06 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Philippe Mathieu-Daudé
Create and connect the Clock input for the watchdog device on the
Stellaris boards. Because the Stellaris boards model the ability to
change the clock rate by programming PLL registers, we have to create
an output Clock on the ssys_state device and wire it up to the
watchdog.
Note that the old comment on ssys_calculate_system_clock() got the
units wrong -- system_clock_scale is in nanoseconds, not
milliseconds. Improve the commentary to clarify how we are
calculating the period.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/stellaris.c | 43 +++++++++++++++++++++++++++++++------------
1 file changed, 31 insertions(+), 12 deletions(-)
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index 0194ede2fe0..9b67c739ef2 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -26,6 +26,7 @@
#include "hw/watchdog/cmsdk-apb-watchdog.h"
#include "migration/vmstate.h"
#include "hw/misc/unimp.h"
+#include "hw/qdev-clock.h"
#include "cpu.h"
#include "qom/object.h"
@@ -377,6 +378,7 @@ struct ssys_state {
uint32_t clkvclr;
uint32_t ldoarst;
qemu_irq irq;
+ Clock *sysclk;
/* Properties (all read-only registers) */
uint32_t user0;
uint32_t user1;
@@ -555,15 +557,26 @@ static bool ssys_use_rcc2(ssys_state *s)
}
/*
- * Caculate the sys. clock period in ms.
+ * Calculate the system clock period. We only want to propagate
+ * this change to the rest of the system if we're not being called
+ * from migration post-load.
*/
-static void ssys_calculate_system_clock(ssys_state *s)
+static void ssys_calculate_system_clock(ssys_state *s, bool propagate_clock)
{
+ /*
+ * SYSDIV field specifies divisor: 0 == /1, 1 == /2, etc. Input
+ * clock is 200MHz, which is a period of 5 ns. Dividing the clock
+ * frequency by X is the same as multiplying the period by X.
+ */
if (ssys_use_rcc2(s)) {
system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1);
} else {
system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1);
}
+ clock_set_ns(s->sysclk, system_clock_scale);
+ if (propagate_clock) {
+ clock_propagate(s->sysclk);
+ }
}
static void ssys_write(void *opaque, hwaddr offset,
@@ -598,7 +611,7 @@ static void ssys_write(void *opaque, hwaddr offset,
s->int_status |= (1 << 6);
}
s->rcc = value;
- ssys_calculate_system_clock(s);
+ ssys_calculate_system_clock(s, true);
break;
case 0x070: /* RCC2 */
if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
@@ -610,7 +623,7 @@ static void ssys_write(void *opaque, hwaddr offset,
s->int_status |= (1 << 6);
}
s->rcc2 = value;
- ssys_calculate_system_clock(s);
+ ssys_calculate_system_clock(s, true);
break;
case 0x100: /* RCGC0 */
s->rcgc[0] = value;
@@ -679,7 +692,8 @@ static void stellaris_sys_reset_hold(Object *obj)
{
ssys_state *s = STELLARIS_SYS(obj);
- ssys_calculate_system_clock(s);
+ /* OK to propagate clocks from the hold phase */
+ ssys_calculate_system_clock(s, true);
}
static void stellaris_sys_reset_exit(Object *obj)
@@ -690,7 +704,7 @@ static int stellaris_sys_post_load(void *opaque, int version_id)
{
ssys_state *s = opaque;
- ssys_calculate_system_clock(s);
+ ssys_calculate_system_clock(s, false);
return 0;
}
@@ -713,6 +727,7 @@ static const VMStateDescription vmstate_stellaris_sys = {
VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3),
VMSTATE_UINT32(clkvclr, ssys_state),
VMSTATE_UINT32(ldoarst, ssys_state),
+ /* No field for sysclk -- handled in post-load instead */
VMSTATE_END_OF_LIST()
}
};
@@ -738,11 +753,12 @@ static void stellaris_sys_instance_init(Object *obj)
memory_region_init_io(&s->iomem, obj, &ssys_ops, s, "ssys", 0x00001000);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq);
+ s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK");
}
-static int stellaris_sys_init(uint32_t base, qemu_irq irq,
- stellaris_board_info * board,
- uint8_t *macaddr)
+static DeviceState *stellaris_sys_init(uint32_t base, qemu_irq irq,
+ stellaris_board_info *board,
+ uint8_t *macaddr)
{
DeviceState *dev = qdev_new(TYPE_STELLARIS_SYS);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
@@ -774,7 +790,7 @@ static int stellaris_sys_init(uint32_t base, qemu_irq irq,
*/
device_cold_reset(dev);
- return 0;
+ return dev;
}
/* I2C controller. */
@@ -1341,6 +1357,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
int flash_size;
I2CBus *i2c;
DeviceState *dev;
+ DeviceState *ssys_dev;
int i;
int j;
@@ -1391,8 +1408,8 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
}
}
- stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28),
- board, nd_table[0].macaddr.a);
+ ssys_dev = stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28),
+ board, nd_table[0].macaddr.a);
if (board->dc1 & (1 << 3)) { /* watchdog present */
@@ -1401,6 +1418,8 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
/* system_clock_scale is valid now */
uint32_t mainclk = NANOSECONDS_PER_SECOND / system_clock_scale;
qdev_prop_set_uint32(dev, "wdogclk-frq", mainclk);
+ qdev_connect_clock_in(dev, "WDOGCLK",
+ qdev_get_clock_out(ssys_dev, "SYSCLK"));
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev),
--
2.20.1
^ permalink raw reply related [flat|nested] 80+ messages in thread* Re: [PATCH 17/25] hw/arm/stellaris: Create Clock input for watchdog
2021-01-21 19:06 ` [PATCH 17/25] hw/arm/stellaris: Create Clock input for watchdog Peter Maydell
@ 2021-01-21 21:59 ` Philippe Mathieu-Daudé
2021-01-27 22:16 ` Philippe Mathieu-Daudé
2021-01-22 20:30 ` Luc Michel
1 sibling, 1 reply; 80+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-21 21:59 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel; +Cc: Damien Hedde, Luc Michel
Hi Peter,
On 1/21/21 8:06 PM, Peter Maydell wrote:
> Create and connect the Clock input for the watchdog device on the
> Stellaris boards. Because the Stellaris boards model the ability to
> change the clock rate by programming PLL registers, we have to create
> an output Clock on the ssys_state device and wire it up to the
> watchdog.
>
> Note that the old comment on ssys_calculate_system_clock() got the
> units wrong -- system_clock_scale is in nanoseconds, not
> milliseconds. Improve the commentary to clarify how we are
> calculating the period.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> hw/arm/stellaris.c | 43 +++++++++++++++++++++++++++++++------------
> 1 file changed, 31 insertions(+), 12 deletions(-)
...
> /*
> - * Caculate the sys. clock period in ms.
> + * Calculate the system clock period. We only want to propagate
> + * this change to the rest of the system if we're not being called
> + * from migration post-load.
This part was not trivial to understand. I read the Clock API
doc again then found:
Care should be taken not to use ``clock_update[_ns|_hz]()`` or
``clock_propagate()`` during the whole migration procedure because it
will trigger side effects to other devices in an unknown state.
> */
> -static void ssys_calculate_system_clock(ssys_state *s)
> +static void ssys_calculate_system_clock(ssys_state *s, bool propagate_clock)
> {
> + /*
> + * SYSDIV field specifies divisor: 0 == /1, 1 == /2, etc. Input
> + * clock is 200MHz, which is a period of 5 ns. Dividing the clock
> + * frequency by X is the same as multiplying the period by X.
> + */
> if (ssys_use_rcc2(s)) {
> system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1);
> } else {
> system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1);
> }
> + clock_set_ns(s->sysclk, system_clock_scale);
> + if (propagate_clock) {
> + clock_propagate(s->sysclk);
> + }
> }
...
> static void stellaris_sys_reset_exit(Object *obj)
> @@ -690,7 +704,7 @@ static int stellaris_sys_post_load(void *opaque, int version_id)
> {
> ssys_state *s = opaque;
>
> - ssys_calculate_system_clock(s);
> + ssys_calculate_system_clock(s, false);
So this makes sense.
I'll keep reviewing and come back to this patch later.
Regards,
Phil.
^ permalink raw reply [flat|nested] 80+ messages in thread* Re: [PATCH 17/25] hw/arm/stellaris: Create Clock input for watchdog
2021-01-21 21:59 ` Philippe Mathieu-Daudé
@ 2021-01-27 22:16 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 80+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-27 22:16 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel; +Cc: Damien Hedde, Luc Michel
On 1/21/21 10:59 PM, Philippe Mathieu-Daudé wrote:
> On 1/21/21 8:06 PM, Peter Maydell wrote:
>> Create and connect the Clock input for the watchdog device on the
>> Stellaris boards. Because the Stellaris boards model the ability to
>> change the clock rate by programming PLL registers, we have to create
>> an output Clock on the ssys_state device and wire it up to the
>> watchdog.
>>
>> Note that the old comment on ssys_calculate_system_clock() got the
>> units wrong -- system_clock_scale is in nanoseconds, not
>> milliseconds. Improve the commentary to clarify how we are
>> calculating the period.
>>
>> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
>> ---
>> hw/arm/stellaris.c | 43 +++++++++++++++++++++++++++++++------------
>> 1 file changed, 31 insertions(+), 12 deletions(-)
> ...
>
>> /*
>> - * Caculate the sys. clock period in ms.
>> + * Calculate the system clock period. We only want to propagate
>> + * this change to the rest of the system if we're not being called
>> + * from migration post-load.
>
> This part was not trivial to understand. I read the Clock API
> doc again then found:
>
> Care should be taken not to use ``clock_update[_ns|_hz]()`` or
> ``clock_propagate()`` during the whole migration procedure because it
> will trigger side effects to other devices in an unknown state.
>
>> */
>> -static void ssys_calculate_system_clock(ssys_state *s)
>> +static void ssys_calculate_system_clock(ssys_state *s, bool propagate_clock)
>> {
>> + /*
>> + * SYSDIV field specifies divisor: 0 == /1, 1 == /2, etc. Input
>> + * clock is 200MHz, which is a period of 5 ns. Dividing the clock
>> + * frequency by X is the same as multiplying the period by X.
>> + */
>> if (ssys_use_rcc2(s)) {
>> system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1);
>> } else {
>> system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1);
>> }
>> + clock_set_ns(s->sysclk, system_clock_scale);
>> + if (propagate_clock) {
>> + clock_propagate(s->sysclk);
>> + }
>> }
> ...
>> static void stellaris_sys_reset_exit(Object *obj)
>> @@ -690,7 +704,7 @@ static int stellaris_sys_post_load(void *opaque, int version_id)
>> {
>> ssys_state *s = opaque;
>>
>> - ssys_calculate_system_clock(s);
>> + ssys_calculate_system_clock(s, false);
>
> So this makes sense.
>
> I'll keep reviewing and come back to this patch later.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 17/25] hw/arm/stellaris: Create Clock input for watchdog
2021-01-21 19:06 ` [PATCH 17/25] hw/arm/stellaris: Create Clock input for watchdog Peter Maydell
2021-01-21 21:59 ` Philippe Mathieu-Daudé
@ 2021-01-22 20:30 ` Luc Michel
1 sibling, 0 replies; 80+ messages in thread
From: Luc Michel @ 2021-01-22 20:30 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, qemu-arm, qemu-devel, Philippe Mathieu-Daudé
On 19:06 Thu 21 Jan , Peter Maydell wrote:
> Create and connect the Clock input for the watchdog device on the
> Stellaris boards. Because the Stellaris boards model the ability to
> change the clock rate by programming PLL registers, we have to create
> an output Clock on the ssys_state device and wire it up to the
> watchdog.
>
> Note that the old comment on ssys_calculate_system_clock() got the
> units wrong -- system_clock_scale is in nanoseconds, not
> milliseconds. Improve the commentary to clarify how we are
> calculating the period.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
> ---
> hw/arm/stellaris.c | 43 +++++++++++++++++++++++++++++++------------
> 1 file changed, 31 insertions(+), 12 deletions(-)
>
> diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
> index 0194ede2fe0..9b67c739ef2 100644
> --- a/hw/arm/stellaris.c
> +++ b/hw/arm/stellaris.c
> @@ -26,6 +26,7 @@
> #include "hw/watchdog/cmsdk-apb-watchdog.h"
> #include "migration/vmstate.h"
> #include "hw/misc/unimp.h"
> +#include "hw/qdev-clock.h"
> #include "cpu.h"
> #include "qom/object.h"
>
> @@ -377,6 +378,7 @@ struct ssys_state {
> uint32_t clkvclr;
> uint32_t ldoarst;
> qemu_irq irq;
> + Clock *sysclk;
> /* Properties (all read-only registers) */
> uint32_t user0;
> uint32_t user1;
> @@ -555,15 +557,26 @@ static bool ssys_use_rcc2(ssys_state *s)
> }
>
> /*
> - * Caculate the sys. clock period in ms.
> + * Calculate the system clock period. We only want to propagate
> + * this change to the rest of the system if we're not being called
> + * from migration post-load.
> */
> -static void ssys_calculate_system_clock(ssys_state *s)
> +static void ssys_calculate_system_clock(ssys_state *s, bool propagate_clock)
> {
> + /*
> + * SYSDIV field specifies divisor: 0 == /1, 1 == /2, etc. Input
> + * clock is 200MHz, which is a period of 5 ns. Dividing the clock
> + * frequency by X is the same as multiplying the period by X.
> + */
> if (ssys_use_rcc2(s)) {
> system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1);
> } else {
> system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1);
> }
> + clock_set_ns(s->sysclk, system_clock_scale);
> + if (propagate_clock) {
> + clock_propagate(s->sysclk);
> + }
> }
>
> static void ssys_write(void *opaque, hwaddr offset,
> @@ -598,7 +611,7 @@ static void ssys_write(void *opaque, hwaddr offset,
> s->int_status |= (1 << 6);
> }
> s->rcc = value;
> - ssys_calculate_system_clock(s);
> + ssys_calculate_system_clock(s, true);
> break;
> case 0x070: /* RCC2 */
> if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
> @@ -610,7 +623,7 @@ static void ssys_write(void *opaque, hwaddr offset,
> s->int_status |= (1 << 6);
> }
> s->rcc2 = value;
> - ssys_calculate_system_clock(s);
> + ssys_calculate_system_clock(s, true);
> break;
> case 0x100: /* RCGC0 */
> s->rcgc[0] = value;
> @@ -679,7 +692,8 @@ static void stellaris_sys_reset_hold(Object *obj)
> {
> ssys_state *s = STELLARIS_SYS(obj);
>
> - ssys_calculate_system_clock(s);
> + /* OK to propagate clocks from the hold phase */
> + ssys_calculate_system_clock(s, true);
> }
>
> static void stellaris_sys_reset_exit(Object *obj)
> @@ -690,7 +704,7 @@ static int stellaris_sys_post_load(void *opaque, int version_id)
> {
> ssys_state *s = opaque;
>
> - ssys_calculate_system_clock(s);
> + ssys_calculate_system_clock(s, false);
>
> return 0;
> }
> @@ -713,6 +727,7 @@ static const VMStateDescription vmstate_stellaris_sys = {
> VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3),
> VMSTATE_UINT32(clkvclr, ssys_state),
> VMSTATE_UINT32(ldoarst, ssys_state),
> + /* No field for sysclk -- handled in post-load instead */
> VMSTATE_END_OF_LIST()
> }
> };
> @@ -738,11 +753,12 @@ static void stellaris_sys_instance_init(Object *obj)
> memory_region_init_io(&s->iomem, obj, &ssys_ops, s, "ssys", 0x00001000);
> sysbus_init_mmio(sbd, &s->iomem);
> sysbus_init_irq(sbd, &s->irq);
> + s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK");
> }
>
> -static int stellaris_sys_init(uint32_t base, qemu_irq irq,
> - stellaris_board_info * board,
> - uint8_t *macaddr)
> +static DeviceState *stellaris_sys_init(uint32_t base, qemu_irq irq,
> + stellaris_board_info *board,
> + uint8_t *macaddr)
> {
> DeviceState *dev = qdev_new(TYPE_STELLARIS_SYS);
> SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
> @@ -774,7 +790,7 @@ static int stellaris_sys_init(uint32_t base, qemu_irq irq,
> */
> device_cold_reset(dev);
>
> - return 0;
> + return dev;
> }
>
> /* I2C controller. */
> @@ -1341,6 +1357,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
> int flash_size;
> I2CBus *i2c;
> DeviceState *dev;
> + DeviceState *ssys_dev;
> int i;
> int j;
>
> @@ -1391,8 +1408,8 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
> }
> }
>
> - stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28),
> - board, nd_table[0].macaddr.a);
> + ssys_dev = stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28),
> + board, nd_table[0].macaddr.a);
>
>
> if (board->dc1 & (1 << 3)) { /* watchdog present */
> @@ -1401,6 +1418,8 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
> /* system_clock_scale is valid now */
> uint32_t mainclk = NANOSECONDS_PER_SECOND / system_clock_scale;
> qdev_prop_set_uint32(dev, "wdogclk-frq", mainclk);
> + qdev_connect_clock_in(dev, "WDOGCLK",
> + qdev_get_clock_out(ssys_dev, "SYSCLK"));
>
> sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
> sysbus_mmio_map(SYS_BUS_DEVICE(dev),
> --
> 2.20.1
>
--
^ permalink raw reply [flat|nested] 80+ messages in thread
* [PATCH 18/25] hw/timer/cmsdk-apb-timer: Convert to use Clock input
2021-01-21 19:05 [PATCH 00/25] Convert CMSDK timer, watchdog, dualtimer to Clock framework Peter Maydell
` (16 preceding siblings ...)
2021-01-21 19:06 ` [PATCH 17/25] hw/arm/stellaris: Create Clock input for watchdog Peter Maydell
@ 2021-01-21 19:06 ` Peter Maydell
2021-01-21 22:01 ` Philippe Mathieu-Daudé
2021-01-22 20:33 ` Luc Michel
2021-01-21 19:06 ` [PATCH 19/25] hw/timer/cmsdk-apb-dualtimer: " Peter Maydell
` (6 subsequent siblings)
24 siblings, 2 replies; 80+ messages in thread
From: Peter Maydell @ 2021-01-21 19:06 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Philippe Mathieu-Daudé
Switch the CMSDK APB timer device over to using its Clock input; the
pclk-frq property is now ignored.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/timer/cmsdk-apb-timer.c | 18 ++++++++++++++----
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c
index c63145ff553..f053146d88f 100644
--- a/hw/timer/cmsdk-apb-timer.c
+++ b/hw/timer/cmsdk-apb-timer.c
@@ -204,6 +204,15 @@ static void cmsdk_apb_timer_reset(DeviceState *dev)
ptimer_transaction_commit(s->timer);
}
+static void cmsdk_apb_timer_clk_update(void *opaque)
+{
+ CMSDKAPBTimer *s = CMSDK_APB_TIMER(opaque);
+
+ ptimer_transaction_begin(s->timer);
+ ptimer_set_period_from_clock(s->timer, s->pclk, 1);
+ ptimer_transaction_commit(s->timer);
+}
+
static void cmsdk_apb_timer_init(Object *obj)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
@@ -213,15 +222,16 @@ static void cmsdk_apb_timer_init(Object *obj)
s, "cmsdk-apb-timer", 0x1000);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->timerint);
- s->pclk = qdev_init_clock_in(DEVICE(s), "pclk", NULL, NULL);
+ s->pclk = qdev_init_clock_in(DEVICE(s), "pclk",
+ cmsdk_apb_timer_clk_update, s);
}
static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp)
{
CMSDKAPBTimer *s = CMSDK_APB_TIMER(dev);
- if (s->pclk_frq == 0) {
- error_setg(errp, "CMSDK APB timer: pclk-frq property must be set");
+ if (!clock_has_source(s->pclk)) {
+ error_setg(errp, "CMSDK APB timer: pclk clock must be connected");
return;
}
@@ -232,7 +242,7 @@ static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp)
PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
ptimer_transaction_begin(s->timer);
- ptimer_set_freq(s->timer, s->pclk_frq);
+ ptimer_set_period_from_clock(s->timer, s->pclk, 1);
ptimer_transaction_commit(s->timer);
}
--
2.20.1
^ permalink raw reply related [flat|nested] 80+ messages in thread* Re: [PATCH 18/25] hw/timer/cmsdk-apb-timer: Convert to use Clock input
2021-01-21 19:06 ` [PATCH 18/25] hw/timer/cmsdk-apb-timer: Convert to use Clock input Peter Maydell
@ 2021-01-21 22:01 ` Philippe Mathieu-Daudé
2021-01-22 20:33 ` Luc Michel
1 sibling, 0 replies; 80+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-21 22:01 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel; +Cc: Damien Hedde, Luc Michel
On 1/21/21 8:06 PM, Peter Maydell wrote:
> Switch the CMSDK APB timer device over to using its Clock input; the
> pclk-frq property is now ignored.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> hw/timer/cmsdk-apb-timer.c | 18 ++++++++++++++----
> 1 file changed, 14 insertions(+), 4 deletions(-)
>
> diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c
> index c63145ff553..f053146d88f 100644
> --- a/hw/timer/cmsdk-apb-timer.c
> +++ b/hw/timer/cmsdk-apb-timer.c
> @@ -204,6 +204,15 @@ static void cmsdk_apb_timer_reset(DeviceState *dev)
> ptimer_transaction_commit(s->timer);
> }
>
> +static void cmsdk_apb_timer_clk_update(void *opaque)
> +{
> + CMSDKAPBTimer *s = CMSDK_APB_TIMER(opaque);
> +
> + ptimer_transaction_begin(s->timer);
> + ptimer_set_period_from_clock(s->timer, s->pclk, 1);
> + ptimer_transaction_commit(s->timer);
> +}
> +
> static void cmsdk_apb_timer_init(Object *obj)
> {
> SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
> @@ -213,15 +222,16 @@ static void cmsdk_apb_timer_init(Object *obj)
> s, "cmsdk-apb-timer", 0x1000);
> sysbus_init_mmio(sbd, &s->iomem);
> sysbus_init_irq(sbd, &s->timerint);
> - s->pclk = qdev_init_clock_in(DEVICE(s), "pclk", NULL, NULL);
> + s->pclk = qdev_init_clock_in(DEVICE(s), "pclk",
> + cmsdk_apb_timer_clk_update, s);
> }
>
> static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp)
> {
> CMSDKAPBTimer *s = CMSDK_APB_TIMER(dev);
>
> - if (s->pclk_frq == 0) {
> - error_setg(errp, "CMSDK APB timer: pclk-frq property must be set");
> + if (!clock_has_source(s->pclk)) {
> + error_setg(errp, "CMSDK APB timer: pclk clock must be connected");
> return;
> }
>
> @@ -232,7 +242,7 @@ static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp)
> PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
>
> ptimer_transaction_begin(s->timer);
> - ptimer_set_freq(s->timer, s->pclk_frq);
> + ptimer_set_period_from_clock(s->timer, s->pclk, 1);
> ptimer_transaction_commit(s->timer);
> }
Nice to see how ptimer_set_period_from_clock() fits :)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 80+ messages in thread* Re: [PATCH 18/25] hw/timer/cmsdk-apb-timer: Convert to use Clock input
2021-01-21 19:06 ` [PATCH 18/25] hw/timer/cmsdk-apb-timer: Convert to use Clock input Peter Maydell
2021-01-21 22:01 ` Philippe Mathieu-Daudé
@ 2021-01-22 20:33 ` Luc Michel
1 sibling, 0 replies; 80+ messages in thread
From: Luc Michel @ 2021-01-22 20:33 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, qemu-arm, qemu-devel, Philippe Mathieu-Daudé
On 19:06 Thu 21 Jan , Peter Maydell wrote:
> Switch the CMSDK APB timer device over to using its Clock input; the
> pclk-frq property is now ignored.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
> ---
> hw/timer/cmsdk-apb-timer.c | 18 ++++++++++++++----
> 1 file changed, 14 insertions(+), 4 deletions(-)
>
> diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c
> index c63145ff553..f053146d88f 100644
> --- a/hw/timer/cmsdk-apb-timer.c
> +++ b/hw/timer/cmsdk-apb-timer.c
> @@ -204,6 +204,15 @@ static void cmsdk_apb_timer_reset(DeviceState *dev)
> ptimer_transaction_commit(s->timer);
> }
>
> +static void cmsdk_apb_timer_clk_update(void *opaque)
> +{
> + CMSDKAPBTimer *s = CMSDK_APB_TIMER(opaque);
> +
> + ptimer_transaction_begin(s->timer);
> + ptimer_set_period_from_clock(s->timer, s->pclk, 1);
> + ptimer_transaction_commit(s->timer);
> +}
> +
> static void cmsdk_apb_timer_init(Object *obj)
> {
> SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
> @@ -213,15 +222,16 @@ static void cmsdk_apb_timer_init(Object *obj)
> s, "cmsdk-apb-timer", 0x1000);
> sysbus_init_mmio(sbd, &s->iomem);
> sysbus_init_irq(sbd, &s->timerint);
> - s->pclk = qdev_init_clock_in(DEVICE(s), "pclk", NULL, NULL);
> + s->pclk = qdev_init_clock_in(DEVICE(s), "pclk",
> + cmsdk_apb_timer_clk_update, s);
> }
>
> static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp)
> {
> CMSDKAPBTimer *s = CMSDK_APB_TIMER(dev);
>
> - if (s->pclk_frq == 0) {
> - error_setg(errp, "CMSDK APB timer: pclk-frq property must be set");
> + if (!clock_has_source(s->pclk)) {
> + error_setg(errp, "CMSDK APB timer: pclk clock must be connected");
> return;
> }
>
> @@ -232,7 +242,7 @@ static void cmsdk_apb_timer_realize(DeviceState *dev, Error **errp)
> PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
>
> ptimer_transaction_begin(s->timer);
> - ptimer_set_freq(s->timer, s->pclk_frq);
> + ptimer_set_period_from_clock(s->timer, s->pclk, 1);
> ptimer_transaction_commit(s->timer);
> }
>
> --
> 2.20.1
>
--
^ permalink raw reply [flat|nested] 80+ messages in thread
* [PATCH 19/25] hw/timer/cmsdk-apb-dualtimer: Convert to use Clock input
2021-01-21 19:05 [PATCH 00/25] Convert CMSDK timer, watchdog, dualtimer to Clock framework Peter Maydell
` (17 preceding siblings ...)
2021-01-21 19:06 ` [PATCH 18/25] hw/timer/cmsdk-apb-timer: Convert to use Clock input Peter Maydell
@ 2021-01-21 19:06 ` Peter Maydell
2021-01-22 20:49 ` Luc Michel
2021-01-27 22:00 ` Philippe Mathieu-Daudé
2021-01-21 19:06 ` [PATCH 20/25] hw/watchdog/cmsdk-apb-watchdog: " Peter Maydell
` (5 subsequent siblings)
24 siblings, 2 replies; 80+ messages in thread
From: Peter Maydell @ 2021-01-21 19:06 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Philippe Mathieu-Daudé
Switch the CMSDK APB dualtimer device over to using its Clock input;
the pclk-frq property is now ignored.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/timer/cmsdk-apb-dualtimer.c | 42 ++++++++++++++++++++++++++++++----
1 file changed, 37 insertions(+), 5 deletions(-)
diff --git a/hw/timer/cmsdk-apb-dualtimer.c b/hw/timer/cmsdk-apb-dualtimer.c
index 781b496037b..828127b366f 100644
--- a/hw/timer/cmsdk-apb-dualtimer.c
+++ b/hw/timer/cmsdk-apb-dualtimer.c
@@ -106,6 +106,22 @@ static void cmsdk_apb_dualtimer_update(CMSDKAPBDualTimer *s)
qemu_set_irq(s->timerintc, timintc);
}
+static int cmsdk_dualtimermod_divisor(CMSDKAPBDualTimerModule *m)
+{
+ /* Return the divisor set by the current CONTROL.PRESCALE value */
+ switch (FIELD_EX32(m->control, CONTROL, PRESCALE)) {
+ case 0:
+ return 1;
+ case 1:
+ return 16;
+ case 2:
+ case 3: /* UNDEFINED, we treat like 2 (and complained when it was set) */
+ return 256;
+ default:
+ g_assert_not_reached();
+ }
+}
+
static void cmsdk_dualtimermod_write_control(CMSDKAPBDualTimerModule *m,
uint32_t newctrl)
{
@@ -146,7 +162,7 @@ static void cmsdk_dualtimermod_write_control(CMSDKAPBDualTimerModule *m,
default:
g_assert_not_reached();
}
- ptimer_set_freq(m->timer, m->parent->pclk_frq / divisor);
+ ptimer_set_period_from_clock(m->timer, m->parent->timclk, divisor);
}
if (changed & R_CONTROL_MODE_MASK) {
@@ -414,7 +430,8 @@ static void cmsdk_dualtimermod_reset(CMSDKAPBDualTimerModule *m)
* limit must both be set to 0xffff, so we wrap at 16 bits.
*/
ptimer_set_limit(m->timer, 0xffff, 1);
- ptimer_set_freq(m->timer, m->parent->pclk_frq);
+ ptimer_set_period_from_clock(m->timer, m->parent->timclk,
+ cmsdk_dualtimermod_divisor(m));
ptimer_transaction_commit(m->timer);
}
@@ -432,6 +449,20 @@ static void cmsdk_apb_dualtimer_reset(DeviceState *dev)
s->timeritop = 0;
}
+static void cmsdk_apb_dualtimer_clk_update(void *opaque)
+{
+ CMSDKAPBDualTimer *s = CMSDK_APB_DUALTIMER(opaque);
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(s->timermod); i++) {
+ CMSDKAPBDualTimerModule *m = &s->timermod[i];
+ ptimer_transaction_begin(m->timer);
+ ptimer_set_period_from_clock(m->timer, m->parent->timclk,
+ cmsdk_dualtimermod_divisor(m));
+ ptimer_transaction_commit(m->timer);
+ }
+}
+
static void cmsdk_apb_dualtimer_init(Object *obj)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
@@ -446,7 +477,8 @@ static void cmsdk_apb_dualtimer_init(Object *obj)
for (i = 0; i < ARRAY_SIZE(s->timermod); i++) {
sysbus_init_irq(sbd, &s->timermod[i].timerint);
}
- s->timclk = qdev_init_clock_in(DEVICE(s), "TIMCLK", NULL, NULL);
+ s->timclk = qdev_init_clock_in(DEVICE(s), "TIMCLK",
+ cmsdk_apb_dualtimer_clk_update, s);
}
static void cmsdk_apb_dualtimer_realize(DeviceState *dev, Error **errp)
@@ -454,8 +486,8 @@ static void cmsdk_apb_dualtimer_realize(DeviceState *dev, Error **errp)
CMSDKAPBDualTimer *s = CMSDK_APB_DUALTIMER(dev);
int i;
- if (s->pclk_frq == 0) {
- error_setg(errp, "CMSDK APB timer: pclk-frq property must be set");
+ if (!clock_has_source(s->timclk)) {
+ error_setg(errp, "CMSDK APB dualtimer: TIMCLK clock must be connected");
return;
}
--
2.20.1
^ permalink raw reply related [flat|nested] 80+ messages in thread* Re: [PATCH 19/25] hw/timer/cmsdk-apb-dualtimer: Convert to use Clock input
2021-01-21 19:06 ` [PATCH 19/25] hw/timer/cmsdk-apb-dualtimer: " Peter Maydell
@ 2021-01-22 20:49 ` Luc Michel
2021-01-22 21:41 ` Peter Maydell
2021-01-27 22:00 ` Philippe Mathieu-Daudé
1 sibling, 1 reply; 80+ messages in thread
From: Luc Michel @ 2021-01-22 20:49 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, qemu-arm, qemu-devel, Philippe Mathieu-Daudé
On 19:06 Thu 21 Jan , Peter Maydell wrote:
> Switch the CMSDK APB dualtimer device over to using its Clock input;
> the pclk-frq property is now ignored.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> hw/timer/cmsdk-apb-dualtimer.c | 42 ++++++++++++++++++++++++++++++----
> 1 file changed, 37 insertions(+), 5 deletions(-)
>
> diff --git a/hw/timer/cmsdk-apb-dualtimer.c b/hw/timer/cmsdk-apb-dualtimer.c
> index 781b496037b..828127b366f 100644
> --- a/hw/timer/cmsdk-apb-dualtimer.c
> +++ b/hw/timer/cmsdk-apb-dualtimer.c
> @@ -106,6 +106,22 @@ static void cmsdk_apb_dualtimer_update(CMSDKAPBDualTimer *s)
> qemu_set_irq(s->timerintc, timintc);
> }
>
> +static int cmsdk_dualtimermod_divisor(CMSDKAPBDualTimerModule *m)
> +{
> + /* Return the divisor set by the current CONTROL.PRESCALE value */
> + switch (FIELD_EX32(m->control, CONTROL, PRESCALE)) {
> + case 0:
> + return 1;
> + case 1:
> + return 16;
> + case 2:
> + case 3: /* UNDEFINED, we treat like 2 (and complained when it was set) */
> + return 256;
> + default:
> + g_assert_not_reached();
> + }
> +}
> +
> static void cmsdk_dualtimermod_write_control(CMSDKAPBDualTimerModule *m,
> uint32_t newctrl)
> {
> @@ -146,7 +162,7 @@ static void cmsdk_dualtimermod_write_control(CMSDKAPBDualTimerModule *m,
> default:
> g_assert_not_reached();
> }
> - ptimer_set_freq(m->timer, m->parent->pclk_frq / divisor);
> + ptimer_set_period_from_clock(m->timer, m->parent->timclk, divisor);
Just a small cosmetic note, maybe you can use your new
cmsdk_dualtimermod_divisor function to factor out the switch above?
Something like:
if (changed & R_CONTROL_PRESCALE_MASK) {
if (FIELD_EX32(newctrl, CONTROL, PRESCALE) == 3) {
qemu_log_mask(LOG_GUEST_ERROR,
"CMSDK APB dual-timer: CONTROL.PRESCALE==0b11"
" is undefined behaviour\n");
}
ptimer_set_period_from_clock(m->timer, m->parent->timclk,
cmsdk_dualtimermod_divisor(m));
}
With or without this modification:
Reviewed-by: Luc Michel <luc@lmichel.fr>
Luc
> }
>
> if (changed & R_CONTROL_MODE_MASK) {
> @@ -414,7 +430,8 @@ static void cmsdk_dualtimermod_reset(CMSDKAPBDualTimerModule *m)
> * limit must both be set to 0xffff, so we wrap at 16 bits.
> */
> ptimer_set_limit(m->timer, 0xffff, 1);
> - ptimer_set_freq(m->timer, m->parent->pclk_frq);
> + ptimer_set_period_from_clock(m->timer, m->parent->timclk,
> + cmsdk_dualtimermod_divisor(m));
> ptimer_transaction_commit(m->timer);
> }
>
> @@ -432,6 +449,20 @@ static void cmsdk_apb_dualtimer_reset(DeviceState *dev)
> s->timeritop = 0;
> }
>
> +static void cmsdk_apb_dualtimer_clk_update(void *opaque)
> +{
> + CMSDKAPBDualTimer *s = CMSDK_APB_DUALTIMER(opaque);
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(s->timermod); i++) {
> + CMSDKAPBDualTimerModule *m = &s->timermod[i];
> + ptimer_transaction_begin(m->timer);
> + ptimer_set_period_from_clock(m->timer, m->parent->timclk,
> + cmsdk_dualtimermod_divisor(m));
> + ptimer_transaction_commit(m->timer);
> + }
> +}
> +
> static void cmsdk_apb_dualtimer_init(Object *obj)
> {
> SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
> @@ -446,7 +477,8 @@ static void cmsdk_apb_dualtimer_init(Object *obj)
> for (i = 0; i < ARRAY_SIZE(s->timermod); i++) {
> sysbus_init_irq(sbd, &s->timermod[i].timerint);
> }
> - s->timclk = qdev_init_clock_in(DEVICE(s), "TIMCLK", NULL, NULL);
> + s->timclk = qdev_init_clock_in(DEVICE(s), "TIMCLK",
> + cmsdk_apb_dualtimer_clk_update, s);
> }
>
> static void cmsdk_apb_dualtimer_realize(DeviceState *dev, Error **errp)
> @@ -454,8 +486,8 @@ static void cmsdk_apb_dualtimer_realize(DeviceState *dev, Error **errp)
> CMSDKAPBDualTimer *s = CMSDK_APB_DUALTIMER(dev);
> int i;
>
> - if (s->pclk_frq == 0) {
> - error_setg(errp, "CMSDK APB timer: pclk-frq property must be set");
> + if (!clock_has_source(s->timclk)) {
> + error_setg(errp, "CMSDK APB dualtimer: TIMCLK clock must be connected");
> return;
> }
>
> --
> 2.20.1
>
--
^ permalink raw reply [flat|nested] 80+ messages in thread* Re: [PATCH 19/25] hw/timer/cmsdk-apb-dualtimer: Convert to use Clock input
2021-01-22 20:49 ` Luc Michel
@ 2021-01-22 21:41 ` Peter Maydell
2021-01-23 19:58 ` Luc Michel
0 siblings, 1 reply; 80+ messages in thread
From: Peter Maydell @ 2021-01-22 21:41 UTC (permalink / raw)
To: Luc Michel
Cc: Damien Hedde, qemu-arm, QEMU Developers, Philippe Mathieu-Daudé
On Fri, 22 Jan 2021 at 20:48, Luc Michel <luc@lmichel.fr> wrote:
>
> On 19:06 Thu 21 Jan , Peter Maydell wrote:
> > Switch the CMSDK APB dualtimer device over to using its Clock input;
> > the pclk-frq property is now ignored.
> >
> > Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> > ---
> > hw/timer/cmsdk-apb-dualtimer.c | 42 ++++++++++++++++++++++++++++++----
> > 1 file changed, 37 insertions(+), 5 deletions(-)
> >
> > diff --git a/hw/timer/cmsdk-apb-dualtimer.c b/hw/timer/cmsdk-apb-dualtimer.c
> > index 781b496037b..828127b366f 100644
> > --- a/hw/timer/cmsdk-apb-dualtimer.c
> > +++ b/hw/timer/cmsdk-apb-dualtimer.c
> > @@ -106,6 +106,22 @@ static void cmsdk_apb_dualtimer_update(CMSDKAPBDualTimer *s)
> > qemu_set_irq(s->timerintc, timintc);
> > }
> >
> > +static int cmsdk_dualtimermod_divisor(CMSDKAPBDualTimerModule *m)
> > +{
> > + /* Return the divisor set by the current CONTROL.PRESCALE value */
> > + switch (FIELD_EX32(m->control, CONTROL, PRESCALE)) {
> > + case 0:
> > + return 1;
> > + case 1:
> > + return 16;
> > + case 2:
> > + case 3: /* UNDEFINED, we treat like 2 (and complained when it was set) */
> > + return 256;
> > + default:
> > + g_assert_not_reached();
> > + }
> > +}
> > +
> > static void cmsdk_dualtimermod_write_control(CMSDKAPBDualTimerModule *m,
> > uint32_t newctrl)
> > {
> > @@ -146,7 +162,7 @@ static void cmsdk_dualtimermod_write_control(CMSDKAPBDualTimerModule *m,
> > default:
> > g_assert_not_reached();
> > }
> > - ptimer_set_freq(m->timer, m->parent->pclk_frq / divisor);
> > + ptimer_set_period_from_clock(m->timer, m->parent->timclk, divisor);
>
> Just a small cosmetic note, maybe you can use your new
> cmsdk_dualtimermod_divisor function to factor out the switch above?
> Something like:
>
> if (changed & R_CONTROL_PRESCALE_MASK) {
> if (FIELD_EX32(newctrl, CONTROL, PRESCALE) == 3) {
> qemu_log_mask(LOG_GUEST_ERROR,
> "CMSDK APB dual-timer: CONTROL.PRESCALE==0b11"
> " is undefined behaviour\n");
> }
>
> ptimer_set_period_from_clock(m->timer, m->parent->timclk,
> cmsdk_dualtimermod_divisor(m));
> }
Nope, because cmsdk_dualtimermod_divisor() uses the current
m->control value, and at this point in the code we need the
divisor from the new control value which isn't in m->control yet.
I liked the slight duplication better than either having to
pass m->control in in all the other callsites or trying to
refactor the control write handling so that m->control is
updated before this point in the code.
thanks
-- PMM
^ permalink raw reply [flat|nested] 80+ messages in thread* Re: [PATCH 19/25] hw/timer/cmsdk-apb-dualtimer: Convert to use Clock input
2021-01-22 21:41 ` Peter Maydell
@ 2021-01-23 19:58 ` Luc Michel
0 siblings, 0 replies; 80+ messages in thread
From: Luc Michel @ 2021-01-23 19:58 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, qemu-arm, QEMU Developers, Philippe Mathieu-Daudé
On 21:41 Fri 22 Jan , Peter Maydell wrote:
> On Fri, 22 Jan 2021 at 20:48, Luc Michel <luc@lmichel.fr> wrote:
> >
> > On 19:06 Thu 21 Jan , Peter Maydell wrote:
> > > Switch the CMSDK APB dualtimer device over to using its Clock input;
> > > the pclk-frq property is now ignored.
> > >
> > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> > > ---
> > > hw/timer/cmsdk-apb-dualtimer.c | 42 ++++++++++++++++++++++++++++++----
> > > 1 file changed, 37 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/hw/timer/cmsdk-apb-dualtimer.c b/hw/timer/cmsdk-apb-dualtimer.c
> > > index 781b496037b..828127b366f 100644
> > > --- a/hw/timer/cmsdk-apb-dualtimer.c
> > > +++ b/hw/timer/cmsdk-apb-dualtimer.c
> > > @@ -106,6 +106,22 @@ static void cmsdk_apb_dualtimer_update(CMSDKAPBDualTimer *s)
> > > qemu_set_irq(s->timerintc, timintc);
> > > }
> > >
> > > +static int cmsdk_dualtimermod_divisor(CMSDKAPBDualTimerModule *m)
> > > +{
> > > + /* Return the divisor set by the current CONTROL.PRESCALE value */
> > > + switch (FIELD_EX32(m->control, CONTROL, PRESCALE)) {
> > > + case 0:
> > > + return 1;
> > > + case 1:
> > > + return 16;
> > > + case 2:
> > > + case 3: /* UNDEFINED, we treat like 2 (and complained when it was set) */
> > > + return 256;
> > > + default:
> > > + g_assert_not_reached();
> > > + }
> > > +}
> > > +
> > > static void cmsdk_dualtimermod_write_control(CMSDKAPBDualTimerModule *m,
> > > uint32_t newctrl)
> > > {
> > > @@ -146,7 +162,7 @@ static void cmsdk_dualtimermod_write_control(CMSDKAPBDualTimerModule *m,
> > > default:
> > > g_assert_not_reached();
> > > }
> > > - ptimer_set_freq(m->timer, m->parent->pclk_frq / divisor);
> > > + ptimer_set_period_from_clock(m->timer, m->parent->timclk, divisor);
> >
> > Just a small cosmetic note, maybe you can use your new
> > cmsdk_dualtimermod_divisor function to factor out the switch above?
> > Something like:
> >
> > if (changed & R_CONTROL_PRESCALE_MASK) {
> > if (FIELD_EX32(newctrl, CONTROL, PRESCALE) == 3) {
> > qemu_log_mask(LOG_GUEST_ERROR,
> > "CMSDK APB dual-timer: CONTROL.PRESCALE==0b11"
> > " is undefined behaviour\n");
> > }
> >
> > ptimer_set_period_from_clock(m->timer, m->parent->timclk,
> > cmsdk_dualtimermod_divisor(m));
> > }
>
> Nope, because cmsdk_dualtimermod_divisor() uses the current
> m->control value, and at this point in the code we need the
> divisor from the new control value which isn't in m->control yet.
> I liked the slight duplication better than either having to
> pass m->control in in all the other callsites or trying to
> refactor the control write handling so that m->control is
> updated before this point in the code.
Oops yes I missed that. Sure make sense, forget what I said.
>
> thanks
> -- PMM
--
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 19/25] hw/timer/cmsdk-apb-dualtimer: Convert to use Clock input
2021-01-21 19:06 ` [PATCH 19/25] hw/timer/cmsdk-apb-dualtimer: " Peter Maydell
2021-01-22 20:49 ` Luc Michel
@ 2021-01-27 22:00 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 80+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-27 22:00 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel; +Cc: Damien Hedde, Luc Michel
On 1/21/21 8:06 PM, Peter Maydell wrote:
> Switch the CMSDK APB dualtimer device over to using its Clock input;
> the pclk-frq property is now ignored.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> hw/timer/cmsdk-apb-dualtimer.c | 42 ++++++++++++++++++++++++++++++----
> 1 file changed, 37 insertions(+), 5 deletions(-)
...
> @@ -454,8 +486,8 @@ static void cmsdk_apb_dualtimer_realize(DeviceState *dev, Error **errp)
> CMSDKAPBDualTimer *s = CMSDK_APB_DUALTIMER(dev);
> int i;
>
> - if (s->pclk_frq == 0) {
> - error_setg(errp, "CMSDK APB timer: pclk-frq property must be set");
> + if (!clock_has_source(s->timclk)) {
> + error_setg(errp, "CMSDK APB dualtimer: TIMCLK clock must be connected");
> return;
> }
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 80+ messages in thread
* [PATCH 20/25] hw/watchdog/cmsdk-apb-watchdog: Convert to use Clock input
2021-01-21 19:05 [PATCH 00/25] Convert CMSDK timer, watchdog, dualtimer to Clock framework Peter Maydell
` (18 preceding siblings ...)
2021-01-21 19:06 ` [PATCH 19/25] hw/timer/cmsdk-apb-dualtimer: " Peter Maydell
@ 2021-01-21 19:06 ` Peter Maydell
2021-01-21 22:01 ` Philippe Mathieu-Daudé
2021-01-22 20:51 ` Luc Michel
2021-01-21 19:06 ` [PATCH 21/25] tests/qtest/cmsdk-apb-watchdog-test: Test clock changes Peter Maydell
` (4 subsequent siblings)
24 siblings, 2 replies; 80+ messages in thread
From: Peter Maydell @ 2021-01-21 19:06 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Philippe Mathieu-Daudé
Switch the CMSDK APB watchdog device over to using its Clock input;
the wdogclk_frq property is now ignored.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/watchdog/cmsdk-apb-watchdog.c | 18 ++++++++++++++----
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watchdog.c
index b03bcb73628..9cad0c67da4 100644
--- a/hw/watchdog/cmsdk-apb-watchdog.c
+++ b/hw/watchdog/cmsdk-apb-watchdog.c
@@ -310,6 +310,15 @@ static void cmsdk_apb_watchdog_reset(DeviceState *dev)
ptimer_transaction_commit(s->timer);
}
+static void cmsdk_apb_watchdog_clk_update(void *opaque)
+{
+ CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(opaque);
+
+ ptimer_transaction_begin(s->timer);
+ ptimer_set_period_from_clock(s->timer, s->wdogclk, 1);
+ ptimer_transaction_commit(s->timer);
+}
+
static void cmsdk_apb_watchdog_init(Object *obj)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
@@ -319,7 +328,8 @@ static void cmsdk_apb_watchdog_init(Object *obj)
s, "cmsdk-apb-watchdog", 0x1000);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->wdogint);
- s->wdogclk = qdev_init_clock_in(DEVICE(s), "WDOGCLK", NULL, NULL);
+ s->wdogclk = qdev_init_clock_in(DEVICE(s), "WDOGCLK",
+ cmsdk_apb_watchdog_clk_update, s);
s->is_luminary = false;
s->id = cmsdk_apb_watchdog_id;
@@ -329,9 +339,9 @@ static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp)
{
CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(dev);
- if (s->wdogclk_frq == 0) {
+ if (!clock_has_source(s->wdogclk)) {
error_setg(errp,
- "CMSDK APB watchdog: wdogclk-frq property must be set");
+ "CMSDK APB watchdog: WDOGCLK clock must be connected");
return;
}
@@ -342,7 +352,7 @@ static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp)
PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
ptimer_transaction_begin(s->timer);
- ptimer_set_freq(s->timer, s->wdogclk_frq);
+ ptimer_set_period_from_clock(s->timer, s->wdogclk, 1);
ptimer_transaction_commit(s->timer);
}
--
2.20.1
^ permalink raw reply related [flat|nested] 80+ messages in thread* Re: [PATCH 20/25] hw/watchdog/cmsdk-apb-watchdog: Convert to use Clock input
2021-01-21 19:06 ` [PATCH 20/25] hw/watchdog/cmsdk-apb-watchdog: " Peter Maydell
@ 2021-01-21 22:01 ` Philippe Mathieu-Daudé
2021-01-22 20:51 ` Luc Michel
1 sibling, 0 replies; 80+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-21 22:01 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel; +Cc: Damien Hedde, Luc Michel
On 1/21/21 8:06 PM, Peter Maydell wrote:
> Switch the CMSDK APB watchdog device over to using its Clock input;
> the wdogclk_frq property is now ignored.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> hw/watchdog/cmsdk-apb-watchdog.c | 18 ++++++++++++++----
> 1 file changed, 14 insertions(+), 4 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 20/25] hw/watchdog/cmsdk-apb-watchdog: Convert to use Clock input
2021-01-21 19:06 ` [PATCH 20/25] hw/watchdog/cmsdk-apb-watchdog: " Peter Maydell
2021-01-21 22:01 ` Philippe Mathieu-Daudé
@ 2021-01-22 20:51 ` Luc Michel
1 sibling, 0 replies; 80+ messages in thread
From: Luc Michel @ 2021-01-22 20:51 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, qemu-arm, qemu-devel, Philippe Mathieu-Daudé
On 19:06 Thu 21 Jan , Peter Maydell wrote:
> Switch the CMSDK APB watchdog device over to using its Clock input;
> the wdogclk_frq property is now ignored.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
> ---
> hw/watchdog/cmsdk-apb-watchdog.c | 18 ++++++++++++++----
> 1 file changed, 14 insertions(+), 4 deletions(-)
>
> diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watchdog.c
> index b03bcb73628..9cad0c67da4 100644
> --- a/hw/watchdog/cmsdk-apb-watchdog.c
> +++ b/hw/watchdog/cmsdk-apb-watchdog.c
> @@ -310,6 +310,15 @@ static void cmsdk_apb_watchdog_reset(DeviceState *dev)
> ptimer_transaction_commit(s->timer);
> }
>
> +static void cmsdk_apb_watchdog_clk_update(void *opaque)
> +{
> + CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(opaque);
> +
> + ptimer_transaction_begin(s->timer);
> + ptimer_set_period_from_clock(s->timer, s->wdogclk, 1);
> + ptimer_transaction_commit(s->timer);
> +}
> +
> static void cmsdk_apb_watchdog_init(Object *obj)
> {
> SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
> @@ -319,7 +328,8 @@ static void cmsdk_apb_watchdog_init(Object *obj)
> s, "cmsdk-apb-watchdog", 0x1000);
> sysbus_init_mmio(sbd, &s->iomem);
> sysbus_init_irq(sbd, &s->wdogint);
> - s->wdogclk = qdev_init_clock_in(DEVICE(s), "WDOGCLK", NULL, NULL);
> + s->wdogclk = qdev_init_clock_in(DEVICE(s), "WDOGCLK",
> + cmsdk_apb_watchdog_clk_update, s);
>
> s->is_luminary = false;
> s->id = cmsdk_apb_watchdog_id;
> @@ -329,9 +339,9 @@ static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp)
> {
> CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(dev);
>
> - if (s->wdogclk_frq == 0) {
> + if (!clock_has_source(s->wdogclk)) {
> error_setg(errp,
> - "CMSDK APB watchdog: wdogclk-frq property must be set");
> + "CMSDK APB watchdog: WDOGCLK clock must be connected");
> return;
> }
>
> @@ -342,7 +352,7 @@ static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp)
> PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
>
> ptimer_transaction_begin(s->timer);
> - ptimer_set_freq(s->timer, s->wdogclk_frq);
> + ptimer_set_period_from_clock(s->timer, s->wdogclk, 1);
> ptimer_transaction_commit(s->timer);
> }
>
> --
> 2.20.1
>
--
^ permalink raw reply [flat|nested] 80+ messages in thread
* [PATCH 21/25] tests/qtest/cmsdk-apb-watchdog-test: Test clock changes
2021-01-21 19:05 [PATCH 00/25] Convert CMSDK timer, watchdog, dualtimer to Clock framework Peter Maydell
` (19 preceding siblings ...)
2021-01-21 19:06 ` [PATCH 20/25] hw/watchdog/cmsdk-apb-watchdog: " Peter Maydell
@ 2021-01-21 19:06 ` Peter Maydell
2021-01-21 22:04 ` Philippe Mathieu-Daudé
2021-01-24 13:35 ` Luc Michel
2021-01-21 19:06 ` [PATCH 22/25] hw/arm/armsse: Use Clock to set system_clock_scale Peter Maydell
` (3 subsequent siblings)
24 siblings, 2 replies; 80+ messages in thread
From: Peter Maydell @ 2021-01-21 19:06 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Philippe Mathieu-Daudé
Now that the CMSDK APB watchdog uses its Clock input, it will
correctly respond when the system clock frequency is changed using
the RCC register on in the Stellaris board system registers. Test
that when the RCC register is written it causes the watchdog timer to
change speed.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
tests/qtest/cmsdk-apb-watchdog-test.c | 52 +++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/tests/qtest/cmsdk-apb-watchdog-test.c b/tests/qtest/cmsdk-apb-watchdog-test.c
index c6add1fee85..9a4873a8314 100644
--- a/tests/qtest/cmsdk-apb-watchdog-test.c
+++ b/tests/qtest/cmsdk-apb-watchdog-test.c
@@ -15,6 +15,7 @@
*/
#include "qemu/osdep.h"
+#include "qemu/bitops.h"
#include "libqtest-single.h"
/*
@@ -31,6 +32,11 @@
#define WDOGMIS 0x14
#define WDOGLOCK 0xc00
+#define SSYS_BASE 0x400fe000
+#define RCC 0x60
+#define SYSDIV_SHIFT 23
+#define SYSDIV_LENGTH 4
+
static void test_watchdog(void)
{
g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
@@ -61,6 +67,50 @@ static void test_watchdog(void)
g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
}
+static void test_clock_change(void)
+{
+ uint32_t rcc;
+
+ /*
+ * Test that writing to the stellaris board's RCC register to
+ * change the system clock frequency causes the watchdog
+ * to change the speed it counts at.
+ */
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
+
+ writel(WDOG_BASE + WDOGCONTROL, 1);
+ writel(WDOG_BASE + WDOGLOAD, 1000);
+
+ /* Step to just past the 500th tick */
+ clock_step(80 * 500 + 1);
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500);
+
+ /* Rewrite RCC.SYSDIV from 16 to 8, so the clock is now 40ns per tick */
+ rcc = readl(SSYS_BASE + RCC);
+ g_assert_cmpuint(extract32(rcc, SYSDIV_SHIFT, SYSDIV_LENGTH), ==, 0xf);
+ rcc = deposit32(rcc, SYSDIV_SHIFT, SYSDIV_LENGTH, 7);
+ writel(SSYS_BASE + RCC, rcc);
+
+ /* Just past the 1000th tick: timer should have fired */
+ clock_step(40 * 500);
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1);
+
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 0);
+
+ /* VALUE reloads at following tick */
+ clock_step(41);
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000);
+
+ /* Writing any value to WDOGINTCLR clears the interrupt and reloads */
+ clock_step(40 * 500);
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500);
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1);
+ writel(WDOG_BASE + WDOGINTCLR, 0);
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000);
+ g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
+}
+
int main(int argc, char **argv)
{
QTestState *s;
@@ -71,6 +121,8 @@ int main(int argc, char **argv)
s = qtest_start("-machine lm3s811evb");
qtest_add_func("/cmsdk-apb-watchdog/watchdog", test_watchdog);
+ qtest_add_func("/cmsdk-apb-watchdog/watchdog_clock_change",
+ test_clock_change);
r = g_test_run();
--
2.20.1
^ permalink raw reply related [flat|nested] 80+ messages in thread* Re: [PATCH 21/25] tests/qtest/cmsdk-apb-watchdog-test: Test clock changes
2021-01-21 19:06 ` [PATCH 21/25] tests/qtest/cmsdk-apb-watchdog-test: Test clock changes Peter Maydell
@ 2021-01-21 22:04 ` Philippe Mathieu-Daudé
2021-01-24 13:35 ` Luc Michel
1 sibling, 0 replies; 80+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-21 22:04 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel; +Cc: Damien Hedde, Luc Michel
On 1/21/21 8:06 PM, Peter Maydell wrote:
> Now that the CMSDK APB watchdog uses its Clock input, it will
> correctly respond when the system clock frequency is changed using
> the RCC register on in the Stellaris board system registers. Test
> that when the RCC register is written it causes the watchdog timer to
> change speed.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> tests/qtest/cmsdk-apb-watchdog-test.c | 52 +++++++++++++++++++++++++++
> 1 file changed, 52 insertions(+)
...
> +static void test_clock_change(void)
> +{
> + uint32_t rcc;
> +
> + /*
> + * Test that writing to the stellaris board's RCC register to
> + * change the system clock frequency causes the watchdog
> + * to change the speed it counts at.
> + */
> + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
> +
> + writel(WDOG_BASE + WDOGCONTROL, 1);
> + writel(WDOG_BASE + WDOGLOAD, 1000);
> +
> + /* Step to just past the 500th tick */
> + clock_step(80 * 500 + 1);
I was wondering about asking you to change that 40000 in patch #3.
Since you use that clearer form here, it would be nice to have it
in #3 too.
Otherwise,
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 80+ messages in thread* Re: [PATCH 21/25] tests/qtest/cmsdk-apb-watchdog-test: Test clock changes
2021-01-21 19:06 ` [PATCH 21/25] tests/qtest/cmsdk-apb-watchdog-test: Test clock changes Peter Maydell
2021-01-21 22:04 ` Philippe Mathieu-Daudé
@ 2021-01-24 13:35 ` Luc Michel
1 sibling, 0 replies; 80+ messages in thread
From: Luc Michel @ 2021-01-24 13:35 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, qemu-arm, qemu-devel, Philippe Mathieu-Daudé
On 19:06 Thu 21 Jan , Peter Maydell wrote:
> Now that the CMSDK APB watchdog uses its Clock input, it will
> correctly respond when the system clock frequency is changed using
> the RCC register on in the Stellaris board system registers. Test
> that when the RCC register is written it causes the watchdog timer to
> change speed.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
> ---
> tests/qtest/cmsdk-apb-watchdog-test.c | 52 +++++++++++++++++++++++++++
> 1 file changed, 52 insertions(+)
>
> diff --git a/tests/qtest/cmsdk-apb-watchdog-test.c b/tests/qtest/cmsdk-apb-watchdog-test.c
> index c6add1fee85..9a4873a8314 100644
> --- a/tests/qtest/cmsdk-apb-watchdog-test.c
> +++ b/tests/qtest/cmsdk-apb-watchdog-test.c
> @@ -15,6 +15,7 @@
> */
>
> #include "qemu/osdep.h"
> +#include "qemu/bitops.h"
> #include "libqtest-single.h"
>
> /*
> @@ -31,6 +32,11 @@
> #define WDOGMIS 0x14
> #define WDOGLOCK 0xc00
>
> +#define SSYS_BASE 0x400fe000
> +#define RCC 0x60
> +#define SYSDIV_SHIFT 23
> +#define SYSDIV_LENGTH 4
> +
> static void test_watchdog(void)
> {
> g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
> @@ -61,6 +67,50 @@ static void test_watchdog(void)
> g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
> }
>
> +static void test_clock_change(void)
> +{
> + uint32_t rcc;
> +
> + /*
> + * Test that writing to the stellaris board's RCC register to
> + * change the system clock frequency causes the watchdog
> + * to change the speed it counts at.
> + */
> + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
> +
> + writel(WDOG_BASE + WDOGCONTROL, 1);
> + writel(WDOG_BASE + WDOGLOAD, 1000);
> +
> + /* Step to just past the 500th tick */
> + clock_step(80 * 500 + 1);
> + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
> + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500);
> +
> + /* Rewrite RCC.SYSDIV from 16 to 8, so the clock is now 40ns per tick */
> + rcc = readl(SSYS_BASE + RCC);
> + g_assert_cmpuint(extract32(rcc, SYSDIV_SHIFT, SYSDIV_LENGTH), ==, 0xf);
> + rcc = deposit32(rcc, SYSDIV_SHIFT, SYSDIV_LENGTH, 7);
> + writel(SSYS_BASE + RCC, rcc);
> +
> + /* Just past the 1000th tick: timer should have fired */
> + clock_step(40 * 500);
> + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1);
> +
> + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 0);
> +
> + /* VALUE reloads at following tick */
> + clock_step(41);
> + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000);
> +
> + /* Writing any value to WDOGINTCLR clears the interrupt and reloads */
> + clock_step(40 * 500);
> + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500);
> + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1);
> + writel(WDOG_BASE + WDOGINTCLR, 0);
> + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000);
> + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0);
> +}
> +
> int main(int argc, char **argv)
> {
> QTestState *s;
> @@ -71,6 +121,8 @@ int main(int argc, char **argv)
> s = qtest_start("-machine lm3s811evb");
>
> qtest_add_func("/cmsdk-apb-watchdog/watchdog", test_watchdog);
> + qtest_add_func("/cmsdk-apb-watchdog/watchdog_clock_change",
> + test_clock_change);
>
> r = g_test_run();
>
> --
> 2.20.1
>
--
^ permalink raw reply [flat|nested] 80+ messages in thread
* [PATCH 22/25] hw/arm/armsse: Use Clock to set system_clock_scale
2021-01-21 19:05 [PATCH 00/25] Convert CMSDK timer, watchdog, dualtimer to Clock framework Peter Maydell
` (20 preceding siblings ...)
2021-01-21 19:06 ` [PATCH 21/25] tests/qtest/cmsdk-apb-watchdog-test: Test clock changes Peter Maydell
@ 2021-01-21 19:06 ` Peter Maydell
2021-01-21 22:05 ` Philippe Mathieu-Daudé
2021-01-23 20:31 ` Luc Michel
2021-01-21 19:06 ` [PATCH 23/25] arm: Don't set freq properties on CMSDK timer, dualtimer, watchdog, ARMSSE Peter Maydell
` (2 subsequent siblings)
24 siblings, 2 replies; 80+ messages in thread
From: Peter Maydell @ 2021-01-21 19:06 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Philippe Mathieu-Daudé
Use the MAINCLK Clock input to set the system_clock_scale variable
rather than using the mainclk_frq property.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
At some point we should make the SysTick take a Clock itself so
that we can get rid of the system_clock_scale global entirely.
(In fact we want two Clocks: one that is the CPU clock and one
for the 'external reference clock' whose period is currently
hardcoded at 1000ns in systick_scale()...)
---
hw/arm/armsse.c | 21 +++++++++++++++++----
1 file changed, 17 insertions(+), 4 deletions(-)
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
index 4349ce9bfdb..1da0c1be4c7 100644
--- a/hw/arm/armsse.c
+++ b/hw/arm/armsse.c
@@ -232,6 +232,16 @@ static void armsse_forward_sec_resp_cfg(ARMSSE *s)
qdev_connect_gpio_out(dev_splitter, 2, s->sec_resp_cfg_in);
}
+static void armsse_mainclk_update(void *opaque)
+{
+ ARMSSE *s = ARM_SSE(opaque);
+ /*
+ * Set system_clock_scale from our Clock input; this is what
+ * controls the tick rate of the CPU SysTick timer.
+ */
+ system_clock_scale = clock_ticks_to_ns(s->mainclk, 1);
+}
+
static void armsse_init(Object *obj)
{
ARMSSE *s = ARM_SSE(obj);
@@ -451,9 +461,11 @@ static void armsse_realize(DeviceState *dev, Error **errp)
return;
}
- if (!s->mainclk_frq) {
- error_setg(errp, "MAINCLK_FRQ property was not set");
- return;
+ if (!clock_has_source(s->mainclk)) {
+ error_setg(errp, "MAINCLK clock was not connected");
+ }
+ if (!clock_has_source(s->s32kclk)) {
+ error_setg(errp, "S32KCLK clock was not connected");
}
assert(info->num_cpus <= SSE_MAX_CPUS);
@@ -1115,7 +1127,8 @@ static void armsse_realize(DeviceState *dev, Error **errp)
*/
sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->container);
- system_clock_scale = NANOSECONDS_PER_SECOND / s->mainclk_frq;
+ /* Set initial system_clock_scale from MAINCLK */
+ armsse_mainclk_update(s);
}
static void armsse_idau_check(IDAUInterface *ii, uint32_t address,
--
2.20.1
^ permalink raw reply related [flat|nested] 80+ messages in thread* Re: [PATCH 22/25] hw/arm/armsse: Use Clock to set system_clock_scale
2021-01-21 19:06 ` [PATCH 22/25] hw/arm/armsse: Use Clock to set system_clock_scale Peter Maydell
@ 2021-01-21 22:05 ` Philippe Mathieu-Daudé
2021-01-23 20:31 ` Luc Michel
1 sibling, 0 replies; 80+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-21 22:05 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel; +Cc: Damien Hedde, Luc Michel
On 1/21/21 8:06 PM, Peter Maydell wrote:
> Use the MAINCLK Clock input to set the system_clock_scale variable
> rather than using the mainclk_frq property.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> At some point we should make the SysTick take a Clock itself so
> that we can get rid of the system_clock_scale global entirely.
> (In fact we want two Clocks: one that is the CPU clock and one
> for the 'external reference clock' whose period is currently
> hardcoded at 1000ns in systick_scale()...)
> ---
> hw/arm/armsse.c | 21 +++++++++++++++++----
> 1 file changed, 17 insertions(+), 4 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 22/25] hw/arm/armsse: Use Clock to set system_clock_scale
2021-01-21 19:06 ` [PATCH 22/25] hw/arm/armsse: Use Clock to set system_clock_scale Peter Maydell
2021-01-21 22:05 ` Philippe Mathieu-Daudé
@ 2021-01-23 20:31 ` Luc Michel
2021-01-23 22:33 ` Peter Maydell
1 sibling, 1 reply; 80+ messages in thread
From: Luc Michel @ 2021-01-23 20:31 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, qemu-arm, qemu-devel, Philippe Mathieu-Daudé
On 19:06 Thu 21 Jan , Peter Maydell wrote:
> Use the MAINCLK Clock input to set the system_clock_scale variable
> rather than using the mainclk_frq property.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> At some point we should make the SysTick take a Clock itself so
> that we can get rid of the system_clock_scale global entirely.
> (In fact we want two Clocks: one that is the CPU clock and one
> for the 'external reference clock' whose period is currently
> hardcoded at 1000ns in systick_scale()...)
> ---
> hw/arm/armsse.c | 21 +++++++++++++++++----
> 1 file changed, 17 insertions(+), 4 deletions(-)
>
> diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
> index 4349ce9bfdb..1da0c1be4c7 100644
> --- a/hw/arm/armsse.c
> +++ b/hw/arm/armsse.c
> @@ -232,6 +232,16 @@ static void armsse_forward_sec_resp_cfg(ARMSSE *s)
> qdev_connect_gpio_out(dev_splitter, 2, s->sec_resp_cfg_in);
> }
>
> +static void armsse_mainclk_update(void *opaque)
> +{
> + ARMSSE *s = ARM_SSE(opaque);
> + /*
> + * Set system_clock_scale from our Clock input; this is what
> + * controls the tick rate of the CPU SysTick timer.
> + */
> + system_clock_scale = clock_ticks_to_ns(s->mainclk, 1);
> +}
> +
I think you forgot to connect this callback to the clock itself (the
`qdev_init_clock_in` call in `armsse_init`).
Moreover on a clock change event, shouldn't the SysTick timer be
recomputed? I guess this will be better fixed in the SysTick itself once
it takes the two Clock inputs as you said.
--
Luc
> static void armsse_init(Object *obj)
> {
> ARMSSE *s = ARM_SSE(obj);
> @@ -451,9 +461,11 @@ static void armsse_realize(DeviceState *dev, Error **errp)
> return;
> }
>
> - if (!s->mainclk_frq) {
> - error_setg(errp, "MAINCLK_FRQ property was not set");
> - return;
> + if (!clock_has_source(s->mainclk)) {
> + error_setg(errp, "MAINCLK clock was not connected");
> + }
> + if (!clock_has_source(s->s32kclk)) {
> + error_setg(errp, "S32KCLK clock was not connected");
> }
>
> assert(info->num_cpus <= SSE_MAX_CPUS);
> @@ -1115,7 +1127,8 @@ static void armsse_realize(DeviceState *dev, Error **errp)
> */
> sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->container);
>
> - system_clock_scale = NANOSECONDS_PER_SECOND / s->mainclk_frq;
> + /* Set initial system_clock_scale from MAINCLK */
> + armsse_mainclk_update(s);
> }
>
> static void armsse_idau_check(IDAUInterface *ii, uint32_t address,
> --
> 2.20.1
>
--
^ permalink raw reply [flat|nested] 80+ messages in thread* Re: [PATCH 22/25] hw/arm/armsse: Use Clock to set system_clock_scale
2021-01-23 20:31 ` Luc Michel
@ 2021-01-23 22:33 ` Peter Maydell
0 siblings, 0 replies; 80+ messages in thread
From: Peter Maydell @ 2021-01-23 22:33 UTC (permalink / raw)
To: Luc Michel
Cc: Damien Hedde, qemu-arm, QEMU Developers, Philippe Mathieu-Daudé
On Sat, 23 Jan 2021 at 20:30, Luc Michel <luc@lmichel.fr> wrote:
>
> On 19:06 Thu 21 Jan , Peter Maydell wrote:
> > Use the MAINCLK Clock input to set the system_clock_scale variable
> > rather than using the mainclk_frq property.
> >
> > Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> > ---
> > At some point we should make the SysTick take a Clock itself so
> > that we can get rid of the system_clock_scale global entirely.
> > (In fact we want two Clocks: one that is the CPU clock and one
> > for the 'external reference clock' whose period is currently
> > hardcoded at 1000ns in systick_scale()...)
> > ---
> > hw/arm/armsse.c | 21 +++++++++++++++++----
> > 1 file changed, 17 insertions(+), 4 deletions(-)
> >
> > diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
> > index 4349ce9bfdb..1da0c1be4c7 100644
> > --- a/hw/arm/armsse.c
> > +++ b/hw/arm/armsse.c
> > @@ -232,6 +232,16 @@ static void armsse_forward_sec_resp_cfg(ARMSSE *s)
> > qdev_connect_gpio_out(dev_splitter, 2, s->sec_resp_cfg_in);
> > }
> >
> > +static void armsse_mainclk_update(void *opaque)
> > +{
> > + ARMSSE *s = ARM_SSE(opaque);
> > + /*
> > + * Set system_clock_scale from our Clock input; this is what
> > + * controls the tick rate of the CPU SysTick timer.
> > + */
> > + system_clock_scale = clock_ticks_to_ns(s->mainclk, 1);
> > +}
> > +
> I think you forgot to connect this callback to the clock itself (the
> `qdev_init_clock_in` call in `armsse_init`).
Whoops, yes :-) As it happens all ARMSSE users are fixed-frequency
so this doesn't make a guest-visible difference, but it was
definitely my intention that this was a clock update callback.
> Moreover on a clock change event, shouldn't the SysTick timer be
> recomputed?
Systick correctly handles the system_clock_scale global being changed
at runtime, so once this callback is actually wired up to its Clock
that should just work.
thanks
-- PMM
^ permalink raw reply [flat|nested] 80+ messages in thread
* [PATCH 23/25] arm: Don't set freq properties on CMSDK timer, dualtimer, watchdog, ARMSSE
2021-01-21 19:05 [PATCH 00/25] Convert CMSDK timer, watchdog, dualtimer to Clock framework Peter Maydell
` (21 preceding siblings ...)
2021-01-21 19:06 ` [PATCH 22/25] hw/arm/armsse: Use Clock to set system_clock_scale Peter Maydell
@ 2021-01-21 19:06 ` Peter Maydell
2021-01-21 22:06 ` Philippe Mathieu-Daudé
2021-01-23 20:32 ` Luc Michel
2021-01-21 19:06 ` [PATCH 24/25] arm: Remove frq " Peter Maydell
2021-01-21 19:06 ` [PATCH 25/25] hw/arm/stellaris: Remove board-creation reset of STELLARIS_SYS Peter Maydell
24 siblings, 2 replies; 80+ messages in thread
From: Peter Maydell @ 2021-01-21 19:06 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Philippe Mathieu-Daudé
Remove all the code that sets frequency properties on the CMSDK
timer, dualtimer and watchdog devices and on the ARMSSE SoC device:
these properties are unused now that the devices rely on their Clock
inputs instead.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/armsse.c | 7 -------
hw/arm/mps2-tz.c | 1 -
hw/arm/mps2.c | 3 ---
hw/arm/musca.c | 1 -
hw/arm/stellaris.c | 3 ---
5 files changed, 15 deletions(-)
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
index 1da0c1be4c7..7494afc630e 100644
--- a/hw/arm/armsse.c
+++ b/hw/arm/armsse.c
@@ -726,7 +726,6 @@ static void armsse_realize(DeviceState *dev, Error **errp)
* it to the appropriate PPC port; then we can realize the PPC and
* map its upstream ends to the right place in the container.
*/
- qdev_prop_set_uint32(DEVICE(&s->timer0), "pclk-frq", s->mainclk_frq);
qdev_connect_clock_in(DEVICE(&s->timer0), "pclk", s->mainclk);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer0), errp)) {
return;
@@ -737,7 +736,6 @@ static void armsse_realize(DeviceState *dev, Error **errp)
object_property_set_link(OBJECT(&s->apb_ppc0), "port[0]", OBJECT(mr),
&error_abort);
- qdev_prop_set_uint32(DEVICE(&s->timer1), "pclk-frq", s->mainclk_frq);
qdev_connect_clock_in(DEVICE(&s->timer1), "pclk", s->mainclk);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer1), errp)) {
return;
@@ -748,7 +746,6 @@ static void armsse_realize(DeviceState *dev, Error **errp)
object_property_set_link(OBJECT(&s->apb_ppc0), "port[1]", OBJECT(mr),
&error_abort);
- qdev_prop_set_uint32(DEVICE(&s->dualtimer), "pclk-frq", s->mainclk_frq);
qdev_connect_clock_in(DEVICE(&s->dualtimer), "TIMCLK", s->mainclk);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->dualtimer), errp)) {
return;
@@ -907,7 +904,6 @@ static void armsse_realize(DeviceState *dev, Error **errp)
/* Devices behind APB PPC1:
* 0x4002f000: S32K timer
*/
- qdev_prop_set_uint32(DEVICE(&s->s32ktimer), "pclk-frq", S32KCLK);
qdev_connect_clock_in(DEVICE(&s->s32ktimer), "pclk", s->s32kclk);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32ktimer), errp)) {
return;
@@ -1001,7 +997,6 @@ static void armsse_realize(DeviceState *dev, Error **errp)
qdev_connect_gpio_out(DEVICE(&s->nmi_orgate), 0,
qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI", 0));
- qdev_prop_set_uint32(DEVICE(&s->s32kwatchdog), "wdogclk-frq", S32KCLK);
qdev_connect_clock_in(DEVICE(&s->s32kwatchdog), "WDOGCLK", s->s32kclk);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32kwatchdog), errp)) {
return;
@@ -1012,7 +1007,6 @@ static void armsse_realize(DeviceState *dev, Error **errp)
/* 0x40080000 .. 0x4008ffff : ARMSSE second Base peripheral region */
- qdev_prop_set_uint32(DEVICE(&s->nswatchdog), "wdogclk-frq", s->mainclk_frq);
qdev_connect_clock_in(DEVICE(&s->nswatchdog), "WDOGCLK", s->mainclk);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->nswatchdog), errp)) {
return;
@@ -1021,7 +1015,6 @@ static void armsse_realize(DeviceState *dev, Error **errp)
armsse_get_common_irq_in(s, 1));
sysbus_mmio_map(SYS_BUS_DEVICE(&s->nswatchdog), 0, 0x40081000);
- qdev_prop_set_uint32(DEVICE(&s->swatchdog), "wdogclk-frq", s->mainclk_frq);
qdev_connect_clock_in(DEVICE(&s->swatchdog), "WDOGCLK", s->mainclk);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->swatchdog), errp)) {
return;
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index 7acdf490f28..90caa914934 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -413,7 +413,6 @@ static void mps2tz_common_init(MachineState *machine)
object_property_set_link(OBJECT(&mms->iotkit), "memory",
OBJECT(system_memory), &error_abort);
qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ);
- qdev_prop_set_uint32(iotkitdev, "MAINCLK_FRQ", SYSCLK_FRQ);
qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk);
qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk);
sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal);
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index cd1c215f941..39add416db5 100644
--- a/hw/arm/mps2.c
+++ b/hw/arm/mps2.c
@@ -346,7 +346,6 @@ static void mps2_common_init(MachineState *machine)
object_initialize_child(OBJECT(mms), name, &mms->timer[i],
TYPE_CMSDK_APB_TIMER);
sbd = SYS_BUS_DEVICE(&mms->timer[i]);
- qdev_prop_set_uint32(DEVICE(&mms->timer[i]), "pclk-frq", SYSCLK_FRQ);
qdev_connect_clock_in(DEVICE(&mms->timer[i]), "pclk", mms->sysclk);
sysbus_realize_and_unref(sbd, &error_fatal);
sysbus_mmio_map(sbd, 0, base);
@@ -355,7 +354,6 @@ static void mps2_common_init(MachineState *machine)
object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer,
TYPE_CMSDK_APB_DUALTIMER);
- qdev_prop_set_uint32(DEVICE(&mms->dualtimer), "pclk-frq", SYSCLK_FRQ);
qdev_connect_clock_in(DEVICE(&mms->dualtimer), "TIMCLK", mms->sysclk);
sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal);
sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0,
@@ -363,7 +361,6 @@ static void mps2_common_init(MachineState *machine)
sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0x40002000);
object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog,
TYPE_CMSDK_APB_WATCHDOG);
- qdev_prop_set_uint32(DEVICE(&mms->watchdog), "wdogclk-frq", SYSCLK_FRQ);
qdev_connect_clock_in(DEVICE(&mms->watchdog), "WDOGCLK", mms->sysclk);
sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal);
sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0,
diff --git a/hw/arm/musca.c b/hw/arm/musca.c
index a9292482a06..945643c3cd7 100644
--- a/hw/arm/musca.c
+++ b/hw/arm/musca.c
@@ -385,7 +385,6 @@ static void musca_init(MachineState *machine)
qdev_prop_set_uint32(ssedev, "EXP_NUMIRQ", mmc->num_irqs);
qdev_prop_set_uint32(ssedev, "init-svtor", mmc->init_svtor);
qdev_prop_set_uint32(ssedev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width);
- qdev_prop_set_uint32(ssedev, "MAINCLK_FRQ", SYSCLK_FRQ);
qdev_connect_clock_in(ssedev, "MAINCLK", mms->sysclk);
qdev_connect_clock_in(ssedev, "S32KCLK", mms->s32kclk);
/*
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index 9b67c739ef2..5acb043a07e 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -1415,9 +1415,6 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
if (board->dc1 & (1 << 3)) { /* watchdog present */
dev = qdev_new(TYPE_LUMINARY_WATCHDOG);
- /* system_clock_scale is valid now */
- uint32_t mainclk = NANOSECONDS_PER_SECOND / system_clock_scale;
- qdev_prop_set_uint32(dev, "wdogclk-frq", mainclk);
qdev_connect_clock_in(dev, "WDOGCLK",
qdev_get_clock_out(ssys_dev, "SYSCLK"));
--
2.20.1
^ permalink raw reply related [flat|nested] 80+ messages in thread* Re: [PATCH 23/25] arm: Don't set freq properties on CMSDK timer, dualtimer, watchdog, ARMSSE
2021-01-21 19:06 ` [PATCH 23/25] arm: Don't set freq properties on CMSDK timer, dualtimer, watchdog, ARMSSE Peter Maydell
@ 2021-01-21 22:06 ` Philippe Mathieu-Daudé
2021-01-23 20:32 ` Luc Michel
1 sibling, 0 replies; 80+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-21 22:06 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel; +Cc: Damien Hedde, Luc Michel
On 1/21/21 8:06 PM, Peter Maydell wrote:
> Remove all the code that sets frequency properties on the CMSDK
> timer, dualtimer and watchdog devices and on the ARMSSE SoC device:
> these properties are unused now that the devices rely on their Clock
> inputs instead.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> hw/arm/armsse.c | 7 -------
> hw/arm/mps2-tz.c | 1 -
> hw/arm/mps2.c | 3 ---
> hw/arm/musca.c | 1 -
> hw/arm/stellaris.c | 3 ---
> 5 files changed, 15 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 23/25] arm: Don't set freq properties on CMSDK timer, dualtimer, watchdog, ARMSSE
2021-01-21 19:06 ` [PATCH 23/25] arm: Don't set freq properties on CMSDK timer, dualtimer, watchdog, ARMSSE Peter Maydell
2021-01-21 22:06 ` Philippe Mathieu-Daudé
@ 2021-01-23 20:32 ` Luc Michel
1 sibling, 0 replies; 80+ messages in thread
From: Luc Michel @ 2021-01-23 20:32 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, qemu-arm, qemu-devel, Philippe Mathieu-Daudé
On 19:06 Thu 21 Jan , Peter Maydell wrote:
> Remove all the code that sets frequency properties on the CMSDK
> timer, dualtimer and watchdog devices and on the ARMSSE SoC device:
> these properties are unused now that the devices rely on their Clock
> inputs instead.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
> ---
> hw/arm/armsse.c | 7 -------
> hw/arm/mps2-tz.c | 1 -
> hw/arm/mps2.c | 3 ---
> hw/arm/musca.c | 1 -
> hw/arm/stellaris.c | 3 ---
> 5 files changed, 15 deletions(-)
>
> diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
> index 1da0c1be4c7..7494afc630e 100644
> --- a/hw/arm/armsse.c
> +++ b/hw/arm/armsse.c
> @@ -726,7 +726,6 @@ static void armsse_realize(DeviceState *dev, Error **errp)
> * it to the appropriate PPC port; then we can realize the PPC and
> * map its upstream ends to the right place in the container.
> */
> - qdev_prop_set_uint32(DEVICE(&s->timer0), "pclk-frq", s->mainclk_frq);
> qdev_connect_clock_in(DEVICE(&s->timer0), "pclk", s->mainclk);
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer0), errp)) {
> return;
> @@ -737,7 +736,6 @@ static void armsse_realize(DeviceState *dev, Error **errp)
> object_property_set_link(OBJECT(&s->apb_ppc0), "port[0]", OBJECT(mr),
> &error_abort);
>
> - qdev_prop_set_uint32(DEVICE(&s->timer1), "pclk-frq", s->mainclk_frq);
> qdev_connect_clock_in(DEVICE(&s->timer1), "pclk", s->mainclk);
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer1), errp)) {
> return;
> @@ -748,7 +746,6 @@ static void armsse_realize(DeviceState *dev, Error **errp)
> object_property_set_link(OBJECT(&s->apb_ppc0), "port[1]", OBJECT(mr),
> &error_abort);
>
> - qdev_prop_set_uint32(DEVICE(&s->dualtimer), "pclk-frq", s->mainclk_frq);
> qdev_connect_clock_in(DEVICE(&s->dualtimer), "TIMCLK", s->mainclk);
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->dualtimer), errp)) {
> return;
> @@ -907,7 +904,6 @@ static void armsse_realize(DeviceState *dev, Error **errp)
> /* Devices behind APB PPC1:
> * 0x4002f000: S32K timer
> */
> - qdev_prop_set_uint32(DEVICE(&s->s32ktimer), "pclk-frq", S32KCLK);
> qdev_connect_clock_in(DEVICE(&s->s32ktimer), "pclk", s->s32kclk);
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32ktimer), errp)) {
> return;
> @@ -1001,7 +997,6 @@ static void armsse_realize(DeviceState *dev, Error **errp)
> qdev_connect_gpio_out(DEVICE(&s->nmi_orgate), 0,
> qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI", 0));
>
> - qdev_prop_set_uint32(DEVICE(&s->s32kwatchdog), "wdogclk-frq", S32KCLK);
> qdev_connect_clock_in(DEVICE(&s->s32kwatchdog), "WDOGCLK", s->s32kclk);
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->s32kwatchdog), errp)) {
> return;
> @@ -1012,7 +1007,6 @@ static void armsse_realize(DeviceState *dev, Error **errp)
>
> /* 0x40080000 .. 0x4008ffff : ARMSSE second Base peripheral region */
>
> - qdev_prop_set_uint32(DEVICE(&s->nswatchdog), "wdogclk-frq", s->mainclk_frq);
> qdev_connect_clock_in(DEVICE(&s->nswatchdog), "WDOGCLK", s->mainclk);
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->nswatchdog), errp)) {
> return;
> @@ -1021,7 +1015,6 @@ static void armsse_realize(DeviceState *dev, Error **errp)
> armsse_get_common_irq_in(s, 1));
> sysbus_mmio_map(SYS_BUS_DEVICE(&s->nswatchdog), 0, 0x40081000);
>
> - qdev_prop_set_uint32(DEVICE(&s->swatchdog), "wdogclk-frq", s->mainclk_frq);
> qdev_connect_clock_in(DEVICE(&s->swatchdog), "WDOGCLK", s->mainclk);
> if (!sysbus_realize(SYS_BUS_DEVICE(&s->swatchdog), errp)) {
> return;
> diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
> index 7acdf490f28..90caa914934 100644
> --- a/hw/arm/mps2-tz.c
> +++ b/hw/arm/mps2-tz.c
> @@ -413,7 +413,6 @@ static void mps2tz_common_init(MachineState *machine)
> object_property_set_link(OBJECT(&mms->iotkit), "memory",
> OBJECT(system_memory), &error_abort);
> qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ);
> - qdev_prop_set_uint32(iotkitdev, "MAINCLK_FRQ", SYSCLK_FRQ);
> qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk);
> qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk);
> sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal);
> diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
> index cd1c215f941..39add416db5 100644
> --- a/hw/arm/mps2.c
> +++ b/hw/arm/mps2.c
> @@ -346,7 +346,6 @@ static void mps2_common_init(MachineState *machine)
> object_initialize_child(OBJECT(mms), name, &mms->timer[i],
> TYPE_CMSDK_APB_TIMER);
> sbd = SYS_BUS_DEVICE(&mms->timer[i]);
> - qdev_prop_set_uint32(DEVICE(&mms->timer[i]), "pclk-frq", SYSCLK_FRQ);
> qdev_connect_clock_in(DEVICE(&mms->timer[i]), "pclk", mms->sysclk);
> sysbus_realize_and_unref(sbd, &error_fatal);
> sysbus_mmio_map(sbd, 0, base);
> @@ -355,7 +354,6 @@ static void mps2_common_init(MachineState *machine)
>
> object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer,
> TYPE_CMSDK_APB_DUALTIMER);
> - qdev_prop_set_uint32(DEVICE(&mms->dualtimer), "pclk-frq", SYSCLK_FRQ);
> qdev_connect_clock_in(DEVICE(&mms->dualtimer), "TIMCLK", mms->sysclk);
> sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal);
> sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0,
> @@ -363,7 +361,6 @@ static void mps2_common_init(MachineState *machine)
> sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0x40002000);
> object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog,
> TYPE_CMSDK_APB_WATCHDOG);
> - qdev_prop_set_uint32(DEVICE(&mms->watchdog), "wdogclk-frq", SYSCLK_FRQ);
> qdev_connect_clock_in(DEVICE(&mms->watchdog), "WDOGCLK", mms->sysclk);
> sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal);
> sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0,
> diff --git a/hw/arm/musca.c b/hw/arm/musca.c
> index a9292482a06..945643c3cd7 100644
> --- a/hw/arm/musca.c
> +++ b/hw/arm/musca.c
> @@ -385,7 +385,6 @@ static void musca_init(MachineState *machine)
> qdev_prop_set_uint32(ssedev, "EXP_NUMIRQ", mmc->num_irqs);
> qdev_prop_set_uint32(ssedev, "init-svtor", mmc->init_svtor);
> qdev_prop_set_uint32(ssedev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width);
> - qdev_prop_set_uint32(ssedev, "MAINCLK_FRQ", SYSCLK_FRQ);
> qdev_connect_clock_in(ssedev, "MAINCLK", mms->sysclk);
> qdev_connect_clock_in(ssedev, "S32KCLK", mms->s32kclk);
> /*
> diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
> index 9b67c739ef2..5acb043a07e 100644
> --- a/hw/arm/stellaris.c
> +++ b/hw/arm/stellaris.c
> @@ -1415,9 +1415,6 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
> if (board->dc1 & (1 << 3)) { /* watchdog present */
> dev = qdev_new(TYPE_LUMINARY_WATCHDOG);
>
> - /* system_clock_scale is valid now */
> - uint32_t mainclk = NANOSECONDS_PER_SECOND / system_clock_scale;
> - qdev_prop_set_uint32(dev, "wdogclk-frq", mainclk);
> qdev_connect_clock_in(dev, "WDOGCLK",
> qdev_get_clock_out(ssys_dev, "SYSCLK"));
>
> --
> 2.20.1
>
--
^ permalink raw reply [flat|nested] 80+ messages in thread
* [PATCH 24/25] arm: Remove frq properties on CMSDK timer, dualtimer, watchdog, ARMSSE
2021-01-21 19:05 [PATCH 00/25] Convert CMSDK timer, watchdog, dualtimer to Clock framework Peter Maydell
` (22 preceding siblings ...)
2021-01-21 19:06 ` [PATCH 23/25] arm: Don't set freq properties on CMSDK timer, dualtimer, watchdog, ARMSSE Peter Maydell
@ 2021-01-21 19:06 ` Peter Maydell
2021-01-21 22:09 ` Philippe Mathieu-Daudé
2021-01-23 20:33 ` Luc Michel
2021-01-21 19:06 ` [PATCH 25/25] hw/arm/stellaris: Remove board-creation reset of STELLARIS_SYS Peter Maydell
24 siblings, 2 replies; 80+ messages in thread
From: Peter Maydell @ 2021-01-21 19:06 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Philippe Mathieu-Daudé
Now no users are setting the frq properties on the CMSDK timer,
dualtimer, watchdog or ARMSSE SoC devices, we can remove the
properties and the struct fields that back them.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/armsse.h | 2 --
include/hw/timer/cmsdk-apb-dualtimer.h | 2 --
include/hw/timer/cmsdk-apb-timer.h | 2 --
include/hw/watchdog/cmsdk-apb-watchdog.h | 2 --
hw/arm/armsse.c | 2 --
hw/timer/cmsdk-apb-dualtimer.c | 6 ------
hw/timer/cmsdk-apb-timer.c | 6 ------
hw/watchdog/cmsdk-apb-watchdog.c | 6 ------
8 files changed, 28 deletions(-)
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
index bfa1e79c4fe..676cd4f36b0 100644
--- a/include/hw/arm/armsse.h
+++ b/include/hw/arm/armsse.h
@@ -41,7 +41,6 @@
* + Clock input "S32KCLK": slow 32KHz clock used for a few peripherals
* + QOM property "memory" is a MemoryRegion containing the devices provided
* by the board model.
- * + QOM property "MAINCLK_FRQ" is the frequency of the main system clock
* + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts.
* (In hardware, the SSE-200 permits the number of expansion interrupts
* for the two CPUs to be configured separately, but we restrict it to
@@ -218,7 +217,6 @@ struct ARMSSE {
/* Properties */
MemoryRegion *board_memory;
uint32_t exp_numirq;
- uint32_t mainclk_frq;
uint32_t sram_addr_width;
uint32_t init_svtor;
bool cpu_fpu[SSE_MAX_CPUS];
diff --git a/include/hw/timer/cmsdk-apb-dualtimer.h b/include/hw/timer/cmsdk-apb-dualtimer.h
index 3adbb01dd34..f3ec86c00b5 100644
--- a/include/hw/timer/cmsdk-apb-dualtimer.h
+++ b/include/hw/timer/cmsdk-apb-dualtimer.h
@@ -16,7 +16,6 @@
* https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit
*
* QEMU interface:
- * + QOM property "pclk-frq": frequency at which the timer is clocked
* + Clock input "TIMCLK": clock (for both timers)
* + sysbus MMIO region 0: the register bank
* + sysbus IRQ 0: combined timer interrupt TIMINTC
@@ -63,7 +62,6 @@ struct CMSDKAPBDualTimer {
/*< public >*/
MemoryRegion iomem;
qemu_irq timerintc;
- uint32_t pclk_frq;
Clock *timclk;
CMSDKAPBDualTimerModule timermod[CMSDK_APB_DUALTIMER_NUM_MODULES];
diff --git a/include/hw/timer/cmsdk-apb-timer.h b/include/hw/timer/cmsdk-apb-timer.h
index 54f7ec8c502..c4c7eae8499 100644
--- a/include/hw/timer/cmsdk-apb-timer.h
+++ b/include/hw/timer/cmsdk-apb-timer.h
@@ -23,7 +23,6 @@ OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBTimer, CMSDK_APB_TIMER)
/*
* QEMU interface:
- * + QOM property "pclk-frq": frequency at which the timer is clocked
* + Clock input "pclk": clock for the timer
* + sysbus MMIO region 0: the register bank
* + sysbus IRQ 0: timer interrupt TIMERINT
@@ -35,7 +34,6 @@ struct CMSDKAPBTimer {
/*< public >*/
MemoryRegion iomem;
qemu_irq timerint;
- uint32_t pclk_frq;
struct ptimer_state *timer;
Clock *pclk;
diff --git a/include/hw/watchdog/cmsdk-apb-watchdog.h b/include/hw/watchdog/cmsdk-apb-watchdog.h
index 34069ca6969..c6b3e78731e 100644
--- a/include/hw/watchdog/cmsdk-apb-watchdog.h
+++ b/include/hw/watchdog/cmsdk-apb-watchdog.h
@@ -16,7 +16,6 @@
* https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit
*
* QEMU interface:
- * + QOM property "wdogclk-frq": frequency at which the watchdog is clocked
* + Clock input "WDOGCLK": clock for the watchdog's timer
* + sysbus MMIO region 0: the register bank
* + sysbus IRQ 0: watchdog interrupt
@@ -53,7 +52,6 @@ struct CMSDKAPBWatchdog {
/*< public >*/
MemoryRegion iomem;
qemu_irq wdogint;
- uint32_t wdogclk_frq;
bool is_luminary;
struct ptimer_state *timer;
Clock *wdogclk;
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
index 7494afc630e..513caa33a9a 100644
--- a/hw/arm/armsse.c
+++ b/hw/arm/armsse.c
@@ -48,7 +48,6 @@ static Property iotkit_properties[] = {
DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION,
MemoryRegion *),
DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64),
- DEFINE_PROP_UINT32("MAINCLK_FRQ", ARMSSE, mainclk_frq, 0),
DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15),
DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
@@ -60,7 +59,6 @@ static Property armsse_properties[] = {
DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION,
MemoryRegion *),
DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64),
- DEFINE_PROP_UINT32("MAINCLK_FRQ", ARMSSE, mainclk_frq, 0),
DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15),
DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false),
diff --git a/hw/timer/cmsdk-apb-dualtimer.c b/hw/timer/cmsdk-apb-dualtimer.c
index 828127b366f..ef49f5852d3 100644
--- a/hw/timer/cmsdk-apb-dualtimer.c
+++ b/hw/timer/cmsdk-apb-dualtimer.c
@@ -533,11 +533,6 @@ static const VMStateDescription cmsdk_apb_dualtimer_vmstate = {
}
};
-static Property cmsdk_apb_dualtimer_properties[] = {
- DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBDualTimer, pclk_frq, 0),
- DEFINE_PROP_END_OF_LIST(),
-};
-
static void cmsdk_apb_dualtimer_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -545,7 +540,6 @@ static void cmsdk_apb_dualtimer_class_init(ObjectClass *klass, void *data)
dc->realize = cmsdk_apb_dualtimer_realize;
dc->vmsd = &cmsdk_apb_dualtimer_vmstate;
dc->reset = cmsdk_apb_dualtimer_reset;
- device_class_set_props(dc, cmsdk_apb_dualtimer_properties);
}
static const TypeInfo cmsdk_apb_dualtimer_info = {
diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c
index f053146d88f..ee51ce3369c 100644
--- a/hw/timer/cmsdk-apb-timer.c
+++ b/hw/timer/cmsdk-apb-timer.c
@@ -261,11 +261,6 @@ static const VMStateDescription cmsdk_apb_timer_vmstate = {
}
};
-static Property cmsdk_apb_timer_properties[] = {
- DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBTimer, pclk_frq, 0),
- DEFINE_PROP_END_OF_LIST(),
-};
-
static void cmsdk_apb_timer_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -273,7 +268,6 @@ static void cmsdk_apb_timer_class_init(ObjectClass *klass, void *data)
dc->realize = cmsdk_apb_timer_realize;
dc->vmsd = &cmsdk_apb_timer_vmstate;
dc->reset = cmsdk_apb_timer_reset;
- device_class_set_props(dc, cmsdk_apb_timer_properties);
}
static const TypeInfo cmsdk_apb_timer_info = {
diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watchdog.c
index 9cad0c67da4..302f1711738 100644
--- a/hw/watchdog/cmsdk-apb-watchdog.c
+++ b/hw/watchdog/cmsdk-apb-watchdog.c
@@ -373,11 +373,6 @@ static const VMStateDescription cmsdk_apb_watchdog_vmstate = {
}
};
-static Property cmsdk_apb_watchdog_properties[] = {
- DEFINE_PROP_UINT32("wdogclk-frq", CMSDKAPBWatchdog, wdogclk_frq, 0),
- DEFINE_PROP_END_OF_LIST(),
-};
-
static void cmsdk_apb_watchdog_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -385,7 +380,6 @@ static void cmsdk_apb_watchdog_class_init(ObjectClass *klass, void *data)
dc->realize = cmsdk_apb_watchdog_realize;
dc->vmsd = &cmsdk_apb_watchdog_vmstate;
dc->reset = cmsdk_apb_watchdog_reset;
- device_class_set_props(dc, cmsdk_apb_watchdog_properties);
}
static const TypeInfo cmsdk_apb_watchdog_info = {
--
2.20.1
^ permalink raw reply related [flat|nested] 80+ messages in thread* Re: [PATCH 24/25] arm: Remove frq properties on CMSDK timer, dualtimer, watchdog, ARMSSE
2021-01-21 19:06 ` [PATCH 24/25] arm: Remove frq " Peter Maydell
@ 2021-01-21 22:09 ` Philippe Mathieu-Daudé
2021-01-23 20:33 ` Luc Michel
1 sibling, 0 replies; 80+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-21 22:09 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel; +Cc: Damien Hedde, Luc Michel
On 1/21/21 8:06 PM, Peter Maydell wrote:
> Now no users are setting the frq properties on the CMSDK timer,
"Now that no ..."? No clue, double "no*" sounds odd to me :)
> dualtimer, watchdog or ARMSSE SoC devices, we can remove the
> properties and the struct fields that back them.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> include/hw/arm/armsse.h | 2 --
> include/hw/timer/cmsdk-apb-dualtimer.h | 2 --
> include/hw/timer/cmsdk-apb-timer.h | 2 --
> include/hw/watchdog/cmsdk-apb-watchdog.h | 2 --
> hw/arm/armsse.c | 2 --
> hw/timer/cmsdk-apb-dualtimer.c | 6 ------
> hw/timer/cmsdk-apb-timer.c | 6 ------
> hw/watchdog/cmsdk-apb-watchdog.c | 6 ------
> 8 files changed, 28 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 24/25] arm: Remove frq properties on CMSDK timer, dualtimer, watchdog, ARMSSE
2021-01-21 19:06 ` [PATCH 24/25] arm: Remove frq " Peter Maydell
2021-01-21 22:09 ` Philippe Mathieu-Daudé
@ 2021-01-23 20:33 ` Luc Michel
1 sibling, 0 replies; 80+ messages in thread
From: Luc Michel @ 2021-01-23 20:33 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, qemu-arm, qemu-devel, Philippe Mathieu-Daudé
On 19:06 Thu 21 Jan , Peter Maydell wrote:
> Now no users are setting the frq properties on the CMSDK timer,
> dualtimer, watchdog or ARMSSE SoC devices, we can remove the
> properties and the struct fields that back them.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
> ---
> include/hw/arm/armsse.h | 2 --
> include/hw/timer/cmsdk-apb-dualtimer.h | 2 --
> include/hw/timer/cmsdk-apb-timer.h | 2 --
> include/hw/watchdog/cmsdk-apb-watchdog.h | 2 --
> hw/arm/armsse.c | 2 --
> hw/timer/cmsdk-apb-dualtimer.c | 6 ------
> hw/timer/cmsdk-apb-timer.c | 6 ------
> hw/watchdog/cmsdk-apb-watchdog.c | 6 ------
> 8 files changed, 28 deletions(-)
>
> diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
> index bfa1e79c4fe..676cd4f36b0 100644
> --- a/include/hw/arm/armsse.h
> +++ b/include/hw/arm/armsse.h
> @@ -41,7 +41,6 @@
> * + Clock input "S32KCLK": slow 32KHz clock used for a few peripherals
> * + QOM property "memory" is a MemoryRegion containing the devices provided
> * by the board model.
> - * + QOM property "MAINCLK_FRQ" is the frequency of the main system clock
> * + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts.
> * (In hardware, the SSE-200 permits the number of expansion interrupts
> * for the two CPUs to be configured separately, but we restrict it to
> @@ -218,7 +217,6 @@ struct ARMSSE {
> /* Properties */
> MemoryRegion *board_memory;
> uint32_t exp_numirq;
> - uint32_t mainclk_frq;
> uint32_t sram_addr_width;
> uint32_t init_svtor;
> bool cpu_fpu[SSE_MAX_CPUS];
> diff --git a/include/hw/timer/cmsdk-apb-dualtimer.h b/include/hw/timer/cmsdk-apb-dualtimer.h
> index 3adbb01dd34..f3ec86c00b5 100644
> --- a/include/hw/timer/cmsdk-apb-dualtimer.h
> +++ b/include/hw/timer/cmsdk-apb-dualtimer.h
> @@ -16,7 +16,6 @@
> * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit
> *
> * QEMU interface:
> - * + QOM property "pclk-frq": frequency at which the timer is clocked
> * + Clock input "TIMCLK": clock (for both timers)
> * + sysbus MMIO region 0: the register bank
> * + sysbus IRQ 0: combined timer interrupt TIMINTC
> @@ -63,7 +62,6 @@ struct CMSDKAPBDualTimer {
> /*< public >*/
> MemoryRegion iomem;
> qemu_irq timerintc;
> - uint32_t pclk_frq;
> Clock *timclk;
>
> CMSDKAPBDualTimerModule timermod[CMSDK_APB_DUALTIMER_NUM_MODULES];
> diff --git a/include/hw/timer/cmsdk-apb-timer.h b/include/hw/timer/cmsdk-apb-timer.h
> index 54f7ec8c502..c4c7eae8499 100644
> --- a/include/hw/timer/cmsdk-apb-timer.h
> +++ b/include/hw/timer/cmsdk-apb-timer.h
> @@ -23,7 +23,6 @@ OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBTimer, CMSDK_APB_TIMER)
>
> /*
> * QEMU interface:
> - * + QOM property "pclk-frq": frequency at which the timer is clocked
> * + Clock input "pclk": clock for the timer
> * + sysbus MMIO region 0: the register bank
> * + sysbus IRQ 0: timer interrupt TIMERINT
> @@ -35,7 +34,6 @@ struct CMSDKAPBTimer {
> /*< public >*/
> MemoryRegion iomem;
> qemu_irq timerint;
> - uint32_t pclk_frq;
> struct ptimer_state *timer;
> Clock *pclk;
>
> diff --git a/include/hw/watchdog/cmsdk-apb-watchdog.h b/include/hw/watchdog/cmsdk-apb-watchdog.h
> index 34069ca6969..c6b3e78731e 100644
> --- a/include/hw/watchdog/cmsdk-apb-watchdog.h
> +++ b/include/hw/watchdog/cmsdk-apb-watchdog.h
> @@ -16,7 +16,6 @@
> * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit
> *
> * QEMU interface:
> - * + QOM property "wdogclk-frq": frequency at which the watchdog is clocked
> * + Clock input "WDOGCLK": clock for the watchdog's timer
> * + sysbus MMIO region 0: the register bank
> * + sysbus IRQ 0: watchdog interrupt
> @@ -53,7 +52,6 @@ struct CMSDKAPBWatchdog {
> /*< public >*/
> MemoryRegion iomem;
> qemu_irq wdogint;
> - uint32_t wdogclk_frq;
> bool is_luminary;
> struct ptimer_state *timer;
> Clock *wdogclk;
> diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
> index 7494afc630e..513caa33a9a 100644
> --- a/hw/arm/armsse.c
> +++ b/hw/arm/armsse.c
> @@ -48,7 +48,6 @@ static Property iotkit_properties[] = {
> DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION,
> MemoryRegion *),
> DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64),
> - DEFINE_PROP_UINT32("MAINCLK_FRQ", ARMSSE, mainclk_frq, 0),
> DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15),
> DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
> DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
> @@ -60,7 +59,6 @@ static Property armsse_properties[] = {
> DEFINE_PROP_LINK("memory", ARMSSE, board_memory, TYPE_MEMORY_REGION,
> MemoryRegion *),
> DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64),
> - DEFINE_PROP_UINT32("MAINCLK_FRQ", ARMSSE, mainclk_frq, 0),
> DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15),
> DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
> DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], false),
> diff --git a/hw/timer/cmsdk-apb-dualtimer.c b/hw/timer/cmsdk-apb-dualtimer.c
> index 828127b366f..ef49f5852d3 100644
> --- a/hw/timer/cmsdk-apb-dualtimer.c
> +++ b/hw/timer/cmsdk-apb-dualtimer.c
> @@ -533,11 +533,6 @@ static const VMStateDescription cmsdk_apb_dualtimer_vmstate = {
> }
> };
>
> -static Property cmsdk_apb_dualtimer_properties[] = {
> - DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBDualTimer, pclk_frq, 0),
> - DEFINE_PROP_END_OF_LIST(),
> -};
> -
> static void cmsdk_apb_dualtimer_class_init(ObjectClass *klass, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
> @@ -545,7 +540,6 @@ static void cmsdk_apb_dualtimer_class_init(ObjectClass *klass, void *data)
> dc->realize = cmsdk_apb_dualtimer_realize;
> dc->vmsd = &cmsdk_apb_dualtimer_vmstate;
> dc->reset = cmsdk_apb_dualtimer_reset;
> - device_class_set_props(dc, cmsdk_apb_dualtimer_properties);
> }
>
> static const TypeInfo cmsdk_apb_dualtimer_info = {
> diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c
> index f053146d88f..ee51ce3369c 100644
> --- a/hw/timer/cmsdk-apb-timer.c
> +++ b/hw/timer/cmsdk-apb-timer.c
> @@ -261,11 +261,6 @@ static const VMStateDescription cmsdk_apb_timer_vmstate = {
> }
> };
>
> -static Property cmsdk_apb_timer_properties[] = {
> - DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBTimer, pclk_frq, 0),
> - DEFINE_PROP_END_OF_LIST(),
> -};
> -
> static void cmsdk_apb_timer_class_init(ObjectClass *klass, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
> @@ -273,7 +268,6 @@ static void cmsdk_apb_timer_class_init(ObjectClass *klass, void *data)
> dc->realize = cmsdk_apb_timer_realize;
> dc->vmsd = &cmsdk_apb_timer_vmstate;
> dc->reset = cmsdk_apb_timer_reset;
> - device_class_set_props(dc, cmsdk_apb_timer_properties);
> }
>
> static const TypeInfo cmsdk_apb_timer_info = {
> diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watchdog.c
> index 9cad0c67da4..302f1711738 100644
> --- a/hw/watchdog/cmsdk-apb-watchdog.c
> +++ b/hw/watchdog/cmsdk-apb-watchdog.c
> @@ -373,11 +373,6 @@ static const VMStateDescription cmsdk_apb_watchdog_vmstate = {
> }
> };
>
> -static Property cmsdk_apb_watchdog_properties[] = {
> - DEFINE_PROP_UINT32("wdogclk-frq", CMSDKAPBWatchdog, wdogclk_frq, 0),
> - DEFINE_PROP_END_OF_LIST(),
> -};
> -
> static void cmsdk_apb_watchdog_class_init(ObjectClass *klass, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
> @@ -385,7 +380,6 @@ static void cmsdk_apb_watchdog_class_init(ObjectClass *klass, void *data)
> dc->realize = cmsdk_apb_watchdog_realize;
> dc->vmsd = &cmsdk_apb_watchdog_vmstate;
> dc->reset = cmsdk_apb_watchdog_reset;
> - device_class_set_props(dc, cmsdk_apb_watchdog_properties);
> }
>
> static const TypeInfo cmsdk_apb_watchdog_info = {
> --
> 2.20.1
>
--
^ permalink raw reply [flat|nested] 80+ messages in thread
* [PATCH 25/25] hw/arm/stellaris: Remove board-creation reset of STELLARIS_SYS
2021-01-21 19:05 [PATCH 00/25] Convert CMSDK timer, watchdog, dualtimer to Clock framework Peter Maydell
` (23 preceding siblings ...)
2021-01-21 19:06 ` [PATCH 24/25] arm: Remove frq " Peter Maydell
@ 2021-01-21 19:06 ` Peter Maydell
2021-01-23 20:33 ` Luc Michel
2021-01-27 22:10 ` Philippe Mathieu-Daudé
24 siblings, 2 replies; 80+ messages in thread
From: Peter Maydell @ 2021-01-21 19:06 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Damien Hedde, Luc Michel, Philippe Mathieu-Daudé
Now that the watchdog device uses its Clock input rather than being
passed the value of system_clock_scale at creation time, we can
remove the hack where we reset the STELLARIS_SYS at board creation
time to force it to set system_clock_scale. Instead it will be reset
at the usual point in startup and will inform the watchdog of the
clock frequency at that point.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/stellaris.c | 10 ----------
1 file changed, 10 deletions(-)
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index 5acb043a07e..ad72c0959f1 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -780,16 +780,6 @@ static DeviceState *stellaris_sys_init(uint32_t base, qemu_irq irq,
sysbus_mmio_map(sbd, 0, base);
sysbus_connect_irq(sbd, 0, irq);
- /*
- * Normally we should not be resetting devices like this during
- * board creation. For the moment we need to do so, because
- * system_clock_scale will only get set when the STELLARIS_SYS
- * device is reset, and we need its initial value to pass to
- * the watchdog device. This hack can be removed once the
- * watchdog has been converted to use a Clock input instead.
- */
- device_cold_reset(dev);
-
return dev;
}
--
2.20.1
^ permalink raw reply related [flat|nested] 80+ messages in thread* Re: [PATCH 25/25] hw/arm/stellaris: Remove board-creation reset of STELLARIS_SYS
2021-01-21 19:06 ` [PATCH 25/25] hw/arm/stellaris: Remove board-creation reset of STELLARIS_SYS Peter Maydell
@ 2021-01-23 20:33 ` Luc Michel
2021-01-27 22:10 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 80+ messages in thread
From: Luc Michel @ 2021-01-23 20:33 UTC (permalink / raw)
To: Peter Maydell
Cc: Damien Hedde, qemu-arm, qemu-devel, Philippe Mathieu-Daudé
On 19:06 Thu 21 Jan , Peter Maydell wrote:
> Now that the watchdog device uses its Clock input rather than being
> passed the value of system_clock_scale at creation time, we can
> remove the hack where we reset the STELLARIS_SYS at board creation
> time to force it to set system_clock_scale. Instead it will be reset
> at the usual point in startup and will inform the watchdog of the
> clock frequency at that point.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
> ---
> hw/arm/stellaris.c | 10 ----------
> 1 file changed, 10 deletions(-)
>
> diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
> index 5acb043a07e..ad72c0959f1 100644
> --- a/hw/arm/stellaris.c
> +++ b/hw/arm/stellaris.c
> @@ -780,16 +780,6 @@ static DeviceState *stellaris_sys_init(uint32_t base, qemu_irq irq,
> sysbus_mmio_map(sbd, 0, base);
> sysbus_connect_irq(sbd, 0, irq);
>
> - /*
> - * Normally we should not be resetting devices like this during
> - * board creation. For the moment we need to do so, because
> - * system_clock_scale will only get set when the STELLARIS_SYS
> - * device is reset, and we need its initial value to pass to
> - * the watchdog device. This hack can be removed once the
> - * watchdog has been converted to use a Clock input instead.
> - */
> - device_cold_reset(dev);
> -
> return dev;
> }
>
> --
> 2.20.1
>
--
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH 25/25] hw/arm/stellaris: Remove board-creation reset of STELLARIS_SYS
2021-01-21 19:06 ` [PATCH 25/25] hw/arm/stellaris: Remove board-creation reset of STELLARIS_SYS Peter Maydell
2021-01-23 20:33 ` Luc Michel
@ 2021-01-27 22:10 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 80+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-27 22:10 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel; +Cc: Damien Hedde, Luc Michel
On 1/21/21 8:06 PM, Peter Maydell wrote:
> Now that the watchdog device uses its Clock input rather than being
> passed the value of system_clock_scale at creation time, we can
> remove the hack where we reset the STELLARIS_SYS at board creation
> time to force it to set system_clock_scale. Instead it will be reset
> at the usual point in startup and will inform the watchdog of the
> clock frequency at that point.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> hw/arm/stellaris.c | 10 ----------
> 1 file changed, 10 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 80+ messages in thread