From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PULL 10/24] tcg/mips: Split out target constraints to tcg-target-con-str.h
Date: Tue, 2 Feb 2021 16:15:36 -1000 [thread overview]
Message-ID: <20210203021550.375058-11-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210203021550.375058-1-richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/mips/tcg-target-con-str.h | 24 +++++++++++
tcg/mips/tcg-target.h | 1 +
tcg/mips/tcg-target.c.inc | 77 ++++++++++-------------------------
3 files changed, 46 insertions(+), 56 deletions(-)
create mode 100644 tcg/mips/tcg-target-con-str.h
diff --git a/tcg/mips/tcg-target-con-str.h b/tcg/mips/tcg-target-con-str.h
new file mode 100644
index 0000000000..e4b2965c72
--- /dev/null
+++ b/tcg/mips/tcg-target-con-str.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define MIPS target-specific operand constraints.
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * Define constraint letters for register sets:
+ * REGS(letter, register_mask)
+ */
+REGS('r', ALL_GENERAL_REGS)
+REGS('L', ALL_QLOAD_REGS)
+REGS('S', ALL_QSTORE_REGS)
+
+/*
+ * Define constraint letters for constants:
+ * CONST(letter, TCG_CT_CONST_* bit set)
+ */
+CONST('I', TCG_CT_CONST_U16)
+CONST('J', TCG_CT_CONST_S16)
+CONST('K', TCG_CT_CONST_P2M1)
+CONST('N', TCG_CT_CONST_N16)
+CONST('W', TCG_CT_CONST_WSZ)
+CONST('Z', TCG_CT_CONST_ZERO)
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index c2c32fb38f..d850200855 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -207,5 +207,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
#ifdef CONFIG_SOFTMMU
#define TCG_TARGET_NEED_LDST_LABELS
#endif
+#define TCG_TARGET_CON_STR_H
#endif
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index 7293169ab2..432d38a010 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -171,67 +171,27 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
#define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */
#define TCG_CT_CONST_WSZ 0x2000 /* word size */
+#define ALL_GENERAL_REGS 0xffffffffu
+#define NOA0_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_A0))
+
+#ifdef CONFIG_SOFTMMU
+#define ALL_QLOAD_REGS \
+ (NOA0_REGS & ~((TCG_TARGET_REG_BITS < TARGET_LONG_BITS) << TCG_REG_A2))
+#define ALL_QSTORE_REGS \
+ (NOA0_REGS & ~(TCG_TARGET_REG_BITS < TARGET_LONG_BITS \
+ ? (1 << TCG_REG_A2) | (1 << TCG_REG_A3) \
+ : (1 << TCG_REG_A1)))
+#else
+#define ALL_QLOAD_REGS NOA0_REGS
+#define ALL_QSTORE_REGS NOA0_REGS
+#endif
+
+
static inline bool is_p2m1(tcg_target_long val)
{
return val && ((val + 1) & val) == 0;
}
-/* parse target specific constraints */
-static const char *target_parse_constraint(TCGArgConstraint *ct,
- const char *ct_str, TCGType type)
-{
- switch(*ct_str++) {
- case 'r':
- ct->regs = 0xffffffff;
- break;
- case 'L': /* qemu_ld input arg constraint */
- ct->regs = 0xffffffff;
- tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
-#if defined(CONFIG_SOFTMMU)
- if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
- tcg_regset_reset_reg(ct->regs, TCG_REG_A2);
- }
-#endif
- break;
- case 'S': /* qemu_st constraint */
- ct->regs = 0xffffffff;
- tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
-#if defined(CONFIG_SOFTMMU)
- if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
- tcg_regset_reset_reg(ct->regs, TCG_REG_A2);
- tcg_regset_reset_reg(ct->regs, TCG_REG_A3);
- } else {
- tcg_regset_reset_reg(ct->regs, TCG_REG_A1);
- }
-#endif
- break;
- case 'I':
- ct->ct |= TCG_CT_CONST_U16;
- break;
- case 'J':
- ct->ct |= TCG_CT_CONST_S16;
- break;
- case 'K':
- ct->ct |= TCG_CT_CONST_P2M1;
- break;
- case 'N':
- ct->ct |= TCG_CT_CONST_N16;
- break;
- case 'W':
- ct->ct |= TCG_CT_CONST_WSZ;
- break;
- case 'Z':
- /* We are cheating a bit here, using the fact that the register
- ZERO is also the register number 0. Hence there is no need
- to check for const_args in each instruction. */
- ct->ct |= TCG_CT_CONST_ZERO;
- break;
- default:
- return NULL;
- }
- return ct_str;
-}
-
/* test if a constant matches the constraint */
static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
const TCGArgConstraint *arg_ct)
@@ -1697,6 +1657,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
TCGArg a0, a1, a2;
int c2;
+ /*
+ * Note that many operands use the constraint set "rZ".
+ * We make use of the fact that 0 is the ZERO register,
+ * and hence such cases need not check for const_args.
+ */
a0 = args[0];
a1 = args[1];
a2 = args[2];
--
2.25.1
next prev parent reply other threads:[~2021-02-03 2:26 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-03 2:15 [PULL 00/24] tcg patch queue Richard Henderson
2021-02-03 2:15 ` [PULL 01/24] tcg/tci: Drop L and S constraints Richard Henderson
2021-02-03 2:15 ` [PULL 02/24] tcg/tci: Remove TCG_TARGET_HAS_* ifdefs Richard Henderson
2021-02-03 2:15 ` [PULL 03/24] tcg/i386: Move constraint type check to tcg_target_const_match Richard Henderson
2021-02-03 2:15 ` [PULL 04/24] tcg/i386: Tidy register constraint definitions Richard Henderson
2021-02-03 2:15 ` [PULL 05/24] tcg/i386: Split out target constraints to tcg-target-con-str.h Richard Henderson
2021-02-03 2:15 ` [PULL 06/24] tcg/arm: " Richard Henderson
2021-02-03 2:15 ` [PULL 07/24] tcg/aarch64: " Richard Henderson
2021-02-03 2:15 ` [PULL 08/24] tcg/ppc: " Richard Henderson
2021-02-03 2:15 ` [PULL 09/24] tcg/tci: " Richard Henderson
2021-02-03 2:15 ` Richard Henderson [this message]
2021-02-03 2:15 ` [PULL 11/24] tcg/riscv: " Richard Henderson
2021-02-03 2:15 ` [PULL 12/24] tcg/s390: " Richard Henderson
2021-02-03 2:15 ` [PULL 13/24] tcg/sparc: " Richard Henderson
2021-02-03 2:15 ` [PULL 14/24] tcg: Remove TCG_TARGET_CON_STR_H Richard Henderson
2021-02-03 2:15 ` [PULL 15/24] tcg/i386: Split out constraint sets to tcg-target-con-set.h Richard Henderson
2021-02-03 2:15 ` [PULL 16/24] tcg/aarch64: " Richard Henderson
2021-02-03 2:15 ` [PULL 17/24] tcg/arm: " Richard Henderson
2021-02-03 2:15 ` [PULL 18/24] tcg/mips: " Richard Henderson
2021-02-03 2:15 ` [PULL 19/24] tcg/ppc: " Richard Henderson
2021-02-03 2:15 ` [PULL 20/24] tcg/riscv: " Richard Henderson
2021-02-03 2:15 ` [PULL 21/24] tcg/s390: " Richard Henderson
2021-02-03 2:15 ` [PULL 22/24] tcg/sparc: " Richard Henderson
2021-02-03 2:15 ` [PULL 23/24] tcg/tci: " Richard Henderson
2021-02-03 2:15 ` [PULL 24/24] tcg: Remove TCG_TARGET_CON_SET_H Richard Henderson
2021-02-03 2:39 ` [PULL 00/24] tcg patch queue no-reply
2021-02-04 10:00 ` Peter Maydell
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