From: Claudio Fontana <cfontana@suse.de>
To: "Alex Bennée" <alex.bennee@linaro.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>,
"Eduardo Habkost" <ehabkost@redhat.com>,
"Peter Maydell" <peter.maydell@linaro.org>
Cc: Laurent Vivier <lvivier@redhat.com>,
Thomas Huth <thuth@redhat.com>,
Roman Bolshakov <r.bolshakov@yadro.com>,
Claudio Fontana <cfontana@suse.de>,
qemu-devel@nongnu.org
Subject: [RFC v18 05/15] accel-cpu: make cpu_realizefn return a bool
Date: Fri, 12 Feb 2021 13:36:12 +0100 [thread overview]
Message-ID: <20210212123622.15834-6-cfontana@suse.de> (raw)
In-Reply-To: <20210212123622.15834-1-cfontana@suse.de>
overall, all devices' realize functions take an Error **errp, but return void.
hw/core/qdev.c code, which realizes devices, therefore does:
local_err = NULL;
dc->realize(dev, &local_err);
if (local_err != NULL) {
goto fail;
}
However, we can improve at least accel_cpu to return a meaningful bool value.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
include/hw/core/accel-cpu.h | 2 +-
include/qemu/accel.h | 2 +-
target/i386/host-cpu.h | 2 +-
accel/accel-common.c | 6 +++---
cpu.c | 5 +++--
target/i386/host-cpu.c | 5 +++--
target/i386/kvm/kvm-cpu.c | 4 ++--
target/i386/tcg/tcg-cpu.c | 6 ++++--
8 files changed, 18 insertions(+), 14 deletions(-)
diff --git a/include/hw/core/accel-cpu.h b/include/hw/core/accel-cpu.h
index 24a6697412..5dbfd79955 100644
--- a/include/hw/core/accel-cpu.h
+++ b/include/hw/core/accel-cpu.h
@@ -32,7 +32,7 @@ typedef struct AccelCPUClass {
void (*cpu_class_init)(CPUClass *cc);
void (*cpu_instance_init)(CPUState *cpu);
- void (*cpu_realizefn)(CPUState *cpu, Error **errp);
+ bool (*cpu_realizefn)(CPUState *cpu, Error **errp);
} AccelCPUClass;
#endif /* ACCEL_CPU_H */
diff --git a/include/qemu/accel.h b/include/qemu/accel.h
index da0c8ab523..4f4c283f6f 100644
--- a/include/qemu/accel.h
+++ b/include/qemu/accel.h
@@ -89,6 +89,6 @@ void accel_cpu_instance_init(CPUState *cpu);
* @cpu: The CPU that needs to call accel-specific cpu realization.
* @errp: currently unused.
*/
-void accel_cpu_realizefn(CPUState *cpu, Error **errp);
+bool accel_cpu_realizefn(CPUState *cpu, Error **errp);
#endif /* QEMU_ACCEL_H */
diff --git a/target/i386/host-cpu.h b/target/i386/host-cpu.h
index b47bc0943f..6a9bc918ba 100644
--- a/target/i386/host-cpu.h
+++ b/target/i386/host-cpu.h
@@ -12,7 +12,7 @@
void host_cpu_instance_init(X86CPU *cpu);
void host_cpu_max_instance_init(X86CPU *cpu);
-void host_cpu_realizefn(CPUState *cs, Error **errp);
+bool host_cpu_realizefn(CPUState *cs, Error **errp);
void host_cpu_vendor_fms(char *vendor, int *family, int *model, int *stepping);
diff --git a/accel/accel-common.c b/accel/accel-common.c
index 0f6fb4fb66..d77c09d7b5 100644
--- a/accel/accel-common.c
+++ b/accel/accel-common.c
@@ -98,14 +98,14 @@ void accel_cpu_instance_init(CPUState *cpu)
}
}
-void accel_cpu_realizefn(CPUState *cpu, Error **errp)
+bool accel_cpu_realizefn(CPUState *cpu, Error **errp)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
if (cc->accel_cpu && cc->accel_cpu->cpu_realizefn) {
- /* NB: errp parameter is unused currently */
- cc->accel_cpu->cpu_realizefn(cpu, errp);
+ return cc->accel_cpu->cpu_realizefn(cpu, errp);
}
+ return true;
}
static const TypeInfo accel_cpu_type = {
diff --git a/cpu.c b/cpu.c
index 25e6fbfa2c..34a0484bf4 100644
--- a/cpu.c
+++ b/cpu.c
@@ -130,8 +130,9 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp)
CPUClass *cc = CPU_GET_CLASS(cpu);
cpu_list_add(cpu);
- accel_cpu_realizefn(cpu, errp);
-
+ if (!accel_cpu_realizefn(cpu, errp)) {
+ return;
+ }
#ifdef CONFIG_TCG
/* NB: errp parameter is unused currently */
if (tcg_enabled()) {
diff --git a/target/i386/host-cpu.c b/target/i386/host-cpu.c
index d07d41c34c..4ea9e354ea 100644
--- a/target/i386/host-cpu.c
+++ b/target/i386/host-cpu.c
@@ -80,7 +80,7 @@ static uint32_t host_cpu_adjust_phys_bits(X86CPU *cpu)
return phys_bits;
}
-void host_cpu_realizefn(CPUState *cs, Error **errp)
+bool host_cpu_realizefn(CPUState *cs, Error **errp)
{
X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &cpu->env;
@@ -97,10 +97,11 @@ void host_cpu_realizefn(CPUState *cs, Error **errp)
error_setg(errp, "phys-bits should be between 32 and %u "
" (but is %u)",
TARGET_PHYS_ADDR_SPACE_BITS, phys_bits);
- return;
+ return false;
}
cpu->phys_bits = phys_bits;
}
+ return true;
}
#define CPUID_MODEL_ID_SZ 48
diff --git a/target/i386/kvm/kvm-cpu.c b/target/i386/kvm/kvm-cpu.c
index c23bbe6c50..c660ad4293 100644
--- a/target/i386/kvm/kvm-cpu.c
+++ b/target/i386/kvm/kvm-cpu.c
@@ -18,7 +18,7 @@
#include "kvm_i386.h"
#include "hw/core/accel-cpu.h"
-static void kvm_cpu_realizefn(CPUState *cs, Error **errp)
+static bool kvm_cpu_realizefn(CPUState *cs, Error **errp)
{
X86CPU *cpu = X86_CPU(cs);
CPUX86State *env = &cpu->env;
@@ -41,7 +41,7 @@ static void kvm_cpu_realizefn(CPUState *cs, Error **errp)
MSR_IA32_UCODE_REV);
}
}
- host_cpu_realizefn(cs, errp);
+ return host_cpu_realizefn(cs, errp);
}
/*
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index 1d3d6d1c6a..23e1f5f0c3 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -96,7 +96,7 @@ static void x86_cpu_machine_done(Notifier *n, void *unused)
}
}
-static void tcg_cpu_realizefn(CPUState *cs, Error **errp)
+static bool tcg_cpu_realizefn(CPUState *cs, Error **errp)
{
X86CPU *cpu = X86_CPU(cs);
@@ -132,12 +132,14 @@ static void tcg_cpu_realizefn(CPUState *cs, Error **errp)
/* ... SMRAM with higher priority, linked from /machine/smram. */
cpu->machine_done.notify = x86_cpu_machine_done;
qemu_add_machine_init_done_notifier(&cpu->machine_done);
+ return true;
}
#else /* CONFIG_USER_ONLY */
-static void tcg_cpu_realizefn(CPUState *cs, Error **errp)
+static bool tcg_cpu_realizefn(CPUState *cs, Error **errp)
{
+ return true;
}
#endif /* !CONFIG_USER_ONLY */
--
2.26.2
next prev parent reply other threads:[~2021-02-12 12:51 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-12 12:36 [RFC v18 00/15] i386 cleanup PART 2 Claudio Fontana
2021-02-12 12:36 ` [RFC v18 01/15] i386: split cpu accelerators from cpu.c, using AccelCPUClass Claudio Fontana
2021-02-15 11:29 ` Alex Bennée
2021-02-12 12:36 ` [RFC v18 02/15] cpu: call AccelCPUClass::cpu_realizefn in cpu_exec_realizefn Claudio Fontana
2021-02-15 11:30 ` Alex Bennée
2021-02-12 12:36 ` [RFC v18 03/15] accel: introduce new accessor functions Claudio Fontana
2021-02-15 11:34 ` Alex Bennée
2021-02-12 12:36 ` [RFC v18 04/15] target/i386: fix host_cpu_adjust_phys_bits error handling Claudio Fontana
2021-02-12 12:36 ` Claudio Fontana [this message]
2021-02-12 12:36 ` [RFC v18 06/15] meson: add target_user_arch Claudio Fontana
2021-02-15 11:37 ` Alex Bennée
2021-02-12 12:36 ` [RFC v18 07/15] i386: split off softmmu-only functionality in tcg-cpu Claudio Fontana
2021-02-12 12:36 ` [RFC v18 08/15] i386: split smm helper (softmmu) Claudio Fontana
2021-02-15 11:51 ` Claudio Fontana
2021-02-15 12:32 ` Alex Bennée
2021-02-15 12:59 ` Claudio Fontana
2021-02-15 13:30 ` Paolo Bonzini
2021-02-15 14:05 ` Claudio Fontana
2021-02-15 14:13 ` Paolo Bonzini
2021-02-15 14:39 ` Claudio Fontana
2021-02-15 15:33 ` Claudio Fontana
2021-02-12 12:36 ` [RFC v18 09/15] i386: split tcg excp_helper into softmmu and user parts Claudio Fontana
2021-02-12 12:36 ` [RFC v18 10/15] i386: split tcg btp_helper " Claudio Fontana
2021-02-15 11:55 ` Claudio Fontana
2021-02-12 12:36 ` [RFC v18 11/15] i386: split misc helper into user and softmmu parts Claudio Fontana
2021-02-12 12:36 ` [RFC v18 12/15] i386: separate fpu_helper " Claudio Fontana
2021-02-15 10:32 ` Alex Bennée
2021-02-12 12:36 ` [RFC v18 13/15] i386: slit svm_helper into softmmu and stub-only user Claudio Fontana
2021-02-12 12:36 ` [RFC v18 14/15] i386: split seg_helper into user-only and softmmu parts Claudio Fontana
2021-02-12 12:36 ` [RFC v18 15/15] i386: split off softmmu part of cpu.c Claudio Fontana
2021-02-12 12:57 ` [RFC v18 00/15] i386 cleanup PART 2 no-reply
2021-02-15 11:37 ` Alex Bennée
2021-02-15 11:48 ` Claudio Fontana
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