From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [PATCH v7 31/31] tests/tcg/aarch64: Add mte smoke tests
Date: Fri, 12 Feb 2021 10:49:02 -0800 [thread overview]
Message-ID: <20210212184902.1251044-32-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210212184902.1251044-1-richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tests/tcg/aarch64/mte.h | 60 +++++++++++++++++++++++++++++++
tests/tcg/aarch64/mte-1.c | 28 +++++++++++++++
tests/tcg/aarch64/mte-2.c | 45 +++++++++++++++++++++++
tests/tcg/aarch64/mte-3.c | 51 ++++++++++++++++++++++++++
tests/tcg/aarch64/mte-4.c | 45 +++++++++++++++++++++++
tests/tcg/aarch64/Makefile.target | 6 ++++
tests/tcg/configure.sh | 4 +++
7 files changed, 239 insertions(+)
create mode 100644 tests/tcg/aarch64/mte.h
create mode 100644 tests/tcg/aarch64/mte-1.c
create mode 100644 tests/tcg/aarch64/mte-2.c
create mode 100644 tests/tcg/aarch64/mte-3.c
create mode 100644 tests/tcg/aarch64/mte-4.c
diff --git a/tests/tcg/aarch64/mte.h b/tests/tcg/aarch64/mte.h
new file mode 100644
index 0000000000..141cef522c
--- /dev/null
+++ b/tests/tcg/aarch64/mte.h
@@ -0,0 +1,60 @@
+/*
+ * Linux kernel fallback API definitions for MTE and test helpers.
+ *
+ * Copyright (c) 2021 Linaro Ltd
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <assert.h>
+#include <string.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <unistd.h>
+#include <signal.h>
+#include <sys/mman.h>
+#include <sys/prctl.h>
+
+#ifndef PR_SET_TAGGED_ADDR_CTRL
+# define PR_SET_TAGGED_ADDR_CTRL 55
+#endif
+#ifndef PR_TAGGED_ADDR_ENABLE
+# define PR_TAGGED_ADDR_ENABLE (1UL << 0)
+#endif
+#ifndef PR_MTE_TCF_SHIFT
+# define PR_MTE_TCF_SHIFT 1
+# define PR_MTE_TCF_NONE (0UL << PR_MTE_TCF_SHIFT)
+# define PR_MTE_TCF_SYNC (1UL << PR_MTE_TCF_SHIFT)
+# define PR_MTE_TCF_ASYNC (2UL << PR_MTE_TCF_SHIFT)
+# define PR_MTE_TAG_SHIFT 3
+#endif
+
+#ifndef PROT_MTE
+# define PROT_MTE 0x20
+#endif
+
+#ifndef SEGV_MTEAERR
+# define SEGV_MTEAERR 8
+# define SEGV_MTESERR 9
+#endif
+
+static void enable_mte(int tcf)
+{
+ int r = prctl(PR_SET_TAGGED_ADDR_CTRL,
+ PR_TAGGED_ADDR_ENABLE | tcf | (0xfffe << PR_MTE_TAG_SHIFT),
+ 0, 0, 0);
+ if (r < 0) {
+ perror("PR_SET_TAGGED_ADDR_CTRL");
+ exit(2);
+ }
+}
+
+static void *alloc_mte_mem(size_t size)
+{
+ void *p = mmap(NULL, size, PROT_READ | PROT_WRITE | PROT_MTE,
+ MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
+ if (p == MAP_FAILED) {
+ perror("mmap PROT_MTE");
+ exit(2);
+ }
+ return p;
+}
diff --git a/tests/tcg/aarch64/mte-1.c b/tests/tcg/aarch64/mte-1.c
new file mode 100644
index 0000000000..88dcd617ad
--- /dev/null
+++ b/tests/tcg/aarch64/mte-1.c
@@ -0,0 +1,28 @@
+/*
+ * Memory tagging, basic pass cases.
+ *
+ * Copyright (c) 2021 Linaro Ltd
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "mte.h"
+
+int main(int ac, char **av)
+{
+ int *p0, *p1, *p2;
+ long c;
+
+ enable_mte(PR_MTE_TCF_NONE);
+ p0 = alloc_mte_mem(sizeof(*p0));
+
+ asm("irg %0,%1,%2" : "=r"(p1) : "r"(p0), "r"(1));
+ assert(p1 != p0);
+ asm("subp %0,%1,%2" : "=r"(c) : "r"(p0), "r"(p1));
+ assert(c == 0);
+
+ asm("stg %0, [%0]" : : "r"(p1));
+ asm("ldg %0, [%1]" : "=r"(p2) : "r"(p0), "0"(p0));
+ assert(p1 == p2);
+
+ return 0;
+}
diff --git a/tests/tcg/aarch64/mte-2.c b/tests/tcg/aarch64/mte-2.c
new file mode 100644
index 0000000000..a62278276a
--- /dev/null
+++ b/tests/tcg/aarch64/mte-2.c
@@ -0,0 +1,45 @@
+/*
+ * Memory tagging, basic fail cases, synchronous signals.
+ *
+ * Copyright (c) 2021 Linaro Ltd
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "mte.h"
+
+void pass(int sig, siginfo_t *info, void *uc)
+{
+ assert(info->si_code == SEGV_MTESERR);
+ exit(0);
+}
+
+int main(int ac, char **av)
+{
+ struct sigaction sa;
+ int *p0, *p1, *p2;
+ long excl = 1;
+
+ enable_mte(PR_MTE_TCF_SYNC);
+ p0 = alloc_mte_mem(sizeof(*p0));
+
+ /* Create two differently tagged pointers. */
+ asm("irg %0,%1,%2" : "=r"(p1) : "r"(p0), "r"(excl));
+ asm("gmi %0,%1,%0" : "+r"(excl) : "r" (p1));
+ assert(excl != 1);
+ asm("irg %0,%1,%2" : "=r"(p2) : "r"(p0), "r"(excl));
+ assert(p1 != p2);
+
+ /* Store the tag from the first pointer. */
+ asm("stg %0, [%0]" : : "r"(p1));
+
+ *p1 = 0;
+
+ memset(&sa, 0, sizeof(sa));
+ sa.sa_sigaction = pass;
+ sa.sa_flags = SA_SIGINFO;
+ sigaction(SIGSEGV, &sa, NULL);
+
+ *p2 = 0;
+
+ abort();
+}
diff --git a/tests/tcg/aarch64/mte-3.c b/tests/tcg/aarch64/mte-3.c
new file mode 100644
index 0000000000..424ea685c2
--- /dev/null
+++ b/tests/tcg/aarch64/mte-3.c
@@ -0,0 +1,51 @@
+/*
+ * Memory tagging, basic fail cases, asynchronous signals.
+ *
+ * Copyright (c) 2021 Linaro Ltd
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "mte.h"
+
+void pass(int sig, siginfo_t *info, void *uc)
+{
+ assert(info->si_code == SEGV_MTEAERR);
+ exit(0);
+}
+
+int main(int ac, char **av)
+{
+ struct sigaction sa;
+ long *p0, *p1, *p2;
+ long excl = 1;
+
+ enable_mte(PR_MTE_TCF_ASYNC);
+ p0 = alloc_mte_mem(sizeof(*p0));
+
+ /* Create two differently tagged pointers. */
+ asm("irg %0,%1,%2" : "=r"(p1) : "r"(p0), "r"(excl));
+ asm("gmi %0,%1,%0" : "+r"(excl) : "r" (p1));
+ assert(excl != 1);
+ asm("irg %0,%1,%2" : "=r"(p2) : "r"(p0), "r"(excl));
+ assert(p1 != p2);
+
+ /* Store the tag from the first pointer. */
+ asm("stg %0, [%0]" : : "r"(p1));
+
+ *p1 = 0;
+
+ memset(&sa, 0, sizeof(sa));
+ sa.sa_sigaction = pass;
+ sa.sa_flags = SA_SIGINFO;
+ sigaction(SIGSEGV, &sa, NULL);
+
+ /*
+ * Signal for async error will happen eventually.
+ * For a real kernel this should be after the next IRQ (e.g. timer).
+ * For qemu linux-user, we kick the cpu and exit at the next TB.
+ * In either case, loop until this happens (or killed by timeout).
+ * For extra sauce, yield, producing EXCP_YIELD to cpu_loop().
+ */
+ asm("str %0, [%0]; yield" : : "r"(p2));
+ while (1);
+}
diff --git a/tests/tcg/aarch64/mte-4.c b/tests/tcg/aarch64/mte-4.c
new file mode 100644
index 0000000000..a8cc9f5984
--- /dev/null
+++ b/tests/tcg/aarch64/mte-4.c
@@ -0,0 +1,45 @@
+/*
+ * Memory tagging, re-reading tag checks.
+ *
+ * Copyright (c) 2021 Linaro Ltd
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "mte.h"
+
+void __attribute__((noinline)) tagset(void *p, size_t size)
+{
+ size_t i;
+ for (i = 0; i < size; i += 16) {
+ asm("stg %0, [%0]" : : "r"(p + i));
+ }
+}
+
+void __attribute__((noinline)) tagcheck(void *p, size_t size)
+{
+ size_t i;
+ void *c;
+
+ for (i = 0; i < size; i += 16) {
+ asm("ldg %0, [%1]" : "=r"(c) : "r"(p + i), "0"(p));
+ assert(c == p);
+ }
+}
+
+int main(int ac, char **av)
+{
+ size_t size = getpagesize() * 4;
+ long excl = 1;
+ int *p0, *p1;
+
+ enable_mte(PR_MTE_TCF_ASYNC);
+ p0 = alloc_mte_mem(size);
+
+ /* Tag the pointer. */
+ asm("irg %0,%1,%2" : "=r"(p1) : "r"(p0), "r"(excl));
+
+ tagset(p1, size);
+ tagcheck(p1, size);
+
+ return 0;
+}
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
index d7d33e293c..bf53ad0087 100644
--- a/tests/tcg/aarch64/Makefile.target
+++ b/tests/tcg/aarch64/Makefile.target
@@ -35,6 +35,12 @@ endif
# bti-2 tests PROT_BTI, so no special compiler support required.
AARCH64_TESTS += bti-2
+# MTE Tests
+ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_ARMV8_MTE),)
+AARCH64_TESTS += mte-1 mte-2 mte-3 mte-4
+mte-%: CFLAGS += -march=armv8.5-a+memtag
+endif
+
# Semihosting smoke test for linux-user
AARCH64_TESTS += semihosting
run-semihosting: semihosting
diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh
index e1b70e25f2..ba8ac9a93e 100755
--- a/tests/tcg/configure.sh
+++ b/tests/tcg/configure.sh
@@ -244,6 +244,10 @@ for target in $target_list; do
-mbranch-protection=standard -o $TMPE $TMPC; then
echo "CROSS_CC_HAS_ARMV8_BTI=y" >> $config_target_mak
fi
+ if do_compiler "$target_compiler" $target_compiler_cflags \
+ -march=armv8.5-a+memtag -o $TMPE $TMPC; then
+ echo "CROSS_CC_HAS_ARMV8_MTE=y" >> $config_target_mak
+ fi
;;
esac
--
2.25.1
next prev parent reply other threads:[~2021-02-12 19:34 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-12 18:48 [PATCH v7 00/31] target-arm: Implement ARMv8.5-MemTag, user mode Richard Henderson
2021-02-12 18:48 ` [PATCH v7 01/31] tcg: Introduce target-specific page data for user-only Richard Henderson
2021-02-12 18:48 ` [PATCH v7 02/31] linux-user: Introduce PAGE_ANON Richard Henderson
2021-02-12 18:48 ` [PATCH v7 03/31] exec: Use uintptr_t for guest_base Richard Henderson
2021-02-12 18:58 ` Philippe Mathieu-Daudé
2021-02-12 18:48 ` [PATCH v7 04/31] exec: Use uintptr_t in cpu_ldst.h Richard Henderson
2021-02-12 19:05 ` Philippe Mathieu-Daudé
2021-02-12 18:48 ` [PATCH v7 05/31] exec: Improve types for guest_addr_valid Richard Henderson
2021-02-12 19:07 ` Philippe Mathieu-Daudé
2021-02-12 18:48 ` [PATCH v7 06/31] linux-user: Check for overflow in access_ok Richard Henderson
2021-02-12 18:48 ` [PATCH v7 07/31] linux-user: Tidy VERIFY_READ/VERIFY_WRITE Richard Henderson
2021-02-12 18:48 ` [PATCH v7 08/31] bsd-user: " Richard Henderson
2021-02-12 18:48 ` [PATCH v7 09/31] linux-user: Do not use guest_addr_valid for h2g_valid Richard Henderson
2021-02-12 18:48 ` [PATCH v7 10/31] linux-user: Fix guest_addr_valid vs reserved_va Richard Henderson
2021-02-12 18:48 ` [PATCH v7 11/31] exec: Introduce cpu_untagged_addr Richard Henderson
2021-02-12 18:48 ` [PATCH v7 12/31] exec: Use cpu_untagged_addr in g2h; split out g2h_untagged Richard Henderson
2021-02-12 18:48 ` [PATCH v7 13/31] linux-user: Explicitly untag memory management syscalls Richard Henderson
2021-02-12 18:48 ` [PATCH v7 14/31] linux-user: Use guest_range_valid in access_ok Richard Henderson
2021-02-12 18:48 ` [PATCH v7 15/31] exec: Rename guest_{addr,range}_valid to *_untagged Richard Henderson
2021-02-12 18:48 ` [PATCH v7 16/31] linux-user: Use cpu_untagged_addr in access_ok; split out *_untagged Richard Henderson
2021-02-12 18:48 ` [PATCH v7 17/31] linux-user: Move lock_user et al out of line Richard Henderson
2021-02-12 20:35 ` Philippe Mathieu-Daudé
2021-02-16 12:57 ` Peter Maydell
2021-02-12 18:48 ` [PATCH v7 18/31] linux-user: Fix types in uaccess.c Richard Henderson
2021-02-12 20:34 ` Philippe Mathieu-Daudé
2021-02-12 18:48 ` [PATCH v7 19/31] linux-user: Handle tags in lock_user/unlock_user Richard Henderson
2021-02-12 18:48 ` [PATCH v7 20/31] linux-user/aarch64: Implement PR_TAGGED_ADDR_ENABLE Richard Henderson
2021-02-12 18:48 ` [PATCH v7 21/31] target/arm: Improve gen_top_byte_ignore Richard Henderson
2021-02-12 18:48 ` [PATCH v7 22/31] target/arm: Use the proper TBI settings for linux-user Richard Henderson
2021-02-12 18:48 ` [PATCH v7 23/31] linux-user/aarch64: Implement PR_MTE_TCF and PR_MTE_TAG Richard Henderson
2021-02-12 18:48 ` [PATCH v7 24/31] linux-user/aarch64: Implement PROT_MTE Richard Henderson
2021-02-12 18:48 ` [PATCH v7 25/31] target/arm: Split out syndrome.h from internals.h Richard Henderson
2021-02-12 19:07 ` Philippe Mathieu-Daudé
2021-02-12 18:48 ` [PATCH v7 26/31] linux-user/aarch64: Pass syndrome to EXC_*_ABORT Richard Henderson
2021-02-12 18:48 ` [PATCH v7 27/31] linux-user/aarch64: Signal SEGV_MTESERR for sync tag check fault Richard Henderson
2021-02-12 18:48 ` [PATCH v7 28/31] linux-user/aarch64: Signal SEGV_MTEAERR for async tag check error Richard Henderson
2021-02-12 18:49 ` [PATCH v7 29/31] target/arm: Add allocation tag storage for user mode Richard Henderson
2021-02-12 18:49 ` [PATCH v7 30/31] target/arm: Enable MTE for user-only Richard Henderson
2021-02-12 18:49 ` Richard Henderson [this message]
2021-02-12 19:39 ` [PATCH v7 00/31] target-arm: Implement ARMv8.5-MemTag, user mode no-reply
2021-02-16 13:49 ` Peter Maydell
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