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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id 3sm3001576pjk.26.2021.02.17.12.22.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:22:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 10/71] tcg/tci: Remove tci_read_r32s Date: Wed, 17 Feb 2021 12:19:35 -0800 Message-Id: <20210217202036.1724901-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Use explicit casts for ext32s opcodes. Signed-off-by: Richard Henderson --- tcg/tci.c | 20 ++------------------ 1 file changed, 2 insertions(+), 18 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index a5aaa763f8..cef12f263d 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -57,13 +57,6 @@ static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg index) return regs[index]; } -#if TCG_TARGET_REG_BITS == 64 -static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index) -{ - return (int32_t)tci_read_reg(regs, index); -} -#endif - #if TCG_TARGET_REG_BITS == 64 static uint64_t tci_read_reg64(const tcg_target_ulong *regs, TCGReg index) { @@ -149,15 +142,6 @@ static uint64_t tci_read_r64(const tcg_target_ulong *regs, return tci_uint64(tci_read_r(regs, tb_ptr), low); } #elif TCG_TARGET_REG_BITS == 64 -/* Read indexed register (32 bit signed) from bytecode. */ -static int32_t tci_read_r32s(const tcg_target_ulong *regs, - const uint8_t **tb_ptr) -{ - int32_t value = tci_read_reg32s(regs, **tb_ptr); - *tb_ptr += 1; - return value; -} - /* Read indexed register (64 bit) from bytecode. */ static uint64_t tci_read_r64(const tcg_target_ulong *regs, const uint8_t **tb_ptr) @@ -870,8 +854,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #endif case INDEX_op_ext_i32_i64: t0 = *tb_ptr++; - t1 = tci_read_r32s(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (int32_t)t1); break; #if TCG_TARGET_HAS_ext32u_i64 case INDEX_op_ext32u_i64: -- 2.25.1