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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org
Subject: [PATCH v4 11/71] tcg/tci: Reduce use of tci_read_r64
Date: Wed, 17 Feb 2021 12:19:36 -0800	[thread overview]
Message-ID: <20210217202036.1724901-12-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org>

In all cases restricted to 64-bit hosts, tcg_read_r is
identical.  We retain the 64-bit symbol for the single
case of INDEX_op_qemu_st_i64.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/tci.c | 93 +++++++++++++++++++++++++------------------------------
 1 file changed, 42 insertions(+), 51 deletions(-)

diff --git a/tcg/tci.c b/tcg/tci.c
index cef12f263d..9efe69d05f 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -57,13 +57,6 @@ static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg index)
     return regs[index];
 }
 
-#if TCG_TARGET_REG_BITS == 64
-static uint64_t tci_read_reg64(const tcg_target_ulong *regs, TCGReg index)
-{
-    return tci_read_reg(regs, index);
-}
-#endif
-
 static void
 tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value)
 {
@@ -146,9 +139,7 @@ static uint64_t tci_read_r64(const tcg_target_ulong *regs,
 static uint64_t tci_read_r64(const tcg_target_ulong *regs,
                              const uint8_t **tb_ptr)
 {
-    uint64_t value = tci_read_reg64(regs, **tb_ptr);
-    *tb_ptr += 1;
-    return value;
+    return tci_read_r(regs, tb_ptr);
 }
 #endif
 
@@ -390,8 +381,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
 #elif TCG_TARGET_REG_BITS == 64
         case INDEX_op_setcond_i64:
             t0 = *tb_ptr++;
-            t1 = tci_read_r64(regs, &tb_ptr);
-            t2 = tci_read_r64(regs, &tb_ptr);
+            t1 = tci_read_r(regs, &tb_ptr);
+            t2 = tci_read_r(regs, &tb_ptr);
             condition = *tb_ptr++;
             tci_write_reg(regs, t0, tci_compare64(t1, t2, condition));
             break;
@@ -672,7 +663,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
 #if TCG_TARGET_REG_BITS == 64
         case INDEX_op_mov_i64:
             t0 = *tb_ptr++;
-            t1 = tci_read_r64(regs, &tb_ptr);
+            t1 = tci_read_r(regs, &tb_ptr);
             tci_write_reg(regs, t0, t1);
             break;
         case INDEX_op_tci_movi_i64:
@@ -696,7 +687,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
             tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2));
             break;
         case INDEX_op_st_i64:
-            t0 = tci_read_r64(regs, &tb_ptr);
+            t0 = tci_read_r(regs, &tb_ptr);
             t1 = tci_read_r(regs, &tb_ptr);
             t2 = tci_read_s32(&tb_ptr);
             *(uint64_t *)(t1 + t2) = t0;
@@ -706,62 +697,62 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
 
         case INDEX_op_add_i64:
             t0 = *tb_ptr++;
-            t1 = tci_read_r64(regs, &tb_ptr);
-            t2 = tci_read_r64(regs, &tb_ptr);
+            t1 = tci_read_r(regs, &tb_ptr);
+            t2 = tci_read_r(regs, &tb_ptr);
             tci_write_reg(regs, t0, t1 + t2);
             break;
         case INDEX_op_sub_i64:
             t0 = *tb_ptr++;
-            t1 = tci_read_r64(regs, &tb_ptr);
-            t2 = tci_read_r64(regs, &tb_ptr);
+            t1 = tci_read_r(regs, &tb_ptr);
+            t2 = tci_read_r(regs, &tb_ptr);
             tci_write_reg(regs, t0, t1 - t2);
             break;
         case INDEX_op_mul_i64:
             t0 = *tb_ptr++;
-            t1 = tci_read_r64(regs, &tb_ptr);
-            t2 = tci_read_r64(regs, &tb_ptr);
+            t1 = tci_read_r(regs, &tb_ptr);
+            t2 = tci_read_r(regs, &tb_ptr);
             tci_write_reg(regs, t0, t1 * t2);
             break;
         case INDEX_op_div_i64:
             t0 = *tb_ptr++;
-            t1 = tci_read_r64(regs, &tb_ptr);
-            t2 = tci_read_r64(regs, &tb_ptr);
+            t1 = tci_read_r(regs, &tb_ptr);
+            t2 = tci_read_r(regs, &tb_ptr);
             tci_write_reg(regs, t0, (int64_t)t1 / (int64_t)t2);
             break;
         case INDEX_op_divu_i64:
             t0 = *tb_ptr++;
-            t1 = tci_read_r64(regs, &tb_ptr);
-            t2 = tci_read_r64(regs, &tb_ptr);
+            t1 = tci_read_r(regs, &tb_ptr);
+            t2 = tci_read_r(regs, &tb_ptr);
             tci_write_reg(regs, t0, (uint64_t)t1 / (uint64_t)t2);
             break;
         case INDEX_op_rem_i64:
             t0 = *tb_ptr++;
-            t1 = tci_read_r64(regs, &tb_ptr);
-            t2 = tci_read_r64(regs, &tb_ptr);
+            t1 = tci_read_r(regs, &tb_ptr);
+            t2 = tci_read_r(regs, &tb_ptr);
             tci_write_reg(regs, t0, (int64_t)t1 % (int64_t)t2);
             break;
         case INDEX_op_remu_i64:
             t0 = *tb_ptr++;
-            t1 = tci_read_r64(regs, &tb_ptr);
-            t2 = tci_read_r64(regs, &tb_ptr);
+            t1 = tci_read_r(regs, &tb_ptr);
+            t2 = tci_read_r(regs, &tb_ptr);
             tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2);
             break;
         case INDEX_op_and_i64:
             t0 = *tb_ptr++;
-            t1 = tci_read_r64(regs, &tb_ptr);
-            t2 = tci_read_r64(regs, &tb_ptr);
+            t1 = tci_read_r(regs, &tb_ptr);
+            t2 = tci_read_r(regs, &tb_ptr);
             tci_write_reg(regs, t0, t1 & t2);
             break;
         case INDEX_op_or_i64:
             t0 = *tb_ptr++;
-            t1 = tci_read_r64(regs, &tb_ptr);
-            t2 = tci_read_r64(regs, &tb_ptr);
+            t1 = tci_read_r(regs, &tb_ptr);
+            t2 = tci_read_r(regs, &tb_ptr);
             tci_write_reg(regs, t0, t1 | t2);
             break;
         case INDEX_op_xor_i64:
             t0 = *tb_ptr++;
-            t1 = tci_read_r64(regs, &tb_ptr);
-            t2 = tci_read_r64(regs, &tb_ptr);
+            t1 = tci_read_r(regs, &tb_ptr);
+            t2 = tci_read_r(regs, &tb_ptr);
             tci_write_reg(regs, t0, t1 ^ t2);
             break;
 
@@ -769,41 +760,41 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
 
         case INDEX_op_shl_i64:
             t0 = *tb_ptr++;
-            t1 = tci_read_r64(regs, &tb_ptr);
-            t2 = tci_read_r64(regs, &tb_ptr);
+            t1 = tci_read_r(regs, &tb_ptr);
+            t2 = tci_read_r(regs, &tb_ptr);
             tci_write_reg(regs, t0, t1 << (t2 & 63));
             break;
         case INDEX_op_shr_i64:
             t0 = *tb_ptr++;
-            t1 = tci_read_r64(regs, &tb_ptr);
-            t2 = tci_read_r64(regs, &tb_ptr);
+            t1 = tci_read_r(regs, &tb_ptr);
+            t2 = tci_read_r(regs, &tb_ptr);
             tci_write_reg(regs, t0, t1 >> (t2 & 63));
             break;
         case INDEX_op_sar_i64:
             t0 = *tb_ptr++;
-            t1 = tci_read_r64(regs, &tb_ptr);
-            t2 = tci_read_r64(regs, &tb_ptr);
+            t1 = tci_read_r(regs, &tb_ptr);
+            t2 = tci_read_r(regs, &tb_ptr);
             tci_write_reg(regs, t0, ((int64_t)t1 >> (t2 & 63)));
             break;
 #if TCG_TARGET_HAS_rot_i64
         case INDEX_op_rotl_i64:
             t0 = *tb_ptr++;
-            t1 = tci_read_r64(regs, &tb_ptr);
-            t2 = tci_read_r64(regs, &tb_ptr);
+            t1 = tci_read_r(regs, &tb_ptr);
+            t2 = tci_read_r(regs, &tb_ptr);
             tci_write_reg(regs, t0, rol64(t1, t2 & 63));
             break;
         case INDEX_op_rotr_i64:
             t0 = *tb_ptr++;
-            t1 = tci_read_r64(regs, &tb_ptr);
-            t2 = tci_read_r64(regs, &tb_ptr);
+            t1 = tci_read_r(regs, &tb_ptr);
+            t2 = tci_read_r(regs, &tb_ptr);
             tci_write_reg(regs, t0, ror64(t1, t2 & 63));
             break;
 #endif
 #if TCG_TARGET_HAS_deposit_i64
         case INDEX_op_deposit_i64:
             t0 = *tb_ptr++;
-            t1 = tci_read_r64(regs, &tb_ptr);
-            t2 = tci_read_r64(regs, &tb_ptr);
+            t1 = tci_read_r(regs, &tb_ptr);
+            t2 = tci_read_r(regs, &tb_ptr);
             tmp16 = *tb_ptr++;
             tmp8 = *tb_ptr++;
             tmp64 = (((1ULL << tmp8) - 1) << tmp16);
@@ -811,8 +802,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
             break;
 #endif
         case INDEX_op_brcond_i64:
-            t0 = tci_read_r64(regs, &tb_ptr);
-            t1 = tci_read_r64(regs, &tb_ptr);
+            t0 = tci_read_r(regs, &tb_ptr);
+            t1 = tci_read_r(regs, &tb_ptr);
             condition = *tb_ptr++;
             label = tci_read_label(&tb_ptr);
             if (tci_compare64(t0, t1, condition)) {
@@ -882,21 +873,21 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
 #if TCG_TARGET_HAS_bswap64_i64
         case INDEX_op_bswap64_i64:
             t0 = *tb_ptr++;
-            t1 = tci_read_r64(regs, &tb_ptr);
+            t1 = tci_read_r(regs, &tb_ptr);
             tci_write_reg(regs, t0, bswap64(t1));
             break;
 #endif
 #if TCG_TARGET_HAS_not_i64
         case INDEX_op_not_i64:
             t0 = *tb_ptr++;
-            t1 = tci_read_r64(regs, &tb_ptr);
+            t1 = tci_read_r(regs, &tb_ptr);
             tci_write_reg(regs, t0, ~t1);
             break;
 #endif
 #if TCG_TARGET_HAS_neg_i64
         case INDEX_op_neg_i64:
             t0 = *tb_ptr++;
-            t1 = tci_read_r64(regs, &tb_ptr);
+            t1 = tci_read_r(regs, &tb_ptr);
             tci_write_reg(regs, t0, -t1);
             break;
 #endif
-- 
2.25.1



  parent reply	other threads:[~2021-02-17 20:26 UTC|newest]

Thread overview: 92+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-17 20:19 [PATCH v4 00/71] TCI fixes and cleanups Richard Henderson
2021-02-17 20:19 ` [PATCH v4 01/71] tcg/tci: Use exec/cpu_ldst.h interfaces Richard Henderson
2021-02-21 23:00   ` Philippe Mathieu-Daudé
2021-02-17 20:19 ` [PATCH v4 02/71] tcg: Split out tcg_raise_tb_overflow Richard Henderson
2021-02-18 22:22   ` Philippe Mathieu-Daudé
2021-02-17 20:19 ` [PATCH v4 03/71] tcg: Manage splitwx in tc_ptr_to_region_tree by hand Richard Henderson
2021-02-17 20:19 ` [PATCH v4 04/71] tcg/tci: Merge identical cases in generation Richard Henderson
2021-02-18 23:24   ` Philippe Mathieu-Daudé
2021-02-17 20:19 ` [PATCH v4 05/71] tcg/tci: Remove tci_read_r8 Richard Henderson
2021-02-18 23:11   ` Philippe Mathieu-Daudé
2021-02-18 23:33     ` Richard Henderson
2021-02-19  0:03       ` Philippe Mathieu-Daudé
2021-02-17 20:19 ` [PATCH v4 06/71] tcg/tci: Remove tci_read_r8s Richard Henderson
2021-02-18 23:12   ` Philippe Mathieu-Daudé
2021-02-17 20:19 ` [PATCH v4 07/71] tcg/tci: Remove tci_read_r16 Richard Henderson
2021-02-19  0:03   ` Philippe Mathieu-Daudé
2021-02-17 20:19 ` [PATCH v4 08/71] tcg/tci: Remove tci_read_r16s Richard Henderson
2021-02-18 23:15   ` Philippe Mathieu-Daudé
2021-02-17 20:19 ` [PATCH v4 09/71] tcg/tci: Remove tci_read_r32 Richard Henderson
2021-02-19  0:06   ` Philippe Mathieu-Daudé
2021-02-17 20:19 ` [PATCH v4 10/71] tcg/tci: Remove tci_read_r32s Richard Henderson
2021-02-18 23:16   ` Philippe Mathieu-Daudé
2021-02-17 20:19 ` Richard Henderson [this message]
2021-02-19  0:05   ` [PATCH v4 11/71] tcg/tci: Reduce use of tci_read_r64 Philippe Mathieu-Daudé
2021-02-17 20:19 ` [PATCH v4 12/71] tcg/tci: Merge basic arithmetic operations Richard Henderson
2021-02-18 23:17   ` Philippe Mathieu-Daudé
2021-02-17 20:19 ` [PATCH v4 13/71] tcg/tci: Merge extension operations Richard Henderson
2021-02-18 23:22   ` Philippe Mathieu-Daudé
2021-02-17 20:19 ` [PATCH v4 14/71] tcg/tci: Remove ifdefs for TCG_TARGET_HAS_ext32[us]_i64 Richard Henderson
2021-02-17 20:19 ` [PATCH v4 15/71] tcg/tci: Merge bswap operations Richard Henderson
2021-02-18 23:19   ` Philippe Mathieu-Daudé
2021-02-17 20:19 ` [PATCH v4 16/71] tcg/tci: Merge mov, not and neg operations Richard Henderson
2021-02-18 23:20   ` Philippe Mathieu-Daudé
2021-02-17 20:19 ` [PATCH v4 17/71] tcg/tci: Rename tci_read_r to tci_read_rval Richard Henderson
2021-02-17 20:19 ` [PATCH v4 18/71] tcg/tci: Split out tci_args_rrs Richard Henderson
2021-02-17 20:19 ` [PATCH v4 19/71] tcg/tci: Split out tci_args_rr Richard Henderson
2021-02-17 20:19 ` [PATCH v4 20/71] tcg/tci: Split out tci_args_rrr Richard Henderson
2021-02-17 20:19 ` [PATCH v4 21/71] tcg/tci: Split out tci_args_rrrc Richard Henderson
2021-02-17 20:19 ` [PATCH v4 22/71] tcg/tci: Split out tci_args_l Richard Henderson
2021-02-17 20:19 ` [PATCH v4 23/71] tcg/tci: Split out tci_args_rrrrrc Richard Henderson
2021-02-17 20:19 ` [PATCH v4 24/71] tcg/tci: Split out tci_args_rrcl and tci_args_rrrrcl Richard Henderson
2021-02-17 20:19 ` [PATCH v4 25/71] tcg/tci: Split out tci_args_ri and tci_args_rI Richard Henderson
2021-02-17 20:19 ` [PATCH v4 26/71] tcg/tci: Reuse tci_args_l for calls Richard Henderson
2021-02-17 20:19 ` [PATCH v4 27/71] tcg/tci: Reuse tci_args_l for exit_tb Richard Henderson
2021-02-17 20:19 ` [PATCH v4 28/71] tcg/tci: Reuse tci_args_l for goto_tb Richard Henderson
2021-02-17 20:19 ` [PATCH v4 29/71] tcg/tci: Split out tci_args_rrrrrr Richard Henderson
2021-02-17 20:19 ` [PATCH v4 30/71] tcg/tci: Split out tci_args_rrrr Richard Henderson
2021-02-17 20:19 ` [PATCH v4 31/71] tcg/tci: Clean up deposit operations Richard Henderson
2021-02-17 20:19 ` [PATCH v4 32/71] tcg/tci: Reduce qemu_ld/st TCGMemOpIdx operand to 32-bits Richard Henderson
2021-02-17 20:19 ` [PATCH v4 33/71] tcg/tci: Split out tci_args_{rrm,rrrm,rrrrm} Richard Henderson
2021-02-17 20:19 ` [PATCH v4 34/71] tcg/tci: Hoist op_size checking into tci_args_* Richard Henderson
2021-02-17 20:20 ` [PATCH v4 35/71] tcg/tci: Remove tci_disas Richard Henderson
2021-02-17 20:20 ` [PATCH v4 36/71] tcg/tci: Implement the disassembler properly Richard Henderson
2021-02-17 20:20 ` [PATCH v4 37/71] tcg: Build ffi data structures for helpers Richard Henderson
2021-02-17 20:20 ` [PATCH v4 38/71] tcg/tci: Use ffi for calls Richard Henderson
2021-02-17 20:20 ` [PATCH v4 39/71] tcg/tci: Improve tcg_target_call_clobber_regs Richard Henderson
2021-02-17 20:20 ` [PATCH v4 40/71] tcg/tci: Move call-return regs to end of tcg_target_reg_alloc_order Richard Henderson
2021-02-17 20:20 ` [PATCH v4 41/71] tcg/tci: Push opcode emit into each case Richard Henderson
2021-02-17 20:20 ` [PATCH v4 42/71] tcg/tci: Split out tcg_out_op_rrs Richard Henderson
2021-02-17 20:20 ` [PATCH v4 43/71] tcg/tci: Split out tcg_out_op_l Richard Henderson
2021-02-17 20:20 ` [PATCH v4 44/71] tcg/tci: Split out tcg_out_op_p Richard Henderson
2021-02-17 20:20 ` [PATCH v4 45/71] tcg/tci: Split out tcg_out_op_rr Richard Henderson
2021-02-17 20:20 ` [PATCH v4 46/71] tcg/tci: Split out tcg_out_op_rrr Richard Henderson
2021-02-17 20:20 ` [PATCH v4 47/71] tcg/tci: Split out tcg_out_op_rrrc Richard Henderson
2021-02-17 20:20 ` [PATCH v4 48/71] tcg/tci: Split out tcg_out_op_rrrrrc Richard Henderson
2021-02-17 20:20 ` [PATCH v4 49/71] tcg/tci: Split out tcg_out_op_rrrbb Richard Henderson
2021-02-17 20:20 ` [PATCH v4 50/71] tcg/tci: Split out tcg_out_op_rrcl Richard Henderson
2021-02-17 20:20 ` [PATCH v4 51/71] tcg/tci: Split out tcg_out_op_rrrrrr Richard Henderson
2021-02-17 20:20 ` [PATCH v4 52/71] tcg/tci: Split out tcg_out_op_rrrr Richard Henderson
2021-02-17 20:20 ` [PATCH v4 53/71] tcg/tci: Split out tcg_out_op_rrrrcl Richard Henderson
2021-02-17 20:20 ` [PATCH v4 54/71] tcg/tci: Split out tcg_out_op_{rrm,rrrm,rrrrm} Richard Henderson
2021-02-17 20:20 ` [PATCH v4 55/71] tcg/tci: Split out tcg_out_op_v Richard Henderson
2021-02-17 20:20 ` [PATCH v4 56/71] tcg/tci: Split out tcg_out_op_np Richard Henderson
2021-02-17 20:20 ` [PATCH v4 57/71] tcg/tci: Split out tcg_out_op_r[iI] Richard Henderson
2021-02-17 20:20 ` [PATCH v4 58/71] tcg/tci: Reserve r13 for a temporary Richard Henderson
2021-02-17 20:20 ` [PATCH v4 59/71] tcg/tci: Emit setcond before brcond Richard Henderson
2021-02-17 20:20 ` [PATCH v4 60/71] tcg/tci: Remove tci_write_reg Richard Henderson
2021-02-17 20:20 ` [PATCH v4 61/71] tcg/tci: Change encoding to uint32_t units Richard Henderson
2021-02-17 20:20 ` [PATCH v4 62/71] tcg/tci: Implement goto_ptr Richard Henderson
2021-02-17 20:20 ` [PATCH v4 63/71] tcg/tci: Implement movcond Richard Henderson
2021-02-17 20:20 ` [PATCH v4 64/71] tcg/tci: Implement andc, orc, eqv, nand, nor Richard Henderson
2021-02-17 20:20 ` [PATCH v4 65/71] tcg/tci: Implement extract, sextract Richard Henderson
2021-02-17 20:20 ` [PATCH v4 66/71] tcg/tci: Implement clz, ctz, ctpop Richard Henderson
2021-02-17 20:20 ` [PATCH v4 67/71] tcg/tci: Implement mulu2, muls2 Richard Henderson
2021-02-17 20:20 ` [PATCH v4 68/71] tcg/tci: Implement add2, sub2 Richard Henderson
2021-02-17 20:20 ` [PATCH v4 69/71] tcg/tci: Split out tci_qemu_ld, tci_qemu_st Richard Henderson
2021-02-17 20:20 ` [PATCH v4 70/71] tests/tcg: Increase timeout for TCI Richard Henderson
2021-02-18  6:09   ` Thomas Huth
2021-02-22  6:44     ` Richard Henderson
2021-02-17 20:20 ` [PATCH v4 71/71] gitlab: Enable cross-i386 builds of TCI Richard Henderson
2021-02-18  6:19   ` Thomas Huth
2021-02-17 21:37 ` [PATCH v4 00/71] TCI fixes and cleanups no-reply

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