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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id v126sm3232038pfv.163.2021.02.17.12.24.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 12:24:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 60/71] tcg/tci: Remove tci_write_reg Date: Wed, 17 Feb 2021 12:20:25 -0800 Message-Id: <20210217202036.1724901-61-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210217202036.1724901-1-richard.henderson@linaro.org> References: <20210217202036.1724901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sw@weilnetz.de, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Inline it into its one caller, tci_write_reg64. Drop the asserts that are redundant with tcg_read_r. Signed-off-by: Richard Henderson --- tcg/tci.c | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 3f8c6a0291..0b2bc905ea 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -36,20 +36,11 @@ __thread uintptr_t tci_tb_ptr; -static void -tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value) -{ - tci_assert(index < TCG_TARGET_NB_REGS); - tci_assert(index != TCG_AREG0); - tci_assert(index != TCG_REG_CALL_STACK); - regs[index] = value; -} - static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index, uint32_t low_index, uint64_t value) { - tci_write_reg(regs, low_index, value); - tci_write_reg(regs, high_index, value >> 32); + regs[low_index] = value; + regs[high_index] = value >> 32; } /* Create a 64 bit value from two 32 bit values. */ -- 2.25.1