From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
qemu-arm@nongnu.org, "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PATCH v2 2/3] target/arm/cpu: Update coding style to make checkpatch.pl happy
Date: Sun, 21 Feb 2021 23:26:16 +0100 [thread overview]
Message-ID: <20210221222617.2579610-3-f4bug@amsat.org> (raw)
In-Reply-To: <20210221222617.2579610-1-f4bug@amsat.org>
We will move this code in the next commit. Clean it up
first to avoid checkpatch.pl errors.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/arm/cpu.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index a772fd4926f..6865ea76466 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1972,7 +1972,8 @@ static void cortex_a8_initfn(Object *obj)
}
static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
- /* power_control should be set to maximum latency. Again,
+ /*
+ * power_control should be set to maximum latency. Again,
* default to 0 and set by private hook
*/
{ .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
@@ -2009,7 +2010,8 @@ static void cortex_a9_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
set_feature(&cpu->env, ARM_FEATURE_EL3);
- /* Note that A9 supports the MP extensions even for
+ /*
+ * Note that A9 supports the MP extensions even for
* A9UP and single-core A9MP (which are both different
* and valid configurations; we don't model A9UP).
*/
@@ -2046,7 +2048,8 @@ static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
MachineState *ms = MACHINE(qdev_get_machine());
- /* Linux wants the number of processors from here.
+ /*
+ * Linux wants the number of processors from here.
* Might as well set the interrupt-controller bit too.
*/
return ((ms->smp.cpus - 1) << 24) | (1 << 23);
@@ -2093,7 +2096,8 @@ static void cortex_a7_initfn(Object *obj)
cpu->isar.id_mmfr1 = 0x40000000;
cpu->isar.id_mmfr2 = 0x01240000;
cpu->isar.id_mmfr3 = 0x02102211;
- /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
+ /*
+ * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
* table 4-41 gives 0x02101110, which includes the arm div insns.
*/
cpu->isar.id_isar0 = 0x02101110;
--
2.26.2
next prev parent reply other threads:[~2021-02-21 22:28 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-21 22:26 [PATCH v2 0/3] target/arm: Restrict v7A TCG cpus to TCG accel Philippe Mathieu-Daudé
2021-02-21 22:26 ` [PATCH v2 1/3] target/arm: Restrict v8M IDAU to TCG Philippe Mathieu-Daudé
2021-03-09 13:41 ` Claudio Fontana
2021-03-09 14:18 ` Philippe Mathieu-Daudé
2021-03-09 14:55 ` Claudio Fontana
2021-03-10 11:46 ` Claudio Fontana
2021-03-10 13:42 ` Philippe Mathieu-Daudé
2021-03-10 13:45 ` Claudio Fontana
2021-03-10 14:00 ` Claudio Fontana
2021-03-10 14:19 ` Philippe Mathieu-Daudé
2021-02-21 22:26 ` Philippe Mathieu-Daudé [this message]
2021-02-21 22:26 ` [PATCH v2 3/3] target/arm: Restrict v7A TCG cpus to TCG accel Philippe Mathieu-Daudé
2021-03-11 10:43 ` Claudio Fontana
2021-03-18 9:47 ` Philippe Mathieu-Daudé
2021-03-18 9:56 ` Claudio Fontana
2021-03-18 10:47 ` Philippe Mathieu-Daudé
2021-03-18 11:09 ` Philippe Mathieu-Daudé
2021-03-18 11:21 ` Peter Maydell
2021-03-18 11:31 ` Philippe Mathieu-Daudé
2021-03-18 11:38 ` Peter Maydell
2021-03-18 12:37 ` Andrew Jones
2021-03-18 12:50 ` Claudio Fontana
2021-03-18 13:14 ` Philippe Mathieu-Daudé
2021-03-05 14:38 ` [PATCH v2 0/3] " Peter Maydell
2021-03-06 15:13 ` Philippe Mathieu-Daudé
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