* [PATCH v7 00/75] support vector extension v1.0
@ 2021-02-26 3:17 frank.chang
2021-02-26 3:17 ` [PATCH v7 01/75] target/riscv: drop vector 0.7.1 and add 1.0 support frank.chang
` (74 more replies)
0 siblings, 75 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:17 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: Frank Chang
From: Frank Chang <frank.chang@sifive.com>
This patchset implements the vector extension v1.0 for RISC-V on QEMU.
The port is available here:
https://github.com/sifive/qemu/tree/rvv-1.0-upstream-v7
You can change the cpu argument: vext_spec to v1.0 (i.e. vext_spec=v1.0)
to run with RVV v1.0 instructions.
Note: This patchset depends on another patchset listed in Based-on
section below so it might not able to be built unless the patchset
is applied.
Changelog:
v7
* remove hardcoded GDB vector registers list.
* add vsetivli instruction.
* add vle1.v and vse1.v instructions.
v6
* add vector floating-point reciprocal estimate instruction.
* add vector floating-point reciprocal square-root estimate instruction.
* update check rules for segment register groups, each segment register
group has to follow overlap rules.
* update viota.m instruction check rules.
v5
* refactor RVV v1.0 check functions.
(Thanks to Richard Henderson's bitwise tricks.)
* relax RV_VLEN_MAX to 1024-bits.
* implement vstart CSR's behaviors.
* trigger illegal instruction exception if frm is not valid for
vector floating-point instructions.
* rebase on riscv-to-apply.next.
v4
* remove explicit float flmul variable in DisasContext.
* replace floating-point calculations with shift operations to
improve performance.
* relax RV_VLEN_MAX to 512-bits.
v3
* apply nan-box helpers from Richard Henderson.
* remove fp16 api changes as they are sent independently in another
pathcset by Chih-Min Chao.
* remove all tail elements clear functions as tail elements can
retain unchanged for either VTA set to undisturbed or agnostic.
* add fp16 nan-box check generator function.
* add floating-point rounding mode enum.
* replace flmul arithmetic with shifts to avoid floating-point
conversions.
* add Zvqmac extension.
* replace gdbstub vector register xml files with dynamic generator.
* bumped to RVV v1.0.
* RVV v1.0 related changes:
* add vl<nf>re<eew>.v and vs<nf>r.v vector whole register
load/store instructions
* add vrgatherei16 instruction.
* rearranged bits in vtype to make vlmul bits into a contiguous
field.
v2
* drop v0.7.1 support.
* replace invisible return check macros with functions.
* move mark_vs_dirty() to translators.
* add SSTATUS_VS flag for s-mode.
* nan-box scalar fp register for floating-point operations.
* add gdbstub files for vector registers to allow system-mode
debugging with GDB.
Based-on: <1596102747-20226-1-git-send-email-chihmin.chao@sifive.com/>
Frank Chang (70):
target/riscv: drop vector 0.7.1 and add 1.0 support
target/riscv: Use FIELD_EX32() to extract wd field
target/riscv: rvv-1.0: introduce writable misa.v field
target/riscv: rvv-1.0: add translation-time vector context status
target/riscv: rvv-1.0: remove rvv related codes from fcsr registers
target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr
registers
target/riscv: rvv-1.0: remove MLEN calculations
target/riscv: rvv-1.0: add fractional LMUL
target/riscv: rvv-1.0: add VMA and VTA
target/riscv: rvv-1.0: update check functions
target/riscv: introduce more imm value modes in translator functions
target/riscv: rvv:1.0: add translation-time nan-box helper function
target/riscv: rvv-1.0: configure instructions
target/riscv: rvv-1.0: stride load and store instructions
target/riscv: rvv-1.0: index load and store instructions
target/riscv: rvv-1.0: fix address index overflow bug of indexed
load/store insns
target/riscv: rvv-1.0: fault-only-first unit stride load
target/riscv: rvv-1.0: amo operations
target/riscv: rvv-1.0: load/store whole register instructions
target/riscv: rvv-1.0: update vext_max_elems() for load/store insns
target/riscv: rvv-1.0: take fractional LMUL into vector max elements
calculation
target/riscv: rvv-1.0: floating-point square-root instruction
target/riscv: rvv-1.0: floating-point classify instructions
target/riscv: rvv-1.0: mask population count instruction
target/riscv: rvv-1.0: find-first-set mask bit instruction
target/riscv: rvv-1.0: set-X-first mask bit instructions
target/riscv: rvv-1.0: iota instruction
target/riscv: rvv-1.0: element index instruction
target/riscv: rvv-1.0: allow load element with sign-extended
target/riscv: rvv-1.0: register gather instructions
target/riscv: rvv-1.0: integer scalar move instructions
target/riscv: rvv-1.0: floating-point move instruction
target/riscv: rvv-1.0: floating-point scalar move instructions
target/riscv: rvv-1.0: whole register move instructions
target/riscv: rvv-1.0: integer extension instructions
target/riscv: rvv-1.0: single-width averaging add and subtract
instructions
target/riscv: rvv-1.0: single-width bit shift instructions
target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow
target/riscv: rvv-1.0: narrowing integer right shift instructions
target/riscv: rvv-1.0: widening integer multiply-add instructions
target/riscv: rvv-1.0: single-width saturating add and subtract
instructions
target/riscv: rvv-1.0: integer comparison instructions
target/riscv: rvv-1.0: floating-point compare instructions
target/riscv: rvv-1.0: mask-register logical instructions
target/riscv: rvv-1.0: slide instructions
target/riscv: rvv-1.0: floating-point slide instructions
target/riscv: rvv-1.0: narrowing fixed-point clip instructions
target/riscv: rvv-1.0: single-width floating-point reduction
target/riscv: rvv-1.0: widening floating-point reduction instructions
target/riscv: rvv-1.0: single-width scaling shift instructions
target/riscv: rvv-1.0: remove widening saturating scaled multiply-add
target/riscv: rvv-1.0: remove vmford.vv and vmford.vf
target/riscv: rvv-1.0: remove integer extract instruction
target/riscv: rvv-1.0: floating-point min/max instructions
target/riscv: introduce floating-point rounding mode enum
target/riscv: rvv-1.0: floating-point/integer type-convert
instructions
target/riscv: rvv-1.0: widening floating-point/integer type-convert
target/riscv: add "set round to odd" rounding mode helper function
target/riscv: rvv-1.0: narrowing floating-point/integer type-convert
target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
target/riscv: rvv-1.0: implement vstart CSR
target/riscv: rvv-1.0: trigger illegal instruction exception if frm is
not valid
target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs
target/riscv: rvv-1.0: floating-point reciprocal square-root estimate
instruction
target/riscv: rvv-1.0: floating-point reciprocal estimate instruction
target/riscv: set mstatus.SD bit when writing fp CSRs
target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11
target/riscv: rvv-1.0: add vsetivli instruction
target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()
target/riscv: rvv-1.0: add vector unit-stride mask load/store insns
Greentime Hu (1):
target/riscv: rvv-1.0: add vlenb register
Hsiangkai Wang (1):
target/riscv: gdb: support vector registers for rv64 & rv32
LIU Zhiwei (3):
target/riscv: rvv-1.0: add mstatus VS field
target/riscv: rvv-1.0: add sstatus VS field
target/riscv: rvv-1.0: add vcsr register
target/riscv/cpu.c | 12 +-
target/riscv/cpu.h | 75 +-
target/riscv/cpu_bits.h | 10 +
target/riscv/cpu_helper.c | 15 +-
target/riscv/csr.c | 85 +-
target/riscv/fpu_helper.c | 17 +-
target/riscv/gdbstub.c | 184 ++
target/riscv/helper.h | 505 ++-
target/riscv/insn32-64.decode | 18 +-
target/riscv/insn32.decode | 300 +-
target/riscv/insn_trans/trans_rvv.c.inc | 2529 ++++++++++-----
target/riscv/internals.h | 24 +-
target/riscv/translate.c | 72 +-
target/riscv/vector_helper.c | 3729 ++++++++++++-----------
14 files changed, 4594 insertions(+), 2981 deletions(-)
--
2.17.1
^ permalink raw reply [flat|nested] 76+ messages in thread
* [PATCH v7 01/75] target/riscv: drop vector 0.7.1 and add 1.0 support
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
@ 2021-02-26 3:17 ` frank.chang
2021-02-26 3:17 ` [PATCH v7 02/75] target/riscv: Use FIELD_EX32() to extract wd field frank.chang
` (73 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:17 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Alistair Francis, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 10 +++++-----
target/riscv/cpu.h | 2 +-
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 16f1a342388..d95165b3acb 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -379,7 +379,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
CPURISCVState *env = &cpu->env;
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
int priv_version = PRIV_VERSION_1_11_0;
- int vext_version = VEXT_VERSION_0_07_1;
+ int vext_version = VEXT_VERSION_1_00_0;
target_ulong target_misa = env->misa;
Error *local_err = NULL;
@@ -497,8 +497,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
return;
}
if (cpu->cfg.vext_spec) {
- if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) {
- vext_version = VEXT_VERSION_0_07_1;
+ if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) {
+ vext_version = VEXT_VERSION_1_00_0;
} else {
error_setg(errp,
"Unsupported vector spec version '%s'",
@@ -506,8 +506,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
return;
}
} else {
- qemu_log("vector verison is not specified, "
- "use the default value v0.7.1\n");
+ qemu_log("vector version is not specified, "
+ "use the default value v1.0\n");
}
set_vext_version(env, vext_version);
}
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 116b16b9362..9d911f81093 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -86,7 +86,7 @@ enum {
#define PRIV_VERSION_1_10_0 0x00011000
#define PRIV_VERSION_1_11_0 0x00011100
-#define VEXT_VERSION_0_07_1 0x00000701
+#define VEXT_VERSION_1_00_0 0x00010000
enum {
TRANSLATE_SUCCESS,
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 02/75] target/riscv: Use FIELD_EX32() to extract wd field
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
2021-02-26 3:17 ` [PATCH v7 01/75] target/riscv: drop vector 0.7.1 and add 1.0 support frank.chang
@ 2021-02-26 3:17 ` frank.chang
2021-02-26 3:17 ` [PATCH v7 03/75] target/riscv: rvv-1.0: add mstatus VS field frank.chang
` (72 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:17 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Alistair Francis, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/vector_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index a156573d281..bc3f212ceac 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -98,7 +98,7 @@ static inline uint32_t vext_lmul(uint32_t desc)
static uint32_t vext_wd(uint32_t desc)
{
- return (simd_data(desc) >> 11) & 0x1;
+ return FIELD_EX32(simd_data(desc), VDATA, WD);
}
/*
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 03/75] target/riscv: rvv-1.0: add mstatus VS field
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
2021-02-26 3:17 ` [PATCH v7 01/75] target/riscv: drop vector 0.7.1 and add 1.0 support frank.chang
2021-02-26 3:17 ` [PATCH v7 02/75] target/riscv: Use FIELD_EX32() to extract wd field frank.chang
@ 2021-02-26 3:17 ` frank.chang
2021-02-26 3:17 ` [PATCH v7 04/75] target/riscv: rvv-1.0: add sstatus " frank.chang
` (71 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:17 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 7 +++++++
target/riscv/cpu_bits.h | 1 +
target/riscv/cpu_helper.c | 15 ++++++++++++++-
target/riscv/csr.c | 25 ++++++++++++++++++++++++-
4 files changed, 46 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 9d911f81093..2c1e6c46a2d 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -327,6 +327,7 @@ int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
bool riscv_cpu_fp_enabled(CPURISCVState *env);
+bool riscv_cpu_vector_enabled(CPURISCVState *env);
bool riscv_cpu_virt_enabled(CPURISCVState *env);
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env);
@@ -373,6 +374,7 @@ void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
#define TB_FLAGS_PRIV_MMU_MASK 3
#define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2)
#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
+#define TB_FLAGS_MSTATUS_VS MSTATUS_VS
typedef CPURISCVState CPUArchState;
typedef RISCVCPU ArchCPU;
@@ -428,6 +430,7 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
#ifdef CONFIG_USER_ONLY
flags |= TB_FLAGS_MSTATUS_FS;
+ flags |= TB_FLAGS_MSTATUS_VS;
#else
flags |= cpu_mmu_index(env, 0);
if (riscv_cpu_fp_enabled(env)) {
@@ -442,6 +445,10 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
}
}
+
+ if (riscv_cpu_vector_enabled(env)) {
+ flags |= env->mstatus & MSTATUS_VS;
+ }
#endif
*pflags = flags;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 4196ef8b692..ba4c1c7076f 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -370,6 +370,7 @@
#define MSTATUS_SPIE 0x00000020
#define MSTATUS_MPIE 0x00000080
#define MSTATUS_SPP 0x00000100
+#define MSTATUS_VS 0x00000600
#define MSTATUS_MPP 0x00001800
#define MSTATUS_FS 0x00006000
#define MSTATUS_XS 0x00018000
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 2f43939fb6d..b07e10d472f 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -109,11 +109,24 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env)
return false;
}
+/* Return true is vector support is currently enabled */
+bool riscv_cpu_vector_enabled(CPURISCVState *env)
+{
+ if (env->mstatus & MSTATUS_VS) {
+ if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_VS)) {
+ return false;
+ }
+ return true;
+ }
+
+ return false;
+}
+
void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
{
uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS |
MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE |
- MSTATUS64_UXL;
+ MSTATUS64_UXL | MSTATUS_VS;
bool current_virt = riscv_cpu_virt_enabled(env);
g_assert(riscv_has_ext(env, RVH));
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d2ae73e4a08..778d5b85e92 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -260,6 +260,7 @@ static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
return -RISCV_EXCP_ILLEGAL_INST;
}
env->mstatus |= MSTATUS_FS;
+ env->mstatus |= MSTATUS_VS;
#endif
env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
if (vs(env, csrno) >= 0) {
@@ -290,6 +291,13 @@ static int read_vxrm(CPURISCVState *env, int csrno, target_ulong *val)
static int write_vxrm(CPURISCVState *env, int csrno, target_ulong val)
{
+#if !defined(CONFIG_USER_ONLY)
+ if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ env->mstatus |= MSTATUS_VS;
+#endif
+
env->vxrm = val;
return 0;
}
@@ -302,6 +310,13 @@ static int read_vxsat(CPURISCVState *env, int csrno, target_ulong *val)
static int write_vxsat(CPURISCVState *env, int csrno, target_ulong val)
{
+#if !defined(CONFIG_USER_ONLY)
+ if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ env->mstatus |= MSTATUS_VS;
+#endif
+
env->vxsat = val;
return 0;
}
@@ -314,6 +329,13 @@ static int read_vstart(CPURISCVState *env, int csrno, target_ulong *val)
static int write_vstart(CPURISCVState *env, int csrno, target_ulong val)
{
+#if !defined(CONFIG_USER_ONLY)
+ if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ env->mstatus |= MSTATUS_VS;
+#endif
+
env->vstart = val;
return 0;
}
@@ -477,7 +499,7 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
- MSTATUS_TW;
+ MSTATUS_TW | MSTATUS_VS;
if (!riscv_cpu_is_32bit(env)) {
/*
@@ -490,6 +512,7 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
mstatus = (mstatus & ~mask) | (val & mask);
dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
+ ((mstatus & MSTATUS_VS) == MSTATUS_VS) |
((mstatus & MSTATUS_XS) == MSTATUS_XS);
mstatus = set_field(mstatus, MSTATUS_SD, dirty);
env->mstatus = mstatus;
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 04/75] target/riscv: rvv-1.0: add sstatus VS field
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (2 preceding siblings ...)
2021-02-26 3:17 ` [PATCH v7 03/75] target/riscv: rvv-1.0: add mstatus VS field frank.chang
@ 2021-02-26 3:17 ` frank.chang
2021-02-26 3:17 ` [PATCH v7 05/75] target/riscv: rvv-1.0: introduce writable misa.v field frank.chang
` (70 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:17 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index ba4c1c7076f..73e88c2a7b1 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -414,6 +414,7 @@
#define SSTATUS_UPIE 0x00000010
#define SSTATUS_SPIE 0x00000020
#define SSTATUS_SPP 0x00000100
+#define SSTATUS_VS 0x00000600
#define SSTATUS_FS 0x00006000
#define SSTATUS_XS 0x00018000
#define SSTATUS_PUM 0x00040000 /* until: priv-1.9.1 */
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 778d5b85e92..098de1abacb 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -440,7 +440,7 @@ static const target_ulong delegable_excps =
(1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT));
static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
- SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
+ SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD | SSTATUS_VS;
static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
static const target_ulong vsip_writable_mask = MIP_VSSIP;
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 05/75] target/riscv: rvv-1.0: introduce writable misa.v field
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (3 preceding siblings ...)
2021-02-26 3:17 ` [PATCH v7 04/75] target/riscv: rvv-1.0: add sstatus " frank.chang
@ 2021-02-26 3:17 ` frank.chang
2021-02-26 3:17 ` [PATCH v7 06/75] target/riscv: rvv-1.0: add translation-time vector context status frank.chang
` (69 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:17 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Alistair Francis, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
Implementations may have a writable misa.v field. Analogous to the way
in which the floating-point unit is handled, the mstatus.vs field may
exist even if misa.v is clear.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 098de1abacb..89867a93643 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -571,7 +571,7 @@ static int write_misa(CPURISCVState *env, int csrno, target_ulong val)
val &= env->misa_mask;
/* Mask extensions that are not supported by QEMU */
- val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+ val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV);
/* 'D' depends on 'F', so clear 'D' if 'F' is not present */
if ((val & RVD) && !(val & RVF)) {
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 06/75] target/riscv: rvv-1.0: add translation-time vector context status
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (4 preceding siblings ...)
2021-02-26 3:17 ` [PATCH v7 05/75] target/riscv: rvv-1.0: introduce writable misa.v field frank.chang
@ 2021-02-26 3:17 ` frank.chang
2021-02-26 3:17 ` [PATCH v7 07/75] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers frank.chang
` (68 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:17 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 69 ++++++++++++++++++++-----
target/riscv/translate.c | 33 ++++++++++++
2 files changed, 90 insertions(+), 12 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 887c6b88831..56ce39e769a 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -41,6 +41,7 @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
gen_get_gpr(s2, a->rs2);
gen_helper_vsetvl(dst, cpu_env, s1, s2);
gen_set_gpr(a->rd, dst);
+ mark_vs_dirty(ctx);
tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
lookup_and_goto_ptr(ctx);
ctx->base.is_jmp = DISAS_NORETURN;
@@ -72,6 +73,7 @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
}
gen_helper_vsetvl(dst, cpu_env, s1, s2);
gen_set_gpr(a->rd, dst);
+ mark_vs_dirty(ctx);
gen_goto_tb(ctx, 0, ctx->pc_succ_insn);
ctx->base.is_jmp = DISAS_NORETURN;
@@ -163,7 +165,8 @@ typedef void gen_helper_ldst_us(TCGv_ptr, TCGv_ptr, TCGv,
TCGv_env, TCGv_i32);
static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
- gen_helper_ldst_us *fn, DisasContext *s)
+ gen_helper_ldst_us *fn, DisasContext *s,
+ bool is_store)
{
TCGv_ptr dest, mask;
TCGv base;
@@ -195,6 +198,9 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
tcg_temp_free_ptr(mask);
tcg_temp_free(base);
tcg_temp_free_i32(desc);
+ if (!is_store) {
+ mark_vs_dirty(s);
+ }
gen_set_label(over);
return true;
}
@@ -245,7 +251,7 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
- return ldst_us_trans(a->rd, a->rs1, data, fn, s);
+ return ldst_us_trans(a->rd, a->rs1, data, fn, s, false);
}
static bool ld_us_check(DisasContext *s, arg_r2nfvm* a)
@@ -298,7 +304,7 @@ static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
- return ldst_us_trans(a->rd, a->rs1, data, fn, s);
+ return ldst_us_trans(a->rd, a->rs1, data, fn, s, true);
}
static bool st_us_check(DisasContext *s, arg_r2nfvm* a)
@@ -321,7 +327,7 @@ typedef void gen_helper_ldst_stride(TCGv_ptr, TCGv_ptr, TCGv,
static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
uint32_t data, gen_helper_ldst_stride *fn,
- DisasContext *s)
+ DisasContext *s, bool is_store)
{
TCGv_ptr dest, mask;
TCGv base, stride;
@@ -348,6 +354,9 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
tcg_temp_free(base);
tcg_temp_free(stride);
tcg_temp_free_i32(desc);
+ if (!is_store) {
+ mark_vs_dirty(s);
+ }
gen_set_label(over);
return true;
}
@@ -382,7 +391,7 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
- return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
+ return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
}
static bool ld_stride_check(DisasContext *s, arg_rnfvm* a)
@@ -426,7 +435,7 @@ static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
return false;
}
- return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
+ return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, true);
}
static bool st_stride_check(DisasContext *s, arg_rnfvm* a)
@@ -449,7 +458,7 @@ typedef void gen_helper_ldst_index(TCGv_ptr, TCGv_ptr, TCGv,
static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
uint32_t data, gen_helper_ldst_index *fn,
- DisasContext *s)
+ DisasContext *s, bool is_store)
{
TCGv_ptr dest, mask, index;
TCGv base;
@@ -476,6 +485,9 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
tcg_temp_free_ptr(index);
tcg_temp_free(base);
tcg_temp_free_i32(desc);
+ if (!is_store) {
+ mark_vs_dirty(s);
+ }
gen_set_label(over);
return true;
}
@@ -510,7 +522,7 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
- return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
+ return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
}
/*
@@ -562,7 +574,7 @@ static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
- return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
+ return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, true);
}
static bool st_index_check(DisasContext *s, arg_rnfvm* a)
@@ -606,6 +618,7 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
tcg_temp_free_ptr(mask);
tcg_temp_free(base);
tcg_temp_free_i32(desc);
+ mark_vs_dirty(s);
gen_set_label(over);
return true;
}
@@ -685,6 +698,7 @@ static bool amo_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
tcg_temp_free_ptr(index);
tcg_temp_free(base);
tcg_temp_free_i32(desc);
+ mark_vs_dirty(s);
gen_set_label(over);
return true;
}
@@ -832,6 +846,7 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
cpu_env, 0, s->vlen / 8, data, fn);
}
+ mark_vs_dirty(s);
gen_set_label(over);
return true;
}
@@ -886,6 +901,7 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
tcg_temp_free_ptr(src2);
tcg_temp_free(src1);
tcg_temp_free_i32(desc);
+ mark_vs_dirty(s);
gen_set_label(over);
return true;
}
@@ -920,6 +936,7 @@ do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn,
tcg_temp_free_i64(src1);
tcg_temp_free(tmp);
+ mark_vs_dirty(s);
return true;
}
return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
@@ -1033,6 +1050,7 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
tcg_temp_free_ptr(src2);
tcg_temp_free(src1);
tcg_temp_free_i32(desc);
+ mark_vs_dirty(s);
gen_set_label(over);
return true;
}
@@ -1056,10 +1074,10 @@ do_opivi_gvec(DisasContext *s, arg_rmrr *a, GVecGen2iFn *gvec_fn,
gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
sextract64(a->rs1, 0, 5), MAXSZ(s), MAXSZ(s));
}
- } else {
- return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, zx);
+ mark_vs_dirty(s);
+ return true;
}
- return true;
+ return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, zx);
}
/* OPIVI with GVEC IR */
@@ -1120,6 +1138,7 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
vreg_ofs(s, a->rs2),
cpu_env, 0, s->vlen / 8,
data, fn);
+ mark_vs_dirty(s);
gen_set_label(over);
return true;
}
@@ -1207,6 +1226,7 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
vreg_ofs(s, a->rs1),
vreg_ofs(s, a->rs2),
cpu_env, 0, s->vlen / 8, data, fn);
+ mark_vs_dirty(s);
gen_set_label(over);
return true;
}
@@ -1285,6 +1305,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
s->vlen / 8, data, fns[s->sew]); \
+ mark_vs_dirty(s); \
gen_set_label(over); \
return true; \
} \
@@ -1416,6 +1437,7 @@ do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVecGen2sFn32 *gvec_fn,
tcg_temp_free_i32(src1);
tcg_temp_free(tmp);
+ mark_vs_dirty(s);
return true;
}
return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
@@ -1474,6 +1496,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
s->vlen / 8, data, fns[s->sew]); \
+ mark_vs_dirty(s); \
gen_set_label(over); \
return true; \
} \
@@ -1657,6 +1680,7 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
gen_set_label(over);
}
+ mark_vs_dirty(s);
return true;
}
return false;
@@ -1699,6 +1723,7 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
}
tcg_temp_free(s1);
+ mark_vs_dirty(s);
gen_set_label(over);
return true;
}
@@ -1714,6 +1739,7 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
if (s->vl_eq_vlmax) {
tcg_gen_gvec_dup_imm(s->sew, vreg_ofs(s, a->rd),
MAXSZ(s), MAXSZ(s), simm);
+ mark_vs_dirty(s);
} else {
TCGv_i32 desc;
TCGv_i64 s1;
@@ -1735,6 +1761,7 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
tcg_temp_free_ptr(dest);
tcg_temp_free_i32(desc);
tcg_temp_free_i64(s1);
+ mark_vs_dirty(s);
gen_set_label(over);
}
return true;
@@ -1839,6 +1866,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
s->vlen / 8, data, fns[s->sew - 1]); \
+ mark_vs_dirty(s); \
gen_set_label(over); \
return true; \
} \
@@ -1874,6 +1902,7 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
tcg_temp_free_ptr(mask);
tcg_temp_free_ptr(src2);
tcg_temp_free_i32(desc);
+ mark_vs_dirty(s);
gen_set_label(over);
return true;
}
@@ -1951,6 +1980,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
s->vlen / 8, data, fns[s->sew - 1]); \
+ mark_vs_dirty(s); \
gen_set_label(over); \
return true; \
} \
@@ -2025,6 +2055,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
s->vlen / 8, data, fns[s->sew - 1]); \
+ mark_vs_dirty(s); \
gen_set_label(over); \
return true; \
} \
@@ -2139,6 +2170,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
s->vlen / 8, data, fns[s->sew - 1]); \
+ mark_vs_dirty(s); \
gen_set_label(over); \
return true; \
} \
@@ -2211,6 +2243,7 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
if (s->vl_eq_vlmax) {
tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
MAXSZ(s), MAXSZ(s), cpu_fpr[a->rs1]);
+ mark_vs_dirty(s);
} else {
TCGv_ptr dest;
TCGv_i32 desc;
@@ -2230,6 +2263,7 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
tcg_temp_free_ptr(dest);
tcg_temp_free_i32(desc);
+ mark_vs_dirty(s);
gen_set_label(over);
}
return true;
@@ -2279,6 +2313,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
s->vlen / 8, data, fns[s->sew - 1]); \
+ mark_vs_dirty(s); \
gen_set_label(over); \
return true; \
} \
@@ -2327,6 +2362,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
s->vlen / 8, data, fns[s->sew - 1]); \
+ mark_vs_dirty(s); \
gen_set_label(over); \
return true; \
} \
@@ -2389,6 +2425,7 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
s->vlen / 8, data, fn); \
+ mark_vs_dirty(s); \
gen_set_label(over); \
return true; \
} \
@@ -2486,6 +2523,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \
vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \
cpu_env, 0, s->vlen / 8, data, fn); \
+ mark_vs_dirty(s); \
gen_set_label(over); \
return true; \
} \
@@ -2517,6 +2555,7 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs2), cpu_env, 0,
s->vlen / 8, data, fns[s->sew]);
+ mark_vs_dirty(s);
gen_set_label(over);
return true;
}
@@ -2542,6 +2581,7 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
};
tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
+ mark_vs_dirty(s);
gen_set_label(over);
return true;
}
@@ -2717,6 +2757,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]);
vec_element_storei(s, a->rd, 0, t1);
tcg_temp_free_i64(t1);
+ mark_vs_dirty(s);
done:
gen_set_label(over);
return true;
@@ -2767,6 +2808,7 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
}
vec_element_storei(s, a->rd, 0, t1);
tcg_temp_free_i64(t1);
+ mark_vs_dirty(s);
gen_set_label(over);
return true;
}
@@ -2833,6 +2875,7 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a)
tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
MAXSZ(s), MAXSZ(s), dest);
tcg_temp_free_i64(dest);
+ mark_vs_dirty(s);
} else {
static gen_helper_opivx * const fns[4] = {
gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h,
@@ -2859,6 +2902,7 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a)
endian_ofs(s, a->rs2, a->rs1),
MAXSZ(s), MAXSZ(s));
}
+ mark_vs_dirty(s);
} else {
static gen_helper_opivx * const fns[4] = {
gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h,
@@ -2895,6 +2939,7 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
+ mark_vs_dirty(s);
gen_set_label(over);
return true;
}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 9b518cdff46..fdb0a83a610 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -47,6 +47,7 @@ typedef struct DisasContext {
bool virt_enabled;
uint32_t opcode;
uint32_t mstatus_fs;
+ uint32_t mstatus_vs;
uint32_t misa;
uint32_t mem_idx;
/* Remember the rounding mode encoded in the previous fp instruction,
@@ -447,6 +448,37 @@ static void mark_fs_dirty(DisasContext *ctx)
static inline void mark_fs_dirty(DisasContext *ctx) { }
#endif
+#ifndef CONFIG_USER_ONLY
+/* The states of mstatus_vs are:
+ * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
+ * We will have already diagnosed disabled state,
+ * and need to turn initial/clean into dirty.
+ */
+static void mark_vs_dirty(DisasContext *ctx)
+{
+ TCGv tmp;
+ if (ctx->mstatus_vs == MSTATUS_VS) {
+ return;
+ }
+ /* Remember the state change for the rest of the TB. */
+ ctx->mstatus_vs = MSTATUS_VS;
+
+ tmp = tcg_temp_new();
+ tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
+ tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS | MSTATUS_SD);
+ tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
+
+ if (ctx->virt_enabled) {
+ tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
+ tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS | MSTATUS_SD);
+ tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
+ }
+ tcg_temp_free(tmp);
+}
+#else
+static inline void mark_vs_dirty(DisasContext *ctx) { }
+#endif
+
#if !defined(TARGET_RISCV64)
static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
int rs1, target_long imm)
@@ -804,6 +836,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->pc_succ_insn = ctx->base.pc_first;
ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX);
ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS;
+ ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS;
ctx->priv_ver = env->priv_ver;
#if !defined(CONFIG_USER_ONLY)
if (riscv_has_ext(env, RVH)) {
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 07/75] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (5 preceding siblings ...)
2021-02-26 3:17 ` [PATCH v7 06/75] target/riscv: rvv-1.0: add translation-time vector context status frank.chang
@ 2021-02-26 3:17 ` frank.chang
2021-02-26 3:17 ` [PATCH v7 08/75] target/riscv: rvv-1.0: add vcsr register frank.chang
` (67 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:17 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Alistair Francis, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
* Remove VXRM and VXSAT fields from FCSR register as they are only
presented in VCSR register.
* Remove RVV loose check in fs() predicate function.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 13 -------------
1 file changed, 13 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 89867a93643..5152bb84261 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -38,10 +38,6 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
static int fs(CPURISCVState *env, int csrno)
{
#if !defined(CONFIG_USER_ONLY)
- /* loose check condition for fcsr in vector extension */
- if ((csrno == CSR_FCSR) && (env->misa & RVV)) {
- return 0;
- }
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
return -RISCV_EXCP_ILLEGAL_INST;
}
@@ -246,10 +242,6 @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
#endif
*val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
| (env->frm << FSR_RD_SHIFT);
- if (vs(env, csrno) >= 0) {
- *val |= (env->vxrm << FSR_VXRM_SHIFT)
- | (env->vxsat << FSR_VXSAT_SHIFT);
- }
return 0;
}
@@ -260,13 +252,8 @@ static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
return -RISCV_EXCP_ILLEGAL_INST;
}
env->mstatus |= MSTATUS_FS;
- env->mstatus |= MSTATUS_VS;
#endif
env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
- if (vs(env, csrno) >= 0) {
- env->vxrm = (val & FSR_VXRM) >> FSR_VXRM_SHIFT;
- env->vxsat = (val & FSR_VXSAT) >> FSR_VXSAT_SHIFT;
- }
riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
return 0;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 08/75] target/riscv: rvv-1.0: add vcsr register
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (6 preceding siblings ...)
2021-02-26 3:17 ` [PATCH v7 07/75] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers frank.chang
@ 2021-02-26 3:17 ` frank.chang
2021-02-26 3:17 ` [PATCH v7 09/75] target/riscv: rvv-1.0: add vlenb register frank.chang
` (66 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:17 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 7 +++++++
target/riscv/csr.c | 21 +++++++++++++++++++++
2 files changed, 28 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 73e88c2a7b1..03a26fa680c 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -60,9 +60,16 @@
#define CSR_VSTART 0x008
#define CSR_VXSAT 0x009
#define CSR_VXRM 0x00a
+#define CSR_VCSR 0x00f
#define CSR_VL 0xc20
#define CSR_VTYPE 0xc21
+/* VCSR fields */
+#define VCSR_VXSAT_SHIFT 0
+#define VCSR_VXSAT (0x1 << VCSR_VXSAT_SHIFT)
+#define VCSR_VXRM_SHIFT 1
+#define VCSR_VXRM (0x3 << VCSR_VXRM_SHIFT)
+
/* User Timers and Counters */
#define CSR_CYCLE 0xc00
#define CSR_TIME 0xc01
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 5152bb84261..f70b67cce3c 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -327,6 +327,26 @@ static int write_vstart(CPURISCVState *env, int csrno, target_ulong val)
return 0;
}
+static int read_vcsr(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_SHIFT);
+ return 0;
+}
+
+static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val)
+{
+#if !defined(CONFIG_USER_ONLY)
+ if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ env->mstatus |= MSTATUS_VS;
+#endif
+
+ env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT;
+ env->vxsat = (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT;
+ return 0;
+}
+
/* User Timers and Counters */
static int read_instret(CPURISCVState *env, int csrno, target_ulong *val)
{
@@ -1389,6 +1409,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart },
[CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat },
[CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm },
+ [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr },
[CSR_VL] = { "vl", vs, read_vl },
[CSR_VTYPE] = { "vtype", vs, read_vtype },
/* User Timers and Counters */
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 09/75] target/riscv: rvv-1.0: add vlenb register
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (7 preceding siblings ...)
2021-02-26 3:17 ` [PATCH v7 08/75] target/riscv: rvv-1.0: add vcsr register frank.chang
@ 2021-02-26 3:17 ` frank.chang
2021-02-26 3:17 ` [PATCH v7 10/75] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers frank.chang
` (65 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:17 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Alistair Francis, Greentime Hu, Palmer Dabbelt
From: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 7 +++++++
2 files changed, 8 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 03a26fa680c..1df818ec6a6 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -63,6 +63,7 @@
#define CSR_VCSR 0x00f
#define CSR_VL 0xc20
#define CSR_VTYPE 0xc21
+#define CSR_VLENB 0xc22
/* VCSR fields */
#define VCSR_VXSAT_SHIFT 0
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index f70b67cce3c..92cf2eedd40 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -264,6 +264,12 @@ static int read_vtype(CPURISCVState *env, int csrno, target_ulong *val)
return 0;
}
+static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env_archcpu(env)->cfg.vlen >> 3;
+ return 0;
+}
+
static int read_vl(CPURISCVState *env, int csrno, target_ulong *val)
{
*val = env->vl;
@@ -1412,6 +1418,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr },
[CSR_VL] = { "vl", vs, read_vl },
[CSR_VTYPE] = { "vtype", vs, read_vtype },
+ [CSR_VLENB] = { "vlenb", vs, read_vlenb },
/* User Timers and Counters */
[CSR_CYCLE] = { "cycle", ctr, read_instret },
[CSR_INSTRET] = { "instret", ctr, read_instret },
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 10/75] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (8 preceding siblings ...)
2021-02-26 3:17 ` [PATCH v7 09/75] target/riscv: rvv-1.0: add vlenb register frank.chang
@ 2021-02-26 3:17 ` frank.chang
2021-02-26 3:17 ` [PATCH v7 11/75] target/riscv: rvv-1.0: remove MLEN calculations frank.chang
` (64 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:17 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Alistair Francis, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
If VS field is off, accessing vector csr registers should raise an
illegal-instruction exception.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 92cf2eedd40..a6a535f7e33 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -48,6 +48,11 @@ static int fs(CPURISCVState *env, int csrno)
static int vs(CPURISCVState *env, int csrno)
{
if (env->misa & RVV) {
+#if !defined(CONFIG_USER_ONLY)
+ if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+#endif
return 0;
}
return -RISCV_EXCP_ILLEGAL_INST;
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 11/75] target/riscv: rvv-1.0: remove MLEN calculations
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (9 preceding siblings ...)
2021-02-26 3:17 ` [PATCH v7 10/75] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers frank.chang
@ 2021-02-26 3:17 ` frank.chang
2021-02-26 3:17 ` [PATCH v7 12/75] target/riscv: rvv-1.0: add fractional LMUL frank.chang
` (63 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:17 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
As in RVV 1.0 design, MLEN is hardcoded with value 1 (Section 4.5).
Thus, remove all MLEN related calculations.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 35 +---
target/riscv/internals.h | 9 +-
target/riscv/translate.c | 2 -
target/riscv/vector_helper.c | 250 ++++++++++--------------
4 files changed, 110 insertions(+), 186 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 56ce39e769a..46e18a62b59 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -247,7 +247,6 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
return false;
}
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
@@ -300,7 +299,6 @@ static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
return false;
}
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
@@ -387,7 +385,6 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
return false;
}
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
@@ -426,7 +423,6 @@ static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
gen_helper_vsse_v_w, gen_helper_vsse_v_d }
};
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
@@ -518,7 +514,6 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
return false;
}
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
@@ -570,7 +565,6 @@ static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
return false;
}
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
@@ -649,7 +643,6 @@ static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
return false;
}
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
@@ -760,7 +753,6 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
}
}
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, WD, a->wd);
@@ -839,7 +831,6 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
} else {
uint32_t data = 0;
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
@@ -885,7 +876,6 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
src1 = tcg_temp_new();
gen_get_gpr(src1, rs1);
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
@@ -1034,7 +1024,6 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
} else {
src1 = tcg_const_tl(sextract64(imm, 0, 5));
}
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
@@ -1130,7 +1119,6 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
@@ -1219,7 +1207,6 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
@@ -1298,7 +1285,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
TCGLabel *over = gen_new_label(); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
@@ -1489,7 +1475,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
TCGLabel *over = gen_new_label(); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
@@ -1859,7 +1844,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_set_rm(s, 7); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
@@ -1932,7 +1916,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_helper_##NAME##_d, \
}; \
gen_set_rm(s, 7); \
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
@@ -1973,7 +1956,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_set_rm(s, 7); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
@@ -2011,7 +1993,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
gen_set_rm(s, 7); \
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
@@ -2048,7 +2029,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_set_rm(s, 7); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
@@ -2084,7 +2064,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
gen_set_rm(s, 7); \
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
@@ -2164,7 +2143,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
gen_set_rm(s, 7); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
@@ -2307,7 +2285,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
gen_set_rm(s, 7); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
@@ -2356,7 +2333,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
gen_set_rm(s, 7); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
@@ -2419,7 +2395,6 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \
TCGLabel *over = gen_new_label(); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
@@ -2449,7 +2424,6 @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
TCGv dst;
TCGv_i32 desc;
uint32_t data = 0;
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
@@ -2481,7 +2455,6 @@ static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a)
TCGv dst;
TCGv_i32 desc;
uint32_t data = 0;
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
@@ -2517,7 +2490,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
TCGLabel *over = gen_new_label(); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \
@@ -2545,7 +2517,6 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
static gen_helper_gvec_3_ptr * const fns[4] = {
@@ -2572,7 +2543,6 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
static gen_helper_gvec_2_ptr * const fns[4] = {
@@ -2863,7 +2833,7 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a)
}
if (a->vm && s->vl_eq_vlmax) {
- int vlmax = s->vlen / s->mlen;
+ int vlmax = s->vlen;
TCGv_i64 dest = tcg_temp_new_i64();
if (a->rs1 == 0) {
@@ -2894,7 +2864,7 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a)
}
if (a->vm && s->vl_eq_vlmax) {
- if (a->rs1 >= s->vlen / s->mlen) {
+ if (a->rs1 >= s->vlen) {
tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd),
MAXSZ(s), MAXSZ(s), 0);
} else {
@@ -2934,7 +2904,6 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
- data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2),
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index b15ad394bb9..c3bbeea9a94 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -22,11 +22,10 @@
#include "hw/registerfields.h"
/* share data between vector helpers and decode code */
-FIELD(VDATA, MLEN, 0, 8)
-FIELD(VDATA, VM, 8, 1)
-FIELD(VDATA, LMUL, 9, 2)
-FIELD(VDATA, NF, 11, 4)
-FIELD(VDATA, WD, 11, 1)
+FIELD(VDATA, VM, 0, 1)
+FIELD(VDATA, LMUL, 1, 3)
+FIELD(VDATA, NF, 4, 4)
+FIELD(VDATA, WD, 4, 1)
/* float point classify helpers */
target_ulong fclass_h(uint64_t frs1);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index fdb0a83a610..6e1896188c0 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -63,7 +63,6 @@ typedef struct DisasContext {
uint8_t lmul;
uint8_t sew;
uint16_t vlen;
- uint16_t mlen;
bool vl_eq_vlmax;
CPUState *cs;
} DisasContext;
@@ -855,7 +854,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);
ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL);
- ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul);
ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
ctx->cs = cs;
}
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index bc3f212ceac..12301e943e6 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -81,11 +81,6 @@ static inline uint32_t vext_nf(uint32_t desc)
return FIELD_EX32(simd_data(desc), VDATA, NF);
}
-static inline uint32_t vext_mlen(uint32_t desc)
-{
- return FIELD_EX32(simd_data(desc), VDATA, MLEN);
-}
-
static inline uint32_t vext_vm(uint32_t desc)
{
return FIELD_EX32(simd_data(desc), VDATA, VM);
@@ -188,19 +183,24 @@ static void clearq(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot)
vext_clear(cur, cnt, tot);
}
-static inline void vext_set_elem_mask(void *v0, int mlen, int index,
+static inline void vext_set_elem_mask(void *v0, int index,
uint8_t value)
{
- int idx = (index * mlen) / 64;
- int pos = (index * mlen) % 64;
+ int idx = index / 64;
+ int pos = index % 64;
uint64_t old = ((uint64_t *)v0)[idx];
- ((uint64_t *)v0)[idx] = deposit64(old, pos, mlen, value);
+ ((uint64_t *)v0)[idx] = deposit64(old, pos, 1, value);
}
-static inline int vext_elem_mask(void *v0, int mlen, int index)
+/*
+ * Earlier designs (pre-0.9) had a varying number of bits
+ * per mask value (MLEN). In the 0.9 design, MLEN=1.
+ * (Section 4.5)
+ */
+static inline int vext_elem_mask(void *v0, int index)
{
- int idx = (index * mlen) / 64;
- int pos = (index * mlen) % 64;
+ int idx = index / 64;
+ int pos = index % 64;
return (((uint64_t *)v0)[idx] >> pos) & 1;
}
@@ -277,12 +277,11 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
{
uint32_t i, k;
uint32_t nf = vext_nf(desc);
- uint32_t mlen = vext_mlen(desc);
uint32_t vlmax = vext_maxsz(desc) / esz;
/* probe every access*/
for (i = 0; i < env->vl; i++) {
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
probe_pages(env, base + stride * i, nf * msz, ra, access_type);
@@ -290,7 +289,7 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
/* do real access */
for (i = 0; i < env->vl; i++) {
k = 0;
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
while (k < nf) {
@@ -506,12 +505,11 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
uint32_t i, k;
uint32_t nf = vext_nf(desc);
uint32_t vm = vext_vm(desc);
- uint32_t mlen = vext_mlen(desc);
uint32_t vlmax = vext_maxsz(desc) / esz;
/* probe every access*/
for (i = 0; i < env->vl; i++) {
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
probe_pages(env, get_index_addr(base, i, vs2), nf * msz, ra,
@@ -520,7 +518,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
/* load bytes from guest memory */
for (i = 0; i < env->vl; i++) {
k = 0;
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
while (k < nf) {
@@ -604,7 +602,6 @@ vext_ldff(void *vd, void *v0, target_ulong base,
{
void *host;
uint32_t i, k, vl = 0;
- uint32_t mlen = vext_mlen(desc);
uint32_t nf = vext_nf(desc);
uint32_t vm = vext_vm(desc);
uint32_t vlmax = vext_maxsz(desc) / esz;
@@ -612,7 +609,7 @@ vext_ldff(void *vd, void *v0, target_ulong base,
/* probe every access*/
for (i = 0; i < env->vl; i++) {
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
addr = base + nf * i * msz;
@@ -653,7 +650,7 @@ ProbeSuccess:
}
for (i = 0; i < env->vl; i++) {
k = 0;
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
while (k < nf) {
@@ -784,18 +781,17 @@ vext_amo_noatomic(void *vs3, void *v0, target_ulong base,
target_long addr;
uint32_t wd = vext_wd(desc);
uint32_t vm = vext_vm(desc);
- uint32_t mlen = vext_mlen(desc);
uint32_t vlmax = vext_maxsz(desc) / esz;
for (i = 0; i < env->vl; i++) {
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
probe_pages(env, get_index_addr(base, i, vs2), msz, ra, MMU_DATA_LOAD);
probe_pages(env, get_index_addr(base, i, vs2), msz, ra, MMU_DATA_STORE);
}
for (i = 0; i < env->vl; i++) {
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
addr = get_index_addr(base, i, vs2);
@@ -911,13 +907,12 @@ static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2,
opivv2_fn *fn, clear_fn *clearfn)
{
uint32_t vlmax = vext_maxsz(desc) / esz;
- uint32_t mlen = vext_mlen(desc);
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
uint32_t i;
for (i = 0; i < vl; i++) {
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
fn(vd, vs1, vs2, i);
@@ -976,13 +971,12 @@ static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2,
opivx2_fn fn, clear_fn *clearfn)
{
uint32_t vlmax = vext_maxsz(desc) / esz;
- uint32_t mlen = vext_mlen(desc);
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
uint32_t i;
for (i = 0; i < vl; i++) {
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
fn(vd, s1, vs2, i);
@@ -1172,7 +1166,6 @@ GEN_VEXT_VX(vwsub_wx_w, 4, 8, clearq)
void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
uint32_t vlmax = vext_maxsz(desc) / esz; \
@@ -1181,7 +1174,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
for (i = 0; i < vl; i++) { \
ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- uint8_t carry = vext_elem_mask(v0, mlen, i); \
+ uint8_t carry = vext_elem_mask(v0, i); \
\
*((ETYPE *)vd + H(i)) = DO_OP(s2, s1, carry); \
} \
@@ -1202,7 +1195,6 @@ GEN_VEXT_VADC_VVM(vsbc_vvm_d, uint64_t, H8, DO_VSBC, clearq)
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
uint32_t vlmax = vext_maxsz(desc) / esz; \
@@ -1210,7 +1202,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
\
for (i = 0; i < vl; i++) { \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- uint8_t carry = vext_elem_mask(v0, mlen, i); \
+ uint8_t carry = vext_elem_mask(v0, i); \
\
*((ETYPE *)vd + H(i)) = DO_OP(s2, (ETYPE)(target_long)s1, carry);\
} \
@@ -1235,7 +1227,6 @@ GEN_VEXT_VADC_VXM(vsbc_vxm_d, uint64_t, H8, DO_VSBC, clearq)
void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vl = env->vl; \
uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
uint32_t i; \
@@ -1243,12 +1234,12 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
for (i = 0; i < vl; i++) { \
ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- uint8_t carry = vext_elem_mask(v0, mlen, i); \
+ uint8_t carry = vext_elem_mask(v0, i); \
\
- vext_set_elem_mask(vd, mlen, i, DO_OP(s2, s1, carry));\
+ vext_set_elem_mask(vd, i, DO_OP(s2, s1, carry)); \
} \
for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, mlen, i, 0); \
+ vext_set_elem_mask(vd, i, 0); \
} \
}
@@ -1266,20 +1257,19 @@ GEN_VEXT_VMADC_VVM(vmsbc_vvm_d, uint64_t, H8, DO_MSBC)
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vl = env->vl; \
uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- uint8_t carry = vext_elem_mask(v0, mlen, i); \
+ uint8_t carry = vext_elem_mask(v0, i); \
\
- vext_set_elem_mask(vd, mlen, i, \
+ vext_set_elem_mask(vd, i, \
DO_OP(s2, (ETYPE)(target_long)s1, carry)); \
} \
for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, mlen, i, 0); \
+ vext_set_elem_mask(vd, i, 0); \
} \
}
@@ -1353,7 +1343,6 @@ GEN_VEXT_VX(vxor_vx_d, 8, 8, clearq)
void HELPER(NAME)(void *vd, void *v0, void *vs1, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(TS1); \
@@ -1361,7 +1350,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
TS1 s1 = *((TS1 *)vs1 + HS1(i)); \
@@ -1391,7 +1380,6 @@ GEN_VEXT_SHIFT_VV(vsra_vv_d, uint64_t, int64_t, H8, H8, DO_SRL, 0x3f, clearq)
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(TD); \
@@ -1399,7 +1387,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
@@ -1448,7 +1436,6 @@ GEN_VEXT_SHIFT_VX(vnsra_vx_w, int32_t, int64_t, H4, H8, DO_SRL, 0x3f, clearl)
void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
@@ -1457,13 +1444,13 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
for (i = 0; i < vl; i++) { \
ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
- vext_set_elem_mask(vd, mlen, i, DO_OP(s2, s1)); \
+ vext_set_elem_mask(vd, i, DO_OP(s2, s1)); \
} \
for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, mlen, i, 0); \
+ vext_set_elem_mask(vd, i, 0); \
} \
}
@@ -1501,7 +1488,6 @@ GEN_VEXT_CMP_VV(vmsle_vv_d, int64_t, H8, DO_MSLE)
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
@@ -1509,14 +1495,14 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
\
for (i = 0; i < vl; i++) { \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
- vext_set_elem_mask(vd, mlen, i, \
+ vext_set_elem_mask(vd, i, \
DO_OP(s2, (ETYPE)(target_long)s1)); \
} \
for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, mlen, i, 0); \
+ vext_set_elem_mask(vd, i, 0); \
} \
}
@@ -2078,14 +2064,13 @@ GEN_VEXT_VMV_VX(vmv_v_x_d, int64_t, H8, clearq)
void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
uint32_t vlmax = vext_maxsz(desc) / esz; \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
- ETYPE *vt = (!vext_elem_mask(v0, mlen, i) ? vs2 : vs1); \
+ ETYPE *vt = (!vext_elem_mask(v0, i) ? vs2 : vs1); \
*((ETYPE *)vd + H(i)) = *(vt + H(i)); \
} \
CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
@@ -2100,7 +2085,6 @@ GEN_VEXT_VMERGE_VV(vmerge_vvm_d, int64_t, H8, clearq)
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
uint32_t vlmax = vext_maxsz(desc) / esz; \
@@ -2108,7 +2092,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
\
for (i = 0; i < vl; i++) { \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- ETYPE d = (!vext_elem_mask(v0, mlen, i) ? s2 : \
+ ETYPE d = (!vext_elem_mask(v0, i) ? s2 : \
(ETYPE)(target_long)s1); \
*((ETYPE *)vd + H(i)) = d; \
} \
@@ -2146,11 +2130,11 @@ do_##NAME(void *vd, void *vs1, void *vs2, int i, \
static inline void
vext_vv_rm_1(void *vd, void *v0, void *vs1, void *vs2,
CPURISCVState *env,
- uint32_t vl, uint32_t vm, uint32_t mlen, int vxrm,
+ uint32_t vl, uint32_t vm, int vxrm,
opivv2_rm_fn *fn)
{
for (uint32_t i = 0; i < vl; i++) {
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
fn(vd, vs1, vs2, i, env, vxrm);
@@ -2164,26 +2148,25 @@ vext_vv_rm_2(void *vd, void *v0, void *vs1, void *vs2,
opivv2_rm_fn *fn, clear_fn *clearfn)
{
uint32_t vlmax = vext_maxsz(desc) / esz;
- uint32_t mlen = vext_mlen(desc);
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
switch (env->vxrm) {
case 0: /* rnu */
vext_vv_rm_1(vd, v0, vs1, vs2,
- env, vl, vm, mlen, 0, fn);
+ env, vl, vm, 0, fn);
break;
case 1: /* rne */
vext_vv_rm_1(vd, v0, vs1, vs2,
- env, vl, vm, mlen, 1, fn);
+ env, vl, vm, 1, fn);
break;
case 2: /* rdn */
vext_vv_rm_1(vd, v0, vs1, vs2,
- env, vl, vm, mlen, 2, fn);
+ env, vl, vm, 2, fn);
break;
default: /* rod */
vext_vv_rm_1(vd, v0, vs1, vs2,
- env, vl, vm, mlen, 3, fn);
+ env, vl, vm, 3, fn);
break;
}
@@ -2266,11 +2249,11 @@ do_##NAME(void *vd, target_long s1, void *vs2, int i, \
static inline void
vext_vx_rm_1(void *vd, void *v0, target_long s1, void *vs2,
CPURISCVState *env,
- uint32_t vl, uint32_t vm, uint32_t mlen, int vxrm,
+ uint32_t vl, uint32_t vm, int vxrm,
opivx2_rm_fn *fn)
{
for (uint32_t i = 0; i < vl; i++) {
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
fn(vd, s1, vs2, i, env, vxrm);
@@ -2284,26 +2267,25 @@ vext_vx_rm_2(void *vd, void *v0, target_long s1, void *vs2,
opivx2_rm_fn *fn, clear_fn *clearfn)
{
uint32_t vlmax = vext_maxsz(desc) / esz;
- uint32_t mlen = vext_mlen(desc);
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
switch (env->vxrm) {
case 0: /* rnu */
vext_vx_rm_1(vd, v0, s1, vs2,
- env, vl, vm, mlen, 0, fn);
+ env, vl, vm, 0, fn);
break;
case 1: /* rne */
vext_vx_rm_1(vd, v0, s1, vs2,
- env, vl, vm, mlen, 1, fn);
+ env, vl, vm, 1, fn);
break;
case 2: /* rdn */
vext_vx_rm_1(vd, v0, s1, vs2,
- env, vl, vm, mlen, 2, fn);
+ env, vl, vm, 2, fn);
break;
default: /* rod */
vext_vx_rm_1(vd, v0, s1, vs2,
- env, vl, vm, mlen, 3, fn);
+ env, vl, vm, 3, fn);
break;
}
@@ -3188,13 +3170,12 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
uint32_t desc) \
{ \
uint32_t vlmax = vext_maxsz(desc) / ESZ; \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
do_##NAME(vd, vs1, vs2, i, env); \
@@ -3223,13 +3204,12 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, \
uint32_t desc) \
{ \
uint32_t vlmax = vext_maxsz(desc) / ESZ; \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
do_##NAME(vd, s1, vs2, i, env); \
@@ -3794,7 +3774,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
uint32_t vlmax = vext_maxsz(desc) / ESZ; \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
@@ -3803,7 +3782,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \
return; \
} \
for (i = 0; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
do_##NAME(vd, vs2, i, env); \
@@ -3935,7 +3914,6 @@ GEN_VEXT_VF(vfsgnjx_vf_d, 8, 8, clearq)
void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
@@ -3944,14 +3922,14 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
for (i = 0; i < vl; i++) { \
ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
- vext_set_elem_mask(vd, mlen, i, \
+ vext_set_elem_mask(vd, i, \
DO_OP(s2, s1, &env->fp_status)); \
} \
for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, mlen, i, 0); \
+ vext_set_elem_mask(vd, i, 0); \
} \
}
@@ -3963,7 +3941,6 @@ GEN_VEXT_CMP_VV_ENV(vmfeq_vv_d, uint64_t, H8, float64_eq_quiet)
void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
@@ -3971,14 +3948,14 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
\
for (i = 0; i < vl; i++) { \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
- vext_set_elem_mask(vd, mlen, i, \
+ vext_set_elem_mask(vd, i, \
DO_OP(s2, (ETYPE)s1, &env->fp_status)); \
} \
for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, mlen, i, 0); \
+ vext_set_elem_mask(vd, i, 0); \
} \
}
@@ -4092,13 +4069,12 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
uint32_t vlmax = vext_maxsz(desc) / ESZ; \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
do_##NAME(vd, vs2, i); \
@@ -4175,7 +4151,6 @@ GEN_VEXT_V(vfclass_v_d, 8, 8, clearq)
void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t esz = sizeof(ETYPE); \
@@ -4185,7 +4160,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
for (i = 0; i < vl; i++) { \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
*((ETYPE *)vd + H(i)) \
- = (!vm && !vext_elem_mask(v0, mlen, i) ? s2 : s1); \
+ = (!vm && !vext_elem_mask(v0, i) ? s2 : s1); \
} \
CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
}
@@ -4316,7 +4291,6 @@ GEN_VEXT_V_ENV(vfncvt_f_f_v_w, 4, 4, clearl)
void HELPER(NAME)(void *vd, void *v0, void *vs1, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
@@ -4325,7 +4299,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
\
for (i = 0; i < vl; i++) { \
TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
s1 = OP(s1, (TD)s2); \
@@ -4399,7 +4373,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
void *vs2, CPURISCVState *env, \
uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
@@ -4408,7 +4381,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
\
for (i = 0; i < vl; i++) { \
TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
s1 = OP(s1, (TD)s2, &env->fp_status); \
@@ -4437,7 +4410,6 @@ GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, float64_minnum, clearq)
void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1,
void *vs2, CPURISCVState *env, uint32_t desc)
{
- uint32_t mlen = vext_mlen(desc);
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
uint32_t i;
@@ -4446,7 +4418,7 @@ void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1,
for (i = 0; i < vl; i++) {
uint16_t s2 = *((uint16_t *)vs2 + H2(i));
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
s1 = float32_add(s1, float16_to_float32(s2, true, &env->fp_status),
@@ -4459,7 +4431,6 @@ void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1,
void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1,
void *vs2, CPURISCVState *env, uint32_t desc)
{
- uint32_t mlen = vext_mlen(desc);
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
uint32_t i;
@@ -4468,7 +4439,7 @@ void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1,
for (i = 0; i < vl; i++) {
uint32_t s2 = *((uint32_t *)vs2 + H4(i));
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
s1 = float64_add(s1, float32_to_float64(s2, &env->fp_status),
@@ -4487,19 +4458,18 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
void *vs2, CPURISCVState *env, \
uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
+ uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vl = env->vl; \
uint32_t i; \
int a, b; \
\
for (i = 0; i < vl; i++) { \
- a = vext_elem_mask(vs1, mlen, i); \
- b = vext_elem_mask(vs2, mlen, i); \
- vext_set_elem_mask(vd, mlen, i, OP(b, a)); \
+ a = vext_elem_mask(vs1, i); \
+ b = vext_elem_mask(vs2, i); \
+ vext_set_elem_mask(vd, i, OP(b, a)); \
} \
for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, mlen, i, 0); \
+ vext_set_elem_mask(vd, i, 0); \
} \
}
@@ -4523,14 +4493,13 @@ target_ulong HELPER(vmpopc_m)(void *v0, void *vs2, CPURISCVState *env,
uint32_t desc)
{
target_ulong cnt = 0;
- uint32_t mlen = vext_mlen(desc);
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
int i;
for (i = 0; i < vl; i++) {
- if (vm || vext_elem_mask(v0, mlen, i)) {
- if (vext_elem_mask(vs2, mlen, i)) {
+ if (vm || vext_elem_mask(v0, i)) {
+ if (vext_elem_mask(vs2, i)) {
cnt++;
}
}
@@ -4542,14 +4511,13 @@ target_ulong HELPER(vmpopc_m)(void *v0, void *vs2, CPURISCVState *env,
target_ulong HELPER(vmfirst_m)(void *v0, void *vs2, CPURISCVState *env,
uint32_t desc)
{
- uint32_t mlen = vext_mlen(desc);
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
int i;
for (i = 0; i < vl; i++) {
- if (vm || vext_elem_mask(v0, mlen, i)) {
- if (vext_elem_mask(vs2, mlen, i)) {
+ if (vm || vext_elem_mask(v0, i)) {
+ if (vext_elem_mask(vs2, i)) {
return i;
}
}
@@ -4566,39 +4534,38 @@ enum set_mask_type {
static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env,
uint32_t desc, enum set_mask_type type)
{
- uint32_t mlen = vext_mlen(desc);
- uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen;
+ uint32_t vlmax = env_archcpu(env)->cfg.vlen;
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
int i;
bool first_mask_bit = false;
for (i = 0; i < vl; i++) {
- if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
/* write a zero to all following active elements */
if (first_mask_bit) {
- vext_set_elem_mask(vd, mlen, i, 0);
+ vext_set_elem_mask(vd, i, 0);
continue;
}
- if (vext_elem_mask(vs2, mlen, i)) {
+ if (vext_elem_mask(vs2, i)) {
first_mask_bit = true;
if (type == BEFORE_FIRST) {
- vext_set_elem_mask(vd, mlen, i, 0);
+ vext_set_elem_mask(vd, i, 0);
} else {
- vext_set_elem_mask(vd, mlen, i, 1);
+ vext_set_elem_mask(vd, i, 1);
}
} else {
if (type == ONLY_FIRST) {
- vext_set_elem_mask(vd, mlen, i, 0);
+ vext_set_elem_mask(vd, i, 0);
} else {
- vext_set_elem_mask(vd, mlen, i, 1);
+ vext_set_elem_mask(vd, i, 1);
}
}
}
for (; i < vlmax; i++) {
- vext_set_elem_mask(vd, mlen, i, 0);
+ vext_set_elem_mask(vd, i, 0);
}
}
@@ -4625,19 +4592,18 @@ void HELPER(vmsof_m)(void *vd, void *v0, void *vs2, CPURISCVState *env,
void HELPER(NAME)(void *vd, void *v0, void *vs2, CPURISCVState *env, \
uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
+ uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t sum = 0; \
int i; \
\
for (i = 0; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
*((ETYPE *)vd + H(i)) = sum; \
- if (vext_elem_mask(vs2, mlen, i)) { \
+ if (vext_elem_mask(vs2, i)) { \
sum++; \
} \
} \
@@ -4653,14 +4619,13 @@ GEN_VEXT_VIOTA_M(viota_m_d, uint64_t, H8, clearq)
#define GEN_VEXT_VID_V(NAME, ETYPE, H, CLEAR_FN) \
void HELPER(NAME)(void *vd, void *v0, CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
+ uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
int i; \
\
for (i = 0; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
*((ETYPE *)vd + H(i)) = i; \
@@ -4682,14 +4647,13 @@ GEN_VEXT_VID_V(vid_v_d, uint64_t, H8, clearq)
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
+ uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
target_ulong offset = s1, i; \
\
for (i = offset; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
*((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - offset)); \
@@ -4707,15 +4671,14 @@ GEN_VEXT_VSLIDEUP_VX(vslideup_vx_d, uint64_t, H8, clearq)
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
+ uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
target_ulong offset = s1, i; \
\
for (i = 0; i < vl; ++i) { \
target_ulong j = i + offset; \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
*((ETYPE *)vd + H(i)) = j >= vlmax ? 0 : *((ETYPE *)vs2 + H(j)); \
@@ -4733,14 +4696,13 @@ GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_d, uint64_t, H8, clearq)
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
+ uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
if (i == 0) { \
@@ -4762,14 +4724,13 @@ GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, uint64_t, H8, clearq)
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
+ uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
if (i == vl - 1) { \
@@ -4792,14 +4753,13 @@ GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, uint64_t, H8, clearq)
void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
+ uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t index, i; \
\
for (i = 0; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
index = *((ETYPE *)vs1 + H(i)); \
@@ -4822,14 +4782,13 @@ GEN_VEXT_VRGATHER_VV(vrgather_vv_d, uint64_t, H8, clearq)
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
+ uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t index = s1, i; \
\
for (i = 0; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
if (index >= vlmax) { \
@@ -4852,13 +4811,12 @@ GEN_VEXT_VRGATHER_VX(vrgather_vx_d, uint64_t, H8, clearq)
void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t mlen = vext_mlen(desc); \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
+ uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vl = env->vl; \
uint32_t num = 0, i; \
\
for (i = 0; i < vl; i++) { \
- if (!vext_elem_mask(vs1, mlen, i)) { \
+ if (!vext_elem_mask(vs1, i)) { \
continue; \
} \
*((ETYPE *)vd + H(num)) = *((ETYPE *)vs2 + H(i)); \
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 12/75] target/riscv: rvv-1.0: add fractional LMUL
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (10 preceding siblings ...)
2021-02-26 3:17 ` [PATCH v7 11/75] target/riscv: rvv-1.0: remove MLEN calculations frank.chang
@ 2021-02-26 3:17 ` frank.chang
2021-02-26 3:17 ` [PATCH v7 13/75] target/riscv: rvv-1.0: add VMA and VTA frank.chang
` (62 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:17 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Alistair Francis, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
Introduce the concepts of fractional LMUL for RVV 1.0.
In RVV 1.0, LMUL bits are contiguous in vtype register.
Also rearrange rvv bits in TB_FLAGS to skip MSTATUS_VS (0x600)
and MSTATUS_FS (0x6000) bits.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 18 ++++++++++--------
target/riscv/translate.c | 16 ++++++++++++++--
target/riscv/vector_helper.c | 16 ++++++++++++++--
3 files changed, 38 insertions(+), 12 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 2c1e6c46a2d..0ba330e613d 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -105,10 +105,10 @@ typedef struct CPURISCVState CPURISCVState;
#define RV_VLEN_MAX 256
-FIELD(VTYPE, VLMUL, 0, 2)
-FIELD(VTYPE, VSEW, 2, 3)
-FIELD(VTYPE, VEDIV, 5, 2)
-FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9)
+FIELD(VTYPE, VLMUL, 0, 3)
+FIELD(VTYPE, VSEW, 3, 3)
+FIELD(VTYPE, VEDIV, 8, 2)
+FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)
FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
struct CPURISCVState {
@@ -381,12 +381,14 @@ typedef RISCVCPU ArchCPU;
#include "exec/cpu-all.h"
FIELD(TB_FLAGS, MEM_IDX, 0, 3)
-FIELD(TB_FLAGS, VL_EQ_VLMAX, 3, 1)
-FIELD(TB_FLAGS, LMUL, 4, 2)
+FIELD(TB_FLAGS, LMUL, 3, 3)
FIELD(TB_FLAGS, SEW, 6, 3)
-FIELD(TB_FLAGS, VILL, 9, 1)
+/* Skip MSTATUS_VS (0x600) bits */
+FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1)
+FIELD(TB_FLAGS, VILL, 12, 1)
+/* Skip MSTATUS_FS (0x6000) bits */
/* Is a Hypervisor instruction load/store allowed? */
-FIELD(TB_FLAGS, HLSX, 10, 1)
+FIELD(TB_FLAGS, HLSX, 15, 1)
bool riscv_cpu_is_32bit(CPURISCVState *env);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 6e1896188c0..75ed94c802b 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -60,7 +60,19 @@ typedef struct DisasContext {
bool hlsx;
/* vector extension */
bool vill;
- uint8_t lmul;
+ /*
+ * Encode LMUL to lmul as follows:
+ * LMUL vlmul lmul
+ * 1 000 0
+ * 2 001 1
+ * 4 010 2
+ * 8 011 3
+ * - 100 -
+ * 1/8 101 -3
+ * 1/4 110 -2
+ * 1/2 111 -1
+ */
+ int8_t lmul;
uint8_t sew;
uint16_t vlen;
bool vl_eq_vlmax;
@@ -853,7 +865,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX);
ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);
ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
- ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL);
+ ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3);
ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
ctx->cs = cs;
}
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 12301e943e6..aa8348ea25a 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -86,9 +86,21 @@ static inline uint32_t vext_vm(uint32_t desc)
return FIELD_EX32(simd_data(desc), VDATA, VM);
}
-static inline uint32_t vext_lmul(uint32_t desc)
+/*
+ * Encode LMUL to lmul as following:
+ * LMUL vlmul lmul
+ * 1 000 0
+ * 2 001 1
+ * 4 010 2
+ * 8 011 3
+ * - 100 -
+ * 1/8 101 -3
+ * 1/4 110 -2
+ * 1/2 111 -1
+ */
+static inline int32_t vext_lmul(uint32_t desc)
{
- return FIELD_EX32(simd_data(desc), VDATA, LMUL);
+ return sextract32(FIELD_EX32(simd_data(desc), VDATA, LMUL), 0, 3);
}
static uint32_t vext_wd(uint32_t desc)
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 13/75] target/riscv: rvv-1.0: add VMA and VTA
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (11 preceding siblings ...)
2021-02-26 3:17 ` [PATCH v7 12/75] target/riscv: rvv-1.0: add fractional LMUL frank.chang
@ 2021-02-26 3:17 ` frank.chang
2021-02-26 3:17 ` [PATCH v7 14/75] target/riscv: rvv-1.0: update check functions frank.chang
` (61 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:17 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Alistair Francis, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
Introduce vma and vta fields in vtype register.
According to RVV 1.0 spec (section 3.3.3):
When a set is marked agnostic, the corresponding set of destination
elements in any vector or mask destination operand can either retain
the value they previously held, or are overwritten with 1s.
So, either vta/vma is set to undisturbed or agnostic, it's legal to
retain the inactive masked-off elements and tail elements' original
values unchanged. Therefore, besides declaring vta/vma fields in vtype
register, also remove all the tail elements clean functions in this
commit.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 2 +
target/riscv/vector_helper.c | 1927 ++++++++++++++++------------------
2 files changed, 891 insertions(+), 1038 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0ba330e613d..ad79669a2ce 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -107,6 +107,8 @@ typedef struct CPURISCVState CPURISCVState;
FIELD(VTYPE, VLMUL, 0, 3)
FIELD(VTYPE, VSEW, 3, 3)
+FIELD(VTYPE, VTA, 6, 1)
+FIELD(VTYPE, VMA, 7, 1)
FIELD(VTYPE, VEDIV, 8, 2)
FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)
FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index aa8348ea25a..89aa7cbf73f 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -146,55 +146,6 @@ static void probe_pages(CPURISCVState *env, target_ulong addr,
}
}
-#ifdef HOST_WORDS_BIGENDIAN
-static void vext_clear(void *tail, uint32_t cnt, uint32_t tot)
-{
- /*
- * Split the remaining range to two parts.
- * The first part is in the last uint64_t unit.
- * The second part start from the next uint64_t unit.
- */
- int part1 = 0, part2 = tot - cnt;
- if (cnt % 8) {
- part1 = 8 - (cnt % 8);
- part2 = tot - cnt - part1;
- memset(QEMU_ALIGN_PTR_DOWN(tail, 8), 0, part1);
- memset(QEMU_ALIGN_PTR_UP(tail, 8), 0, part2);
- } else {
- memset(tail, 0, part2);
- }
-}
-#else
-static void vext_clear(void *tail, uint32_t cnt, uint32_t tot)
-{
- memset(tail, 0, tot - cnt);
-}
-#endif
-
-static void clearb(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot)
-{
- int8_t *cur = ((int8_t *)vd + H1(idx));
- vext_clear(cur, cnt, tot);
-}
-
-static void clearh(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot)
-{
- int16_t *cur = ((int16_t *)vd + H2(idx));
- vext_clear(cur, cnt, tot);
-}
-
-static void clearl(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot)
-{
- int32_t *cur = ((int32_t *)vd + H4(idx));
- vext_clear(cur, cnt, tot);
-}
-
-static void clearq(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot)
-{
- int64_t *cur = (int64_t *)vd + idx;
- vext_clear(cur, cnt, tot);
-}
-
static inline void vext_set_elem_mask(void *v0, int index,
uint8_t value)
{
@@ -219,7 +170,6 @@ static inline int vext_elem_mask(void *v0, int index)
/* elements operations for load and store */
typedef void vext_ldst_elem_fn(CPURISCVState *env, target_ulong addr,
uint32_t idx, void *vd, uintptr_t retaddr);
-typedef void clear_fn(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot);
#define GEN_VEXT_LD_ELEM(NAME, MTYPE, ETYPE, H, LDSUF) \
static void NAME(CPURISCVState *env, abi_ptr addr, \
@@ -283,7 +233,7 @@ static void
vext_ldst_stride(void *vd, void *v0, target_ulong base,
target_ulong stride, CPURISCVState *env,
uint32_t desc, uint32_t vm,
- vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
+ vext_ldst_elem_fn *ldst_elem,
uint32_t esz, uint32_t msz, uintptr_t ra,
MMUAccessType access_type)
{
@@ -310,47 +260,41 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
k++;
}
}
- /* clear tail elements */
- if (clear_elem) {
- for (k = 0; k < nf; k++) {
- clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz);
- }
- }
}
-#define GEN_VEXT_LD_STRIDE(NAME, MTYPE, ETYPE, LOAD_FN, CLEAR_FN) \
+#define GEN_VEXT_LD_STRIDE(NAME, MTYPE, ETYPE, LOAD_FN) \
void HELPER(NAME)(void *vd, void * v0, target_ulong base, \
target_ulong stride, CPURISCVState *env, \
uint32_t desc) \
{ \
uint32_t vm = vext_vm(desc); \
vext_ldst_stride(vd, v0, base, stride, env, desc, vm, LOAD_FN, \
- CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \
+ sizeof(ETYPE), sizeof(MTYPE), \
GETPC(), MMU_DATA_LOAD); \
}
-GEN_VEXT_LD_STRIDE(vlsb_v_b, int8_t, int8_t, ldb_b, clearb)
-GEN_VEXT_LD_STRIDE(vlsb_v_h, int8_t, int16_t, ldb_h, clearh)
-GEN_VEXT_LD_STRIDE(vlsb_v_w, int8_t, int32_t, ldb_w, clearl)
-GEN_VEXT_LD_STRIDE(vlsb_v_d, int8_t, int64_t, ldb_d, clearq)
-GEN_VEXT_LD_STRIDE(vlsh_v_h, int16_t, int16_t, ldh_h, clearh)
-GEN_VEXT_LD_STRIDE(vlsh_v_w, int16_t, int32_t, ldh_w, clearl)
-GEN_VEXT_LD_STRIDE(vlsh_v_d, int16_t, int64_t, ldh_d, clearq)
-GEN_VEXT_LD_STRIDE(vlsw_v_w, int32_t, int32_t, ldw_w, clearl)
-GEN_VEXT_LD_STRIDE(vlsw_v_d, int32_t, int64_t, ldw_d, clearq)
-GEN_VEXT_LD_STRIDE(vlse_v_b, int8_t, int8_t, lde_b, clearb)
-GEN_VEXT_LD_STRIDE(vlse_v_h, int16_t, int16_t, lde_h, clearh)
-GEN_VEXT_LD_STRIDE(vlse_v_w, int32_t, int32_t, lde_w, clearl)
-GEN_VEXT_LD_STRIDE(vlse_v_d, int64_t, int64_t, lde_d, clearq)
-GEN_VEXT_LD_STRIDE(vlsbu_v_b, uint8_t, uint8_t, ldbu_b, clearb)
-GEN_VEXT_LD_STRIDE(vlsbu_v_h, uint8_t, uint16_t, ldbu_h, clearh)
-GEN_VEXT_LD_STRIDE(vlsbu_v_w, uint8_t, uint32_t, ldbu_w, clearl)
-GEN_VEXT_LD_STRIDE(vlsbu_v_d, uint8_t, uint64_t, ldbu_d, clearq)
-GEN_VEXT_LD_STRIDE(vlshu_v_h, uint16_t, uint16_t, ldhu_h, clearh)
-GEN_VEXT_LD_STRIDE(vlshu_v_w, uint16_t, uint32_t, ldhu_w, clearl)
-GEN_VEXT_LD_STRIDE(vlshu_v_d, uint16_t, uint64_t, ldhu_d, clearq)
-GEN_VEXT_LD_STRIDE(vlswu_v_w, uint32_t, uint32_t, ldwu_w, clearl)
-GEN_VEXT_LD_STRIDE(vlswu_v_d, uint32_t, uint64_t, ldwu_d, clearq)
+GEN_VEXT_LD_STRIDE(vlsb_v_b, int8_t, int8_t, ldb_b)
+GEN_VEXT_LD_STRIDE(vlsb_v_h, int8_t, int16_t, ldb_h)
+GEN_VEXT_LD_STRIDE(vlsb_v_w, int8_t, int32_t, ldb_w)
+GEN_VEXT_LD_STRIDE(vlsb_v_d, int8_t, int64_t, ldb_d)
+GEN_VEXT_LD_STRIDE(vlsh_v_h, int16_t, int16_t, ldh_h)
+GEN_VEXT_LD_STRIDE(vlsh_v_w, int16_t, int32_t, ldh_w)
+GEN_VEXT_LD_STRIDE(vlsh_v_d, int16_t, int64_t, ldh_d)
+GEN_VEXT_LD_STRIDE(vlsw_v_w, int32_t, int32_t, ldw_w)
+GEN_VEXT_LD_STRIDE(vlsw_v_d, int32_t, int64_t, ldw_d)
+GEN_VEXT_LD_STRIDE(vlse_v_b, int8_t, int8_t, lde_b)
+GEN_VEXT_LD_STRIDE(vlse_v_h, int16_t, int16_t, lde_h)
+GEN_VEXT_LD_STRIDE(vlse_v_w, int32_t, int32_t, lde_w)
+GEN_VEXT_LD_STRIDE(vlse_v_d, int64_t, int64_t, lde_d)
+GEN_VEXT_LD_STRIDE(vlsbu_v_b, uint8_t, uint8_t, ldbu_b)
+GEN_VEXT_LD_STRIDE(vlsbu_v_h, uint8_t, uint16_t, ldbu_h)
+GEN_VEXT_LD_STRIDE(vlsbu_v_w, uint8_t, uint32_t, ldbu_w)
+GEN_VEXT_LD_STRIDE(vlsbu_v_d, uint8_t, uint64_t, ldbu_d)
+GEN_VEXT_LD_STRIDE(vlshu_v_h, uint16_t, uint16_t, ldhu_h)
+GEN_VEXT_LD_STRIDE(vlshu_v_w, uint16_t, uint32_t, ldhu_w)
+GEN_VEXT_LD_STRIDE(vlshu_v_d, uint16_t, uint64_t, ldhu_d)
+GEN_VEXT_LD_STRIDE(vlswu_v_w, uint32_t, uint32_t, ldwu_w)
+GEN_VEXT_LD_STRIDE(vlswu_v_d, uint32_t, uint64_t, ldwu_d)
#define GEN_VEXT_ST_STRIDE(NAME, MTYPE, ETYPE, STORE_FN) \
void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
@@ -359,7 +303,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
{ \
uint32_t vm = vext_vm(desc); \
vext_ldst_stride(vd, v0, base, stride, env, desc, vm, STORE_FN, \
- NULL, sizeof(ETYPE), sizeof(MTYPE), \
+ sizeof(ETYPE), sizeof(MTYPE), \
GETPC(), MMU_DATA_STORE); \
}
@@ -384,9 +328,8 @@ GEN_VEXT_ST_STRIDE(vsse_v_d, int64_t, int64_t, ste_d)
/* unmasked unit-stride load and store operation*/
static void
vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
- vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
- uint32_t esz, uint32_t msz, uintptr_t ra,
- MMUAccessType access_type)
+ vext_ldst_elem_fn *ldst_elem, uint32_t esz, uint32_t msz,
+ uintptr_t ra, MMUAccessType access_type)
{
uint32_t i, k;
uint32_t nf = vext_nf(desc);
@@ -403,12 +346,6 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
k++;
}
}
- /* clear tail elements */
- if (clear_elem) {
- for (k = 0; k < nf; k++) {
- clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz);
- }
- }
}
/*
@@ -416,45 +353,45 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
* stride = NF * sizeof (MTYPE)
*/
-#define GEN_VEXT_LD_US(NAME, MTYPE, ETYPE, LOAD_FN, CLEAR_FN) \
+#define GEN_VEXT_LD_US(NAME, MTYPE, ETYPE, LOAD_FN) \
void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \
CPURISCVState *env, uint32_t desc) \
{ \
uint32_t stride = vext_nf(desc) * sizeof(MTYPE); \
vext_ldst_stride(vd, v0, base, stride, env, desc, false, LOAD_FN, \
- CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \
+ sizeof(ETYPE), sizeof(MTYPE), \
GETPC(), MMU_DATA_LOAD); \
} \
\
void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
CPURISCVState *env, uint32_t desc) \
{ \
- vext_ldst_us(vd, base, env, desc, LOAD_FN, CLEAR_FN, \
+ vext_ldst_us(vd, base, env, desc, LOAD_FN, \
sizeof(ETYPE), sizeof(MTYPE), GETPC(), MMU_DATA_LOAD); \
}
-GEN_VEXT_LD_US(vlb_v_b, int8_t, int8_t, ldb_b, clearb)
-GEN_VEXT_LD_US(vlb_v_h, int8_t, int16_t, ldb_h, clearh)
-GEN_VEXT_LD_US(vlb_v_w, int8_t, int32_t, ldb_w, clearl)
-GEN_VEXT_LD_US(vlb_v_d, int8_t, int64_t, ldb_d, clearq)
-GEN_VEXT_LD_US(vlh_v_h, int16_t, int16_t, ldh_h, clearh)
-GEN_VEXT_LD_US(vlh_v_w, int16_t, int32_t, ldh_w, clearl)
-GEN_VEXT_LD_US(vlh_v_d, int16_t, int64_t, ldh_d, clearq)
-GEN_VEXT_LD_US(vlw_v_w, int32_t, int32_t, ldw_w, clearl)
-GEN_VEXT_LD_US(vlw_v_d, int32_t, int64_t, ldw_d, clearq)
-GEN_VEXT_LD_US(vle_v_b, int8_t, int8_t, lde_b, clearb)
-GEN_VEXT_LD_US(vle_v_h, int16_t, int16_t, lde_h, clearh)
-GEN_VEXT_LD_US(vle_v_w, int32_t, int32_t, lde_w, clearl)
-GEN_VEXT_LD_US(vle_v_d, int64_t, int64_t, lde_d, clearq)
-GEN_VEXT_LD_US(vlbu_v_b, uint8_t, uint8_t, ldbu_b, clearb)
-GEN_VEXT_LD_US(vlbu_v_h, uint8_t, uint16_t, ldbu_h, clearh)
-GEN_VEXT_LD_US(vlbu_v_w, uint8_t, uint32_t, ldbu_w, clearl)
-GEN_VEXT_LD_US(vlbu_v_d, uint8_t, uint64_t, ldbu_d, clearq)
-GEN_VEXT_LD_US(vlhu_v_h, uint16_t, uint16_t, ldhu_h, clearh)
-GEN_VEXT_LD_US(vlhu_v_w, uint16_t, uint32_t, ldhu_w, clearl)
-GEN_VEXT_LD_US(vlhu_v_d, uint16_t, uint64_t, ldhu_d, clearq)
-GEN_VEXT_LD_US(vlwu_v_w, uint32_t, uint32_t, ldwu_w, clearl)
-GEN_VEXT_LD_US(vlwu_v_d, uint32_t, uint64_t, ldwu_d, clearq)
+GEN_VEXT_LD_US(vlb_v_b, int8_t, int8_t, ldb_b)
+GEN_VEXT_LD_US(vlb_v_h, int8_t, int16_t, ldb_h)
+GEN_VEXT_LD_US(vlb_v_w, int8_t, int32_t, ldb_w)
+GEN_VEXT_LD_US(vlb_v_d, int8_t, int64_t, ldb_d)
+GEN_VEXT_LD_US(vlh_v_h, int16_t, int16_t, ldh_h)
+GEN_VEXT_LD_US(vlh_v_w, int16_t, int32_t, ldh_w)
+GEN_VEXT_LD_US(vlh_v_d, int16_t, int64_t, ldh_d)
+GEN_VEXT_LD_US(vlw_v_w, int32_t, int32_t, ldw_w)
+GEN_VEXT_LD_US(vlw_v_d, int32_t, int64_t, ldw_d)
+GEN_VEXT_LD_US(vle_v_b, int8_t, int8_t, lde_b)
+GEN_VEXT_LD_US(vle_v_h, int16_t, int16_t, lde_h)
+GEN_VEXT_LD_US(vle_v_w, int32_t, int32_t, lde_w)
+GEN_VEXT_LD_US(vle_v_d, int64_t, int64_t, lde_d)
+GEN_VEXT_LD_US(vlbu_v_b, uint8_t, uint8_t, ldbu_b)
+GEN_VEXT_LD_US(vlbu_v_h, uint8_t, uint16_t, ldbu_h)
+GEN_VEXT_LD_US(vlbu_v_w, uint8_t, uint32_t, ldbu_w)
+GEN_VEXT_LD_US(vlbu_v_d, uint8_t, uint64_t, ldbu_d)
+GEN_VEXT_LD_US(vlhu_v_h, uint16_t, uint16_t, ldhu_h)
+GEN_VEXT_LD_US(vlhu_v_w, uint16_t, uint32_t, ldhu_w)
+GEN_VEXT_LD_US(vlhu_v_d, uint16_t, uint64_t, ldhu_d)
+GEN_VEXT_LD_US(vlwu_v_w, uint32_t, uint32_t, ldwu_w)
+GEN_VEXT_LD_US(vlwu_v_d, uint32_t, uint64_t, ldwu_d)
#define GEN_VEXT_ST_US(NAME, MTYPE, ETYPE, STORE_FN) \
void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \
@@ -462,14 +399,14 @@ void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \
{ \
uint32_t stride = vext_nf(desc) * sizeof(MTYPE); \
vext_ldst_stride(vd, v0, base, stride, env, desc, false, STORE_FN, \
- NULL, sizeof(ETYPE), sizeof(MTYPE), \
+ sizeof(ETYPE), sizeof(MTYPE), \
GETPC(), MMU_DATA_STORE); \
} \
\
void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
CPURISCVState *env, uint32_t desc) \
{ \
- vext_ldst_us(vd, base, env, desc, STORE_FN, NULL, \
+ vext_ldst_us(vd, base, env, desc, STORE_FN, \
sizeof(ETYPE), sizeof(MTYPE), GETPC(), MMU_DATA_STORE);\
}
@@ -510,7 +447,6 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
void *vs2, CPURISCVState *env, uint32_t desc,
vext_get_index_addr get_index_addr,
vext_ldst_elem_fn *ldst_elem,
- clear_fn *clear_elem,
uint32_t esz, uint32_t msz, uintptr_t ra,
MMUAccessType access_type)
{
@@ -539,52 +475,46 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
k++;
}
}
- /* clear tail elements */
- if (clear_elem) {
- for (k = 0; k < nf; k++) {
- clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz);
- }
- }
}
-#define GEN_VEXT_LD_INDEX(NAME, MTYPE, ETYPE, INDEX_FN, LOAD_FN, CLEAR_FN) \
+#define GEN_VEXT_LD_INDEX(NAME, MTYPE, ETYPE, INDEX_FN, LOAD_FN) \
void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \
- LOAD_FN, CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \
+ LOAD_FN, sizeof(ETYPE), sizeof(MTYPE), \
GETPC(), MMU_DATA_LOAD); \
}
-GEN_VEXT_LD_INDEX(vlxb_v_b, int8_t, int8_t, idx_b, ldb_b, clearb)
-GEN_VEXT_LD_INDEX(vlxb_v_h, int8_t, int16_t, idx_h, ldb_h, clearh)
-GEN_VEXT_LD_INDEX(vlxb_v_w, int8_t, int32_t, idx_w, ldb_w, clearl)
-GEN_VEXT_LD_INDEX(vlxb_v_d, int8_t, int64_t, idx_d, ldb_d, clearq)
-GEN_VEXT_LD_INDEX(vlxh_v_h, int16_t, int16_t, idx_h, ldh_h, clearh)
-GEN_VEXT_LD_INDEX(vlxh_v_w, int16_t, int32_t, idx_w, ldh_w, clearl)
-GEN_VEXT_LD_INDEX(vlxh_v_d, int16_t, int64_t, idx_d, ldh_d, clearq)
-GEN_VEXT_LD_INDEX(vlxw_v_w, int32_t, int32_t, idx_w, ldw_w, clearl)
-GEN_VEXT_LD_INDEX(vlxw_v_d, int32_t, int64_t, idx_d, ldw_d, clearq)
-GEN_VEXT_LD_INDEX(vlxe_v_b, int8_t, int8_t, idx_b, lde_b, clearb)
-GEN_VEXT_LD_INDEX(vlxe_v_h, int16_t, int16_t, idx_h, lde_h, clearh)
-GEN_VEXT_LD_INDEX(vlxe_v_w, int32_t, int32_t, idx_w, lde_w, clearl)
-GEN_VEXT_LD_INDEX(vlxe_v_d, int64_t, int64_t, idx_d, lde_d, clearq)
-GEN_VEXT_LD_INDEX(vlxbu_v_b, uint8_t, uint8_t, idx_b, ldbu_b, clearb)
-GEN_VEXT_LD_INDEX(vlxbu_v_h, uint8_t, uint16_t, idx_h, ldbu_h, clearh)
-GEN_VEXT_LD_INDEX(vlxbu_v_w, uint8_t, uint32_t, idx_w, ldbu_w, clearl)
-GEN_VEXT_LD_INDEX(vlxbu_v_d, uint8_t, uint64_t, idx_d, ldbu_d, clearq)
-GEN_VEXT_LD_INDEX(vlxhu_v_h, uint16_t, uint16_t, idx_h, ldhu_h, clearh)
-GEN_VEXT_LD_INDEX(vlxhu_v_w, uint16_t, uint32_t, idx_w, ldhu_w, clearl)
-GEN_VEXT_LD_INDEX(vlxhu_v_d, uint16_t, uint64_t, idx_d, ldhu_d, clearq)
-GEN_VEXT_LD_INDEX(vlxwu_v_w, uint32_t, uint32_t, idx_w, ldwu_w, clearl)
-GEN_VEXT_LD_INDEX(vlxwu_v_d, uint32_t, uint64_t, idx_d, ldwu_d, clearq)
+GEN_VEXT_LD_INDEX(vlxb_v_b, int8_t, int8_t, idx_b, ldb_b)
+GEN_VEXT_LD_INDEX(vlxb_v_h, int8_t, int16_t, idx_h, ldb_h)
+GEN_VEXT_LD_INDEX(vlxb_v_w, int8_t, int32_t, idx_w, ldb_w)
+GEN_VEXT_LD_INDEX(vlxb_v_d, int8_t, int64_t, idx_d, ldb_d)
+GEN_VEXT_LD_INDEX(vlxh_v_h, int16_t, int16_t, idx_h, ldh_h)
+GEN_VEXT_LD_INDEX(vlxh_v_w, int16_t, int32_t, idx_w, ldh_w)
+GEN_VEXT_LD_INDEX(vlxh_v_d, int16_t, int64_t, idx_d, ldh_d)
+GEN_VEXT_LD_INDEX(vlxw_v_w, int32_t, int32_t, idx_w, ldw_w)
+GEN_VEXT_LD_INDEX(vlxw_v_d, int32_t, int64_t, idx_d, ldw_d)
+GEN_VEXT_LD_INDEX(vlxe_v_b, int8_t, int8_t, idx_b, lde_b)
+GEN_VEXT_LD_INDEX(vlxe_v_h, int16_t, int16_t, idx_h, lde_h)
+GEN_VEXT_LD_INDEX(vlxe_v_w, int32_t, int32_t, idx_w, lde_w)
+GEN_VEXT_LD_INDEX(vlxe_v_d, int64_t, int64_t, idx_d, lde_d)
+GEN_VEXT_LD_INDEX(vlxbu_v_b, uint8_t, uint8_t, idx_b, ldbu_b)
+GEN_VEXT_LD_INDEX(vlxbu_v_h, uint8_t, uint16_t, idx_h, ldbu_h)
+GEN_VEXT_LD_INDEX(vlxbu_v_w, uint8_t, uint32_t, idx_w, ldbu_w)
+GEN_VEXT_LD_INDEX(vlxbu_v_d, uint8_t, uint64_t, idx_d, ldbu_d)
+GEN_VEXT_LD_INDEX(vlxhu_v_h, uint16_t, uint16_t, idx_h, ldhu_h)
+GEN_VEXT_LD_INDEX(vlxhu_v_w, uint16_t, uint32_t, idx_w, ldhu_w)
+GEN_VEXT_LD_INDEX(vlxhu_v_d, uint16_t, uint64_t, idx_d, ldhu_d)
+GEN_VEXT_LD_INDEX(vlxwu_v_w, uint32_t, uint32_t, idx_w, ldwu_w)
+GEN_VEXT_LD_INDEX(vlxwu_v_d, uint32_t, uint64_t, idx_d, ldwu_d)
#define GEN_VEXT_ST_INDEX(NAME, MTYPE, ETYPE, INDEX_FN, STORE_FN)\
void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \
- STORE_FN, NULL, sizeof(ETYPE), sizeof(MTYPE),\
+ STORE_FN, sizeof(ETYPE), sizeof(MTYPE), \
GETPC(), MMU_DATA_STORE); \
}
@@ -609,7 +539,6 @@ static inline void
vext_ldff(void *vd, void *v0, target_ulong base,
CPURISCVState *env, uint32_t desc,
vext_ldst_elem_fn *ldst_elem,
- clear_fn *clear_elem,
uint32_t esz, uint32_t msz, uintptr_t ra)
{
void *host;
@@ -671,45 +600,38 @@ ProbeSuccess:
k++;
}
}
- /* clear tail elements */
- if (vl != 0) {
- return;
- }
- for (k = 0; k < nf; k++) {
- clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz);
- }
}
-#define GEN_VEXT_LDFF(NAME, MTYPE, ETYPE, LOAD_FN, CLEAR_FN) \
+#define GEN_VEXT_LDFF(NAME, MTYPE, ETYPE, LOAD_FN) \
void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
CPURISCVState *env, uint32_t desc) \
{ \
- vext_ldff(vd, v0, base, env, desc, LOAD_FN, CLEAR_FN, \
+ vext_ldff(vd, v0, base, env, desc, LOAD_FN, \
sizeof(ETYPE), sizeof(MTYPE), GETPC()); \
}
-GEN_VEXT_LDFF(vlbff_v_b, int8_t, int8_t, ldb_b, clearb)
-GEN_VEXT_LDFF(vlbff_v_h, int8_t, int16_t, ldb_h, clearh)
-GEN_VEXT_LDFF(vlbff_v_w, int8_t, int32_t, ldb_w, clearl)
-GEN_VEXT_LDFF(vlbff_v_d, int8_t, int64_t, ldb_d, clearq)
-GEN_VEXT_LDFF(vlhff_v_h, int16_t, int16_t, ldh_h, clearh)
-GEN_VEXT_LDFF(vlhff_v_w, int16_t, int32_t, ldh_w, clearl)
-GEN_VEXT_LDFF(vlhff_v_d, int16_t, int64_t, ldh_d, clearq)
-GEN_VEXT_LDFF(vlwff_v_w, int32_t, int32_t, ldw_w, clearl)
-GEN_VEXT_LDFF(vlwff_v_d, int32_t, int64_t, ldw_d, clearq)
-GEN_VEXT_LDFF(vleff_v_b, int8_t, int8_t, lde_b, clearb)
-GEN_VEXT_LDFF(vleff_v_h, int16_t, int16_t, lde_h, clearh)
-GEN_VEXT_LDFF(vleff_v_w, int32_t, int32_t, lde_w, clearl)
-GEN_VEXT_LDFF(vleff_v_d, int64_t, int64_t, lde_d, clearq)
-GEN_VEXT_LDFF(vlbuff_v_b, uint8_t, uint8_t, ldbu_b, clearb)
-GEN_VEXT_LDFF(vlbuff_v_h, uint8_t, uint16_t, ldbu_h, clearh)
-GEN_VEXT_LDFF(vlbuff_v_w, uint8_t, uint32_t, ldbu_w, clearl)
-GEN_VEXT_LDFF(vlbuff_v_d, uint8_t, uint64_t, ldbu_d, clearq)
-GEN_VEXT_LDFF(vlhuff_v_h, uint16_t, uint16_t, ldhu_h, clearh)
-GEN_VEXT_LDFF(vlhuff_v_w, uint16_t, uint32_t, ldhu_w, clearl)
-GEN_VEXT_LDFF(vlhuff_v_d, uint16_t, uint64_t, ldhu_d, clearq)
-GEN_VEXT_LDFF(vlwuff_v_w, uint32_t, uint32_t, ldwu_w, clearl)
-GEN_VEXT_LDFF(vlwuff_v_d, uint32_t, uint64_t, ldwu_d, clearq)
+GEN_VEXT_LDFF(vlbff_v_b, int8_t, int8_t, ldb_b)
+GEN_VEXT_LDFF(vlbff_v_h, int8_t, int16_t, ldb_h)
+GEN_VEXT_LDFF(vlbff_v_w, int8_t, int32_t, ldb_w)
+GEN_VEXT_LDFF(vlbff_v_d, int8_t, int64_t, ldb_d)
+GEN_VEXT_LDFF(vlhff_v_h, int16_t, int16_t, ldh_h)
+GEN_VEXT_LDFF(vlhff_v_w, int16_t, int32_t, ldh_w)
+GEN_VEXT_LDFF(vlhff_v_d, int16_t, int64_t, ldh_d)
+GEN_VEXT_LDFF(vlwff_v_w, int32_t, int32_t, ldw_w)
+GEN_VEXT_LDFF(vlwff_v_d, int32_t, int64_t, ldw_d)
+GEN_VEXT_LDFF(vleff_v_b, int8_t, int8_t, lde_b)
+GEN_VEXT_LDFF(vleff_v_h, int16_t, int16_t, lde_h)
+GEN_VEXT_LDFF(vleff_v_w, int32_t, int32_t, lde_w)
+GEN_VEXT_LDFF(vleff_v_d, int64_t, int64_t, lde_d)
+GEN_VEXT_LDFF(vlbuff_v_b, uint8_t, uint8_t, ldbu_b)
+GEN_VEXT_LDFF(vlbuff_v_h, uint8_t, uint16_t, ldbu_h)
+GEN_VEXT_LDFF(vlbuff_v_w, uint8_t, uint32_t, ldbu_w)
+GEN_VEXT_LDFF(vlbuff_v_d, uint8_t, uint64_t, ldbu_d)
+GEN_VEXT_LDFF(vlhuff_v_h, uint16_t, uint16_t, ldhu_h)
+GEN_VEXT_LDFF(vlhuff_v_w, uint16_t, uint32_t, ldhu_w)
+GEN_VEXT_LDFF(vlhuff_v_d, uint16_t, uint64_t, ldhu_d)
+GEN_VEXT_LDFF(vlwuff_v_w, uint32_t, uint32_t, ldwu_w)
+GEN_VEXT_LDFF(vlwuff_v_d, uint32_t, uint64_t, ldwu_d)
/*
*** Vector AMO Operations (Zvamo)
@@ -786,14 +708,12 @@ vext_amo_noatomic(void *vs3, void *v0, target_ulong base,
void *vs2, CPURISCVState *env, uint32_t desc,
vext_get_index_addr get_index_addr,
vext_amo_noatomic_fn *noatomic_op,
- clear_fn *clear_elem,
uint32_t esz, uint32_t msz, uintptr_t ra)
{
uint32_t i;
target_long addr;
uint32_t wd = vext_wd(desc);
uint32_t vm = vext_vm(desc);
- uint32_t vlmax = vext_maxsz(desc) / esz;
for (i = 0; i < env->vl; i++) {
if (!vm && !vext_elem_mask(v0, i)) {
@@ -809,48 +729,47 @@ vext_amo_noatomic(void *vs3, void *v0, target_ulong base,
addr = get_index_addr(base, i, vs2);
noatomic_op(vs3, addr, wd, i, env, ra);
}
- clear_elem(vs3, env->vl, env->vl * esz, vlmax * esz);
}
-#define GEN_VEXT_AMO(NAME, MTYPE, ETYPE, INDEX_FN, CLEAR_FN) \
+#define GEN_VEXT_AMO(NAME, MTYPE, ETYPE, INDEX_FN) \
void HELPER(NAME)(void *vs3, void *v0, target_ulong base, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
vext_amo_noatomic(vs3, v0, base, vs2, env, desc, \
INDEX_FN, vext_##NAME##_noatomic_op, \
- CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \
+ sizeof(ETYPE), sizeof(MTYPE), \
GETPC()); \
}
#ifdef TARGET_RISCV64
-GEN_VEXT_AMO(vamoswapw_v_d, int32_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamoswapd_v_d, int64_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamoaddw_v_d, int32_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamoaddd_v_d, int64_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamoxorw_v_d, int32_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamoxord_v_d, int64_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamoandw_v_d, int32_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamoandd_v_d, int64_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamoorw_v_d, int32_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamoord_v_d, int64_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamominw_v_d, int32_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamomind_v_d, int64_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamomaxw_v_d, int32_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamomaxd_v_d, int64_t, int64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamominuw_v_d, uint32_t, uint64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamominud_v_d, uint64_t, uint64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamomaxuw_v_d, uint32_t, uint64_t, idx_d, clearq)
-GEN_VEXT_AMO(vamomaxud_v_d, uint64_t, uint64_t, idx_d, clearq)
+GEN_VEXT_AMO(vamoswapw_v_d, int32_t, int64_t, idx_d)
+GEN_VEXT_AMO(vamoswapd_v_d, int64_t, int64_t, idx_d)
+GEN_VEXT_AMO(vamoaddw_v_d, int32_t, int64_t, idx_d)
+GEN_VEXT_AMO(vamoaddd_v_d, int64_t, int64_t, idx_d)
+GEN_VEXT_AMO(vamoxorw_v_d, int32_t, int64_t, idx_d)
+GEN_VEXT_AMO(vamoxord_v_d, int64_t, int64_t, idx_d)
+GEN_VEXT_AMO(vamoandw_v_d, int32_t, int64_t, idx_d)
+GEN_VEXT_AMO(vamoandd_v_d, int64_t, int64_t, idx_d)
+GEN_VEXT_AMO(vamoorw_v_d, int32_t, int64_t, idx_d)
+GEN_VEXT_AMO(vamoord_v_d, int64_t, int64_t, idx_d)
+GEN_VEXT_AMO(vamominw_v_d, int32_t, int64_t, idx_d)
+GEN_VEXT_AMO(vamomind_v_d, int64_t, int64_t, idx_d)
+GEN_VEXT_AMO(vamomaxw_v_d, int32_t, int64_t, idx_d)
+GEN_VEXT_AMO(vamomaxd_v_d, int64_t, int64_t, idx_d)
+GEN_VEXT_AMO(vamominuw_v_d, uint32_t, uint64_t, idx_d)
+GEN_VEXT_AMO(vamominud_v_d, uint64_t, uint64_t, idx_d)
+GEN_VEXT_AMO(vamomaxuw_v_d, uint32_t, uint64_t, idx_d)
+GEN_VEXT_AMO(vamomaxud_v_d, uint64_t, uint64_t, idx_d)
#endif
-GEN_VEXT_AMO(vamoswapw_v_w, int32_t, int32_t, idx_w, clearl)
-GEN_VEXT_AMO(vamoaddw_v_w, int32_t, int32_t, idx_w, clearl)
-GEN_VEXT_AMO(vamoxorw_v_w, int32_t, int32_t, idx_w, clearl)
-GEN_VEXT_AMO(vamoandw_v_w, int32_t, int32_t, idx_w, clearl)
-GEN_VEXT_AMO(vamoorw_v_w, int32_t, int32_t, idx_w, clearl)
-GEN_VEXT_AMO(vamominw_v_w, int32_t, int32_t, idx_w, clearl)
-GEN_VEXT_AMO(vamomaxw_v_w, int32_t, int32_t, idx_w, clearl)
-GEN_VEXT_AMO(vamominuw_v_w, uint32_t, uint32_t, idx_w, clearl)
-GEN_VEXT_AMO(vamomaxuw_v_w, uint32_t, uint32_t, idx_w, clearl)
+GEN_VEXT_AMO(vamoswapw_v_w, int32_t, int32_t, idx_w)
+GEN_VEXT_AMO(vamoaddw_v_w, int32_t, int32_t, idx_w)
+GEN_VEXT_AMO(vamoxorw_v_w, int32_t, int32_t, idx_w)
+GEN_VEXT_AMO(vamoandw_v_w, int32_t, int32_t, idx_w)
+GEN_VEXT_AMO(vamoorw_v_w, int32_t, int32_t, idx_w)
+GEN_VEXT_AMO(vamominw_v_w, int32_t, int32_t, idx_w)
+GEN_VEXT_AMO(vamomaxw_v_w, int32_t, int32_t, idx_w)
+GEN_VEXT_AMO(vamominuw_v_w, uint32_t, uint32_t, idx_w)
+GEN_VEXT_AMO(vamomaxuw_v_w, uint32_t, uint32_t, idx_w)
/*
*** Vector Integer Arithmetic Instructions
@@ -916,9 +835,8 @@ RVVCALL(OPIVV2, vsub_vv_d, OP_SSS_D, H8, H8, H8, DO_SUB)
static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2,
CPURISCVState *env, uint32_t desc,
uint32_t esz, uint32_t dsz,
- opivv2_fn *fn, clear_fn *clearfn)
+ opivv2_fn *fn)
{
- uint32_t vlmax = vext_maxsz(desc) / esz;
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
uint32_t i;
@@ -929,27 +847,26 @@ static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2,
}
fn(vd, vs1, vs2, i);
}
- clearfn(vd, vl, vl * dsz, vlmax * dsz);
}
/* generate the helpers for OPIVV */
-#define GEN_VEXT_VV(NAME, ESZ, DSZ, CLEAR_FN) \
+#define GEN_VEXT_VV(NAME, ESZ, DSZ) \
void HELPER(NAME)(void *vd, void *v0, void *vs1, \
void *vs2, CPURISCVState *env, \
uint32_t desc) \
{ \
do_vext_vv(vd, v0, vs1, vs2, env, desc, ESZ, DSZ, \
- do_##NAME, CLEAR_FN); \
+ do_##NAME); \
}
-GEN_VEXT_VV(vadd_vv_b, 1, 1, clearb)
-GEN_VEXT_VV(vadd_vv_h, 2, 2, clearh)
-GEN_VEXT_VV(vadd_vv_w, 4, 4, clearl)
-GEN_VEXT_VV(vadd_vv_d, 8, 8, clearq)
-GEN_VEXT_VV(vsub_vv_b, 1, 1, clearb)
-GEN_VEXT_VV(vsub_vv_h, 2, 2, clearh)
-GEN_VEXT_VV(vsub_vv_w, 4, 4, clearl)
-GEN_VEXT_VV(vsub_vv_d, 8, 8, clearq)
+GEN_VEXT_VV(vadd_vv_b, 1, 1)
+GEN_VEXT_VV(vadd_vv_h, 2, 2)
+GEN_VEXT_VV(vadd_vv_w, 4, 4)
+GEN_VEXT_VV(vadd_vv_d, 8, 8)
+GEN_VEXT_VV(vsub_vv_b, 1, 1)
+GEN_VEXT_VV(vsub_vv_h, 2, 2)
+GEN_VEXT_VV(vsub_vv_w, 4, 4)
+GEN_VEXT_VV(vsub_vv_d, 8, 8)
typedef void opivx2_fn(void *vd, target_long s1, void *vs2, int i);
@@ -980,9 +897,8 @@ RVVCALL(OPIVX2, vrsub_vx_d, OP_SSS_D, H8, H8, DO_RSUB)
static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2,
CPURISCVState *env, uint32_t desc,
uint32_t esz, uint32_t dsz,
- opivx2_fn fn, clear_fn *clearfn)
+ opivx2_fn fn)
{
- uint32_t vlmax = vext_maxsz(desc) / esz;
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
uint32_t i;
@@ -993,31 +909,30 @@ static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2,
}
fn(vd, s1, vs2, i);
}
- clearfn(vd, vl, vl * dsz, vlmax * dsz);
}
/* generate the helpers for OPIVX */
-#define GEN_VEXT_VX(NAME, ESZ, DSZ, CLEAR_FN) \
+#define GEN_VEXT_VX(NAME, ESZ, DSZ) \
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
void *vs2, CPURISCVState *env, \
uint32_t desc) \
{ \
do_vext_vx(vd, v0, s1, vs2, env, desc, ESZ, DSZ, \
- do_##NAME, CLEAR_FN); \
-}
-
-GEN_VEXT_VX(vadd_vx_b, 1, 1, clearb)
-GEN_VEXT_VX(vadd_vx_h, 2, 2, clearh)
-GEN_VEXT_VX(vadd_vx_w, 4, 4, clearl)
-GEN_VEXT_VX(vadd_vx_d, 8, 8, clearq)
-GEN_VEXT_VX(vsub_vx_b, 1, 1, clearb)
-GEN_VEXT_VX(vsub_vx_h, 2, 2, clearh)
-GEN_VEXT_VX(vsub_vx_w, 4, 4, clearl)
-GEN_VEXT_VX(vsub_vx_d, 8, 8, clearq)
-GEN_VEXT_VX(vrsub_vx_b, 1, 1, clearb)
-GEN_VEXT_VX(vrsub_vx_h, 2, 2, clearh)
-GEN_VEXT_VX(vrsub_vx_w, 4, 4, clearl)
-GEN_VEXT_VX(vrsub_vx_d, 8, 8, clearq)
+ do_##NAME); \
+}
+
+GEN_VEXT_VX(vadd_vx_b, 1, 1)
+GEN_VEXT_VX(vadd_vx_h, 2, 2)
+GEN_VEXT_VX(vadd_vx_w, 4, 4)
+GEN_VEXT_VX(vadd_vx_d, 8, 8)
+GEN_VEXT_VX(vsub_vx_b, 1, 1)
+GEN_VEXT_VX(vsub_vx_h, 2, 2)
+GEN_VEXT_VX(vsub_vx_w, 4, 4)
+GEN_VEXT_VX(vsub_vx_d, 8, 8)
+GEN_VEXT_VX(vrsub_vx_b, 1, 1)
+GEN_VEXT_VX(vrsub_vx_h, 2, 2)
+GEN_VEXT_VX(vrsub_vx_w, 4, 4)
+GEN_VEXT_VX(vrsub_vx_d, 8, 8)
void HELPER(vec_rsubs8)(void *d, void *a, uint64_t b, uint32_t desc)
{
@@ -1096,30 +1011,30 @@ RVVCALL(OPIVV2, vwadd_wv_w, WOP_WSSS_W, H8, H4, H4, DO_ADD)
RVVCALL(OPIVV2, vwsub_wv_b, WOP_WSSS_B, H2, H1, H1, DO_SUB)
RVVCALL(OPIVV2, vwsub_wv_h, WOP_WSSS_H, H4, H2, H2, DO_SUB)
RVVCALL(OPIVV2, vwsub_wv_w, WOP_WSSS_W, H8, H4, H4, DO_SUB)
-GEN_VEXT_VV(vwaddu_vv_b, 1, 2, clearh)
-GEN_VEXT_VV(vwaddu_vv_h, 2, 4, clearl)
-GEN_VEXT_VV(vwaddu_vv_w, 4, 8, clearq)
-GEN_VEXT_VV(vwsubu_vv_b, 1, 2, clearh)
-GEN_VEXT_VV(vwsubu_vv_h, 2, 4, clearl)
-GEN_VEXT_VV(vwsubu_vv_w, 4, 8, clearq)
-GEN_VEXT_VV(vwadd_vv_b, 1, 2, clearh)
-GEN_VEXT_VV(vwadd_vv_h, 2, 4, clearl)
-GEN_VEXT_VV(vwadd_vv_w, 4, 8, clearq)
-GEN_VEXT_VV(vwsub_vv_b, 1, 2, clearh)
-GEN_VEXT_VV(vwsub_vv_h, 2, 4, clearl)
-GEN_VEXT_VV(vwsub_vv_w, 4, 8, clearq)
-GEN_VEXT_VV(vwaddu_wv_b, 1, 2, clearh)
-GEN_VEXT_VV(vwaddu_wv_h, 2, 4, clearl)
-GEN_VEXT_VV(vwaddu_wv_w, 4, 8, clearq)
-GEN_VEXT_VV(vwsubu_wv_b, 1, 2, clearh)
-GEN_VEXT_VV(vwsubu_wv_h, 2, 4, clearl)
-GEN_VEXT_VV(vwsubu_wv_w, 4, 8, clearq)
-GEN_VEXT_VV(vwadd_wv_b, 1, 2, clearh)
-GEN_VEXT_VV(vwadd_wv_h, 2, 4, clearl)
-GEN_VEXT_VV(vwadd_wv_w, 4, 8, clearq)
-GEN_VEXT_VV(vwsub_wv_b, 1, 2, clearh)
-GEN_VEXT_VV(vwsub_wv_h, 2, 4, clearl)
-GEN_VEXT_VV(vwsub_wv_w, 4, 8, clearq)
+GEN_VEXT_VV(vwaddu_vv_b, 1, 2)
+GEN_VEXT_VV(vwaddu_vv_h, 2, 4)
+GEN_VEXT_VV(vwaddu_vv_w, 4, 8)
+GEN_VEXT_VV(vwsubu_vv_b, 1, 2)
+GEN_VEXT_VV(vwsubu_vv_h, 2, 4)
+GEN_VEXT_VV(vwsubu_vv_w, 4, 8)
+GEN_VEXT_VV(vwadd_vv_b, 1, 2)
+GEN_VEXT_VV(vwadd_vv_h, 2, 4)
+GEN_VEXT_VV(vwadd_vv_w, 4, 8)
+GEN_VEXT_VV(vwsub_vv_b, 1, 2)
+GEN_VEXT_VV(vwsub_vv_h, 2, 4)
+GEN_VEXT_VV(vwsub_vv_w, 4, 8)
+GEN_VEXT_VV(vwaddu_wv_b, 1, 2)
+GEN_VEXT_VV(vwaddu_wv_h, 2, 4)
+GEN_VEXT_VV(vwaddu_wv_w, 4, 8)
+GEN_VEXT_VV(vwsubu_wv_b, 1, 2)
+GEN_VEXT_VV(vwsubu_wv_h, 2, 4)
+GEN_VEXT_VV(vwsubu_wv_w, 4, 8)
+GEN_VEXT_VV(vwadd_wv_b, 1, 2)
+GEN_VEXT_VV(vwadd_wv_h, 2, 4)
+GEN_VEXT_VV(vwadd_wv_w, 4, 8)
+GEN_VEXT_VV(vwsub_wv_b, 1, 2)
+GEN_VEXT_VV(vwsub_wv_h, 2, 4)
+GEN_VEXT_VV(vwsub_wv_w, 4, 8)
RVVCALL(OPIVX2, vwaddu_vx_b, WOP_UUU_B, H2, H1, DO_ADD)
RVVCALL(OPIVX2, vwaddu_vx_h, WOP_UUU_H, H4, H2, DO_ADD)
@@ -1145,42 +1060,40 @@ RVVCALL(OPIVX2, vwadd_wx_w, WOP_WSSS_W, H8, H4, DO_ADD)
RVVCALL(OPIVX2, vwsub_wx_b, WOP_WSSS_B, H2, H1, DO_SUB)
RVVCALL(OPIVX2, vwsub_wx_h, WOP_WSSS_H, H4, H2, DO_SUB)
RVVCALL(OPIVX2, vwsub_wx_w, WOP_WSSS_W, H8, H4, DO_SUB)
-GEN_VEXT_VX(vwaddu_vx_b, 1, 2, clearh)
-GEN_VEXT_VX(vwaddu_vx_h, 2, 4, clearl)
-GEN_VEXT_VX(vwaddu_vx_w, 4, 8, clearq)
-GEN_VEXT_VX(vwsubu_vx_b, 1, 2, clearh)
-GEN_VEXT_VX(vwsubu_vx_h, 2, 4, clearl)
-GEN_VEXT_VX(vwsubu_vx_w, 4, 8, clearq)
-GEN_VEXT_VX(vwadd_vx_b, 1, 2, clearh)
-GEN_VEXT_VX(vwadd_vx_h, 2, 4, clearl)
-GEN_VEXT_VX(vwadd_vx_w, 4, 8, clearq)
-GEN_VEXT_VX(vwsub_vx_b, 1, 2, clearh)
-GEN_VEXT_VX(vwsub_vx_h, 2, 4, clearl)
-GEN_VEXT_VX(vwsub_vx_w, 4, 8, clearq)
-GEN_VEXT_VX(vwaddu_wx_b, 1, 2, clearh)
-GEN_VEXT_VX(vwaddu_wx_h, 2, 4, clearl)
-GEN_VEXT_VX(vwaddu_wx_w, 4, 8, clearq)
-GEN_VEXT_VX(vwsubu_wx_b, 1, 2, clearh)
-GEN_VEXT_VX(vwsubu_wx_h, 2, 4, clearl)
-GEN_VEXT_VX(vwsubu_wx_w, 4, 8, clearq)
-GEN_VEXT_VX(vwadd_wx_b, 1, 2, clearh)
-GEN_VEXT_VX(vwadd_wx_h, 2, 4, clearl)
-GEN_VEXT_VX(vwadd_wx_w, 4, 8, clearq)
-GEN_VEXT_VX(vwsub_wx_b, 1, 2, clearh)
-GEN_VEXT_VX(vwsub_wx_h, 2, 4, clearl)
-GEN_VEXT_VX(vwsub_wx_w, 4, 8, clearq)
+GEN_VEXT_VX(vwaddu_vx_b, 1, 2)
+GEN_VEXT_VX(vwaddu_vx_h, 2, 4)
+GEN_VEXT_VX(vwaddu_vx_w, 4, 8)
+GEN_VEXT_VX(vwsubu_vx_b, 1, 2)
+GEN_VEXT_VX(vwsubu_vx_h, 2, 4)
+GEN_VEXT_VX(vwsubu_vx_w, 4, 8)
+GEN_VEXT_VX(vwadd_vx_b, 1, 2)
+GEN_VEXT_VX(vwadd_vx_h, 2, 4)
+GEN_VEXT_VX(vwadd_vx_w, 4, 8)
+GEN_VEXT_VX(vwsub_vx_b, 1, 2)
+GEN_VEXT_VX(vwsub_vx_h, 2, 4)
+GEN_VEXT_VX(vwsub_vx_w, 4, 8)
+GEN_VEXT_VX(vwaddu_wx_b, 1, 2)
+GEN_VEXT_VX(vwaddu_wx_h, 2, 4)
+GEN_VEXT_VX(vwaddu_wx_w, 4, 8)
+GEN_VEXT_VX(vwsubu_wx_b, 1, 2)
+GEN_VEXT_VX(vwsubu_wx_h, 2, 4)
+GEN_VEXT_VX(vwsubu_wx_w, 4, 8)
+GEN_VEXT_VX(vwadd_wx_b, 1, 2)
+GEN_VEXT_VX(vwadd_wx_h, 2, 4)
+GEN_VEXT_VX(vwadd_wx_w, 4, 8)
+GEN_VEXT_VX(vwsub_wx_b, 1, 2)
+GEN_VEXT_VX(vwsub_wx_h, 2, 4)
+GEN_VEXT_VX(vwsub_wx_w, 4, 8)
/* Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions */
#define DO_VADC(N, M, C) (N + M + C)
#define DO_VSBC(N, M, C) (N - M - C)
-#define GEN_VEXT_VADC_VVM(NAME, ETYPE, H, DO_OP, CLEAR_FN) \
+#define GEN_VEXT_VADC_VVM(NAME, ETYPE, H, DO_OP) \
void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
uint32_t vl = env->vl; \
- uint32_t esz = sizeof(ETYPE); \
- uint32_t vlmax = vext_maxsz(desc) / esz; \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
@@ -1190,26 +1103,23 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
\
*((ETYPE *)vd + H(i)) = DO_OP(s2, s1, carry); \
} \
- CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
}
-GEN_VEXT_VADC_VVM(vadc_vvm_b, uint8_t, H1, DO_VADC, clearb)
-GEN_VEXT_VADC_VVM(vadc_vvm_h, uint16_t, H2, DO_VADC, clearh)
-GEN_VEXT_VADC_VVM(vadc_vvm_w, uint32_t, H4, DO_VADC, clearl)
-GEN_VEXT_VADC_VVM(vadc_vvm_d, uint64_t, H8, DO_VADC, clearq)
+GEN_VEXT_VADC_VVM(vadc_vvm_b, uint8_t, H1, DO_VADC)
+GEN_VEXT_VADC_VVM(vadc_vvm_h, uint16_t, H2, DO_VADC)
+GEN_VEXT_VADC_VVM(vadc_vvm_w, uint32_t, H4, DO_VADC)
+GEN_VEXT_VADC_VVM(vadc_vvm_d, uint64_t, H8, DO_VADC)
-GEN_VEXT_VADC_VVM(vsbc_vvm_b, uint8_t, H1, DO_VSBC, clearb)
-GEN_VEXT_VADC_VVM(vsbc_vvm_h, uint16_t, H2, DO_VSBC, clearh)
-GEN_VEXT_VADC_VVM(vsbc_vvm_w, uint32_t, H4, DO_VSBC, clearl)
-GEN_VEXT_VADC_VVM(vsbc_vvm_d, uint64_t, H8, DO_VSBC, clearq)
+GEN_VEXT_VADC_VVM(vsbc_vvm_b, uint8_t, H1, DO_VSBC)
+GEN_VEXT_VADC_VVM(vsbc_vvm_h, uint16_t, H2, DO_VSBC)
+GEN_VEXT_VADC_VVM(vsbc_vvm_w, uint32_t, H4, DO_VSBC)
+GEN_VEXT_VADC_VVM(vsbc_vvm_d, uint64_t, H8, DO_VSBC)
-#define GEN_VEXT_VADC_VXM(NAME, ETYPE, H, DO_OP, CLEAR_FN) \
+#define GEN_VEXT_VADC_VXM(NAME, ETYPE, H, DO_OP) \
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
uint32_t vl = env->vl; \
- uint32_t esz = sizeof(ETYPE); \
- uint32_t vlmax = vext_maxsz(desc) / esz; \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
@@ -1218,18 +1128,17 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
\
*((ETYPE *)vd + H(i)) = DO_OP(s2, (ETYPE)(target_long)s1, carry);\
} \
- CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
}
-GEN_VEXT_VADC_VXM(vadc_vxm_b, uint8_t, H1, DO_VADC, clearb)
-GEN_VEXT_VADC_VXM(vadc_vxm_h, uint16_t, H2, DO_VADC, clearh)
-GEN_VEXT_VADC_VXM(vadc_vxm_w, uint32_t, H4, DO_VADC, clearl)
-GEN_VEXT_VADC_VXM(vadc_vxm_d, uint64_t, H8, DO_VADC, clearq)
+GEN_VEXT_VADC_VXM(vadc_vxm_b, uint8_t, H1, DO_VADC)
+GEN_VEXT_VADC_VXM(vadc_vxm_h, uint16_t, H2, DO_VADC)
+GEN_VEXT_VADC_VXM(vadc_vxm_w, uint32_t, H4, DO_VADC)
+GEN_VEXT_VADC_VXM(vadc_vxm_d, uint64_t, H8, DO_VADC)
-GEN_VEXT_VADC_VXM(vsbc_vxm_b, uint8_t, H1, DO_VSBC, clearb)
-GEN_VEXT_VADC_VXM(vsbc_vxm_h, uint16_t, H2, DO_VSBC, clearh)
-GEN_VEXT_VADC_VXM(vsbc_vxm_w, uint32_t, H4, DO_VSBC, clearl)
-GEN_VEXT_VADC_VXM(vsbc_vxm_d, uint64_t, H8, DO_VSBC, clearq)
+GEN_VEXT_VADC_VXM(vsbc_vxm_b, uint8_t, H1, DO_VSBC)
+GEN_VEXT_VADC_VXM(vsbc_vxm_h, uint16_t, H2, DO_VSBC)
+GEN_VEXT_VADC_VXM(vsbc_vxm_w, uint32_t, H4, DO_VSBC)
+GEN_VEXT_VADC_VXM(vsbc_vxm_d, uint64_t, H8, DO_VSBC)
#define DO_MADC(N, M, C) (C ? (__typeof(N))(N + M + 1) <= N : \
(__typeof(N))(N + M) < N)
@@ -1308,18 +1217,18 @@ RVVCALL(OPIVV2, vxor_vv_b, OP_SSS_B, H1, H1, H1, DO_XOR)
RVVCALL(OPIVV2, vxor_vv_h, OP_SSS_H, H2, H2, H2, DO_XOR)
RVVCALL(OPIVV2, vxor_vv_w, OP_SSS_W, H4, H4, H4, DO_XOR)
RVVCALL(OPIVV2, vxor_vv_d, OP_SSS_D, H8, H8, H8, DO_XOR)
-GEN_VEXT_VV(vand_vv_b, 1, 1, clearb)
-GEN_VEXT_VV(vand_vv_h, 2, 2, clearh)
-GEN_VEXT_VV(vand_vv_w, 4, 4, clearl)
-GEN_VEXT_VV(vand_vv_d, 8, 8, clearq)
-GEN_VEXT_VV(vor_vv_b, 1, 1, clearb)
-GEN_VEXT_VV(vor_vv_h, 2, 2, clearh)
-GEN_VEXT_VV(vor_vv_w, 4, 4, clearl)
-GEN_VEXT_VV(vor_vv_d, 8, 8, clearq)
-GEN_VEXT_VV(vxor_vv_b, 1, 1, clearb)
-GEN_VEXT_VV(vxor_vv_h, 2, 2, clearh)
-GEN_VEXT_VV(vxor_vv_w, 4, 4, clearl)
-GEN_VEXT_VV(vxor_vv_d, 8, 8, clearq)
+GEN_VEXT_VV(vand_vv_b, 1, 1)
+GEN_VEXT_VV(vand_vv_h, 2, 2)
+GEN_VEXT_VV(vand_vv_w, 4, 4)
+GEN_VEXT_VV(vand_vv_d, 8, 8)
+GEN_VEXT_VV(vor_vv_b, 1, 1)
+GEN_VEXT_VV(vor_vv_h, 2, 2)
+GEN_VEXT_VV(vor_vv_w, 4, 4)
+GEN_VEXT_VV(vor_vv_d, 8, 8)
+GEN_VEXT_VV(vxor_vv_b, 1, 1)
+GEN_VEXT_VV(vxor_vv_h, 2, 2)
+GEN_VEXT_VV(vxor_vv_w, 4, 4)
+GEN_VEXT_VV(vxor_vv_d, 8, 8)
RVVCALL(OPIVX2, vand_vx_b, OP_SSS_B, H1, H1, DO_AND)
RVVCALL(OPIVX2, vand_vx_h, OP_SSS_H, H2, H2, DO_AND)
@@ -1333,32 +1242,30 @@ RVVCALL(OPIVX2, vxor_vx_b, OP_SSS_B, H1, H1, DO_XOR)
RVVCALL(OPIVX2, vxor_vx_h, OP_SSS_H, H2, H2, DO_XOR)
RVVCALL(OPIVX2, vxor_vx_w, OP_SSS_W, H4, H4, DO_XOR)
RVVCALL(OPIVX2, vxor_vx_d, OP_SSS_D, H8, H8, DO_XOR)
-GEN_VEXT_VX(vand_vx_b, 1, 1, clearb)
-GEN_VEXT_VX(vand_vx_h, 2, 2, clearh)
-GEN_VEXT_VX(vand_vx_w, 4, 4, clearl)
-GEN_VEXT_VX(vand_vx_d, 8, 8, clearq)
-GEN_VEXT_VX(vor_vx_b, 1, 1, clearb)
-GEN_VEXT_VX(vor_vx_h, 2, 2, clearh)
-GEN_VEXT_VX(vor_vx_w, 4, 4, clearl)
-GEN_VEXT_VX(vor_vx_d, 8, 8, clearq)
-GEN_VEXT_VX(vxor_vx_b, 1, 1, clearb)
-GEN_VEXT_VX(vxor_vx_h, 2, 2, clearh)
-GEN_VEXT_VX(vxor_vx_w, 4, 4, clearl)
-GEN_VEXT_VX(vxor_vx_d, 8, 8, clearq)
+GEN_VEXT_VX(vand_vx_b, 1, 1)
+GEN_VEXT_VX(vand_vx_h, 2, 2)
+GEN_VEXT_VX(vand_vx_w, 4, 4)
+GEN_VEXT_VX(vand_vx_d, 8, 8)
+GEN_VEXT_VX(vor_vx_b, 1, 1)
+GEN_VEXT_VX(vor_vx_h, 2, 2)
+GEN_VEXT_VX(vor_vx_w, 4, 4)
+GEN_VEXT_VX(vor_vx_d, 8, 8)
+GEN_VEXT_VX(vxor_vx_b, 1, 1)
+GEN_VEXT_VX(vxor_vx_h, 2, 2)
+GEN_VEXT_VX(vxor_vx_w, 4, 4)
+GEN_VEXT_VX(vxor_vx_d, 8, 8)
/* Vector Single-Width Bit Shift Instructions */
#define DO_SLL(N, M) (N << (M))
#define DO_SRL(N, M) (N >> (M))
/* generate the helpers for shift instructions with two vector operators */
-#define GEN_VEXT_SHIFT_VV(NAME, TS1, TS2, HS1, HS2, OP, MASK, CLEAR_FN) \
+#define GEN_VEXT_SHIFT_VV(NAME, TS1, TS2, HS1, HS2, OP, MASK) \
void HELPER(NAME)(void *vd, void *v0, void *vs1, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
- uint32_t esz = sizeof(TS1); \
- uint32_t vlmax = vext_maxsz(desc) / esz; \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
@@ -1369,73 +1276,69 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
*((TS1 *)vd + HS1(i)) = OP(s2, s1 & MASK); \
} \
- CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
}
-GEN_VEXT_SHIFT_VV(vsll_vv_b, uint8_t, uint8_t, H1, H1, DO_SLL, 0x7, clearb)
-GEN_VEXT_SHIFT_VV(vsll_vv_h, uint16_t, uint16_t, H2, H2, DO_SLL, 0xf, clearh)
-GEN_VEXT_SHIFT_VV(vsll_vv_w, uint32_t, uint32_t, H4, H4, DO_SLL, 0x1f, clearl)
-GEN_VEXT_SHIFT_VV(vsll_vv_d, uint64_t, uint64_t, H8, H8, DO_SLL, 0x3f, clearq)
+GEN_VEXT_SHIFT_VV(vsll_vv_b, uint8_t, uint8_t, H1, H1, DO_SLL, 0x7)
+GEN_VEXT_SHIFT_VV(vsll_vv_h, uint16_t, uint16_t, H2, H2, DO_SLL, 0xf)
+GEN_VEXT_SHIFT_VV(vsll_vv_w, uint32_t, uint32_t, H4, H4, DO_SLL, 0x1f)
+GEN_VEXT_SHIFT_VV(vsll_vv_d, uint64_t, uint64_t, H8, H8, DO_SLL, 0x3f)
-GEN_VEXT_SHIFT_VV(vsrl_vv_b, uint8_t, uint8_t, H1, H1, DO_SRL, 0x7, clearb)
-GEN_VEXT_SHIFT_VV(vsrl_vv_h, uint16_t, uint16_t, H2, H2, DO_SRL, 0xf, clearh)
-GEN_VEXT_SHIFT_VV(vsrl_vv_w, uint32_t, uint32_t, H4, H4, DO_SRL, 0x1f, clearl)
-GEN_VEXT_SHIFT_VV(vsrl_vv_d, uint64_t, uint64_t, H8, H8, DO_SRL, 0x3f, clearq)
+GEN_VEXT_SHIFT_VV(vsrl_vv_b, uint8_t, uint8_t, H1, H1, DO_SRL, 0x7)
+GEN_VEXT_SHIFT_VV(vsrl_vv_h, uint16_t, uint16_t, H2, H2, DO_SRL, 0xf)
+GEN_VEXT_SHIFT_VV(vsrl_vv_w, uint32_t, uint32_t, H4, H4, DO_SRL, 0x1f)
+GEN_VEXT_SHIFT_VV(vsrl_vv_d, uint64_t, uint64_t, H8, H8, DO_SRL, 0x3f)
-GEN_VEXT_SHIFT_VV(vsra_vv_b, uint8_t, int8_t, H1, H1, DO_SRL, 0x7, clearb)
-GEN_VEXT_SHIFT_VV(vsra_vv_h, uint16_t, int16_t, H2, H2, DO_SRL, 0xf, clearh)
-GEN_VEXT_SHIFT_VV(vsra_vv_w, uint32_t, int32_t, H4, H4, DO_SRL, 0x1f, clearl)
-GEN_VEXT_SHIFT_VV(vsra_vv_d, uint64_t, int64_t, H8, H8, DO_SRL, 0x3f, clearq)
+GEN_VEXT_SHIFT_VV(vsra_vv_b, uint8_t, int8_t, H1, H1, DO_SRL, 0x7)
+GEN_VEXT_SHIFT_VV(vsra_vv_h, uint16_t, int16_t, H2, H2, DO_SRL, 0xf)
+GEN_VEXT_SHIFT_VV(vsra_vv_w, uint32_t, int32_t, H4, H4, DO_SRL, 0x1f)
+GEN_VEXT_SHIFT_VV(vsra_vv_d, uint64_t, int64_t, H8, H8, DO_SRL, 0x3f)
/* generate the helpers for shift instructions with one vector and one scalar */
-#define GEN_VEXT_SHIFT_VX(NAME, TD, TS2, HD, HS2, OP, MASK, CLEAR_FN) \
-void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
- void *vs2, CPURISCVState *env, uint32_t desc) \
-{ \
- uint32_t vm = vext_vm(desc); \
- uint32_t vl = env->vl; \
- uint32_t esz = sizeof(TD); \
- uint32_t vlmax = vext_maxsz(desc) / esz; \
- uint32_t i; \
- \
- for (i = 0; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, i)) { \
- continue; \
- } \
- TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
- *((TD *)vd + HD(i)) = OP(s2, s1 & MASK); \
- } \
- CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
-}
-
-GEN_VEXT_SHIFT_VX(vsll_vx_b, uint8_t, int8_t, H1, H1, DO_SLL, 0x7, clearb)
-GEN_VEXT_SHIFT_VX(vsll_vx_h, uint16_t, int16_t, H2, H2, DO_SLL, 0xf, clearh)
-GEN_VEXT_SHIFT_VX(vsll_vx_w, uint32_t, int32_t, H4, H4, DO_SLL, 0x1f, clearl)
-GEN_VEXT_SHIFT_VX(vsll_vx_d, uint64_t, int64_t, H8, H8, DO_SLL, 0x3f, clearq)
-
-GEN_VEXT_SHIFT_VX(vsrl_vx_b, uint8_t, uint8_t, H1, H1, DO_SRL, 0x7, clearb)
-GEN_VEXT_SHIFT_VX(vsrl_vx_h, uint16_t, uint16_t, H2, H2, DO_SRL, 0xf, clearh)
-GEN_VEXT_SHIFT_VX(vsrl_vx_w, uint32_t, uint32_t, H4, H4, DO_SRL, 0x1f, clearl)
-GEN_VEXT_SHIFT_VX(vsrl_vx_d, uint64_t, uint64_t, H8, H8, DO_SRL, 0x3f, clearq)
-
-GEN_VEXT_SHIFT_VX(vsra_vx_b, int8_t, int8_t, H1, H1, DO_SRL, 0x7, clearb)
-GEN_VEXT_SHIFT_VX(vsra_vx_h, int16_t, int16_t, H2, H2, DO_SRL, 0xf, clearh)
-GEN_VEXT_SHIFT_VX(vsra_vx_w, int32_t, int32_t, H4, H4, DO_SRL, 0x1f, clearl)
-GEN_VEXT_SHIFT_VX(vsra_vx_d, int64_t, int64_t, H8, H8, DO_SRL, 0x3f, clearq)
+#define GEN_VEXT_SHIFT_VX(NAME, TD, TS2, HD, HS2, OP, MASK) \
+void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
+ void *vs2, CPURISCVState *env, uint32_t desc) \
+{ \
+ uint32_t vm = vext_vm(desc); \
+ uint32_t vl = env->vl; \
+ uint32_t i; \
+ \
+ for (i = 0; i < vl; i++) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
+ continue; \
+ } \
+ TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
+ *((TD *)vd + HD(i)) = OP(s2, s1 & MASK); \
+ } \
+}
+
+GEN_VEXT_SHIFT_VX(vsll_vx_b, uint8_t, int8_t, H1, H1, DO_SLL, 0x7)
+GEN_VEXT_SHIFT_VX(vsll_vx_h, uint16_t, int16_t, H2, H2, DO_SLL, 0xf)
+GEN_VEXT_SHIFT_VX(vsll_vx_w, uint32_t, int32_t, H4, H4, DO_SLL, 0x1f)
+GEN_VEXT_SHIFT_VX(vsll_vx_d, uint64_t, int64_t, H8, H8, DO_SLL, 0x3f)
+
+GEN_VEXT_SHIFT_VX(vsrl_vx_b, uint8_t, uint8_t, H1, H1, DO_SRL, 0x7)
+GEN_VEXT_SHIFT_VX(vsrl_vx_h, uint16_t, uint16_t, H2, H2, DO_SRL, 0xf)
+GEN_VEXT_SHIFT_VX(vsrl_vx_w, uint32_t, uint32_t, H4, H4, DO_SRL, 0x1f)
+GEN_VEXT_SHIFT_VX(vsrl_vx_d, uint64_t, uint64_t, H8, H8, DO_SRL, 0x3f)
+
+GEN_VEXT_SHIFT_VX(vsra_vx_b, int8_t, int8_t, H1, H1, DO_SRL, 0x7)
+GEN_VEXT_SHIFT_VX(vsra_vx_h, int16_t, int16_t, H2, H2, DO_SRL, 0xf)
+GEN_VEXT_SHIFT_VX(vsra_vx_w, int32_t, int32_t, H4, H4, DO_SRL, 0x1f)
+GEN_VEXT_SHIFT_VX(vsra_vx_d, int64_t, int64_t, H8, H8, DO_SRL, 0x3f)
/* Vector Narrowing Integer Right Shift Instructions */
-GEN_VEXT_SHIFT_VV(vnsrl_vv_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf, clearb)
-GEN_VEXT_SHIFT_VV(vnsrl_vv_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f, clearh)
-GEN_VEXT_SHIFT_VV(vnsrl_vv_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f, clearl)
-GEN_VEXT_SHIFT_VV(vnsra_vv_b, uint8_t, int16_t, H1, H2, DO_SRL, 0xf, clearb)
-GEN_VEXT_SHIFT_VV(vnsra_vv_h, uint16_t, int32_t, H2, H4, DO_SRL, 0x1f, clearh)
-GEN_VEXT_SHIFT_VV(vnsra_vv_w, uint32_t, int64_t, H4, H8, DO_SRL, 0x3f, clearl)
-GEN_VEXT_SHIFT_VX(vnsrl_vx_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf, clearb)
-GEN_VEXT_SHIFT_VX(vnsrl_vx_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f, clearh)
-GEN_VEXT_SHIFT_VX(vnsrl_vx_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f, clearl)
-GEN_VEXT_SHIFT_VX(vnsra_vx_b, int8_t, int16_t, H1, H2, DO_SRL, 0xf, clearb)
-GEN_VEXT_SHIFT_VX(vnsra_vx_h, int16_t, int32_t, H2, H4, DO_SRL, 0x1f, clearh)
-GEN_VEXT_SHIFT_VX(vnsra_vx_w, int32_t, int64_t, H4, H8, DO_SRL, 0x3f, clearl)
+GEN_VEXT_SHIFT_VV(vnsrl_vv_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf)
+GEN_VEXT_SHIFT_VV(vnsrl_vv_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f)
+GEN_VEXT_SHIFT_VV(vnsrl_vv_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f)
+GEN_VEXT_SHIFT_VV(vnsra_vv_b, uint8_t, int16_t, H1, H2, DO_SRL, 0xf)
+GEN_VEXT_SHIFT_VV(vnsra_vv_h, uint16_t, int32_t, H2, H4, DO_SRL, 0x1f)
+GEN_VEXT_SHIFT_VV(vnsra_vv_w, uint32_t, int64_t, H4, H8, DO_SRL, 0x3f)
+GEN_VEXT_SHIFT_VX(vnsrl_vx_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf)
+GEN_VEXT_SHIFT_VX(vnsrl_vx_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f)
+GEN_VEXT_SHIFT_VX(vnsrl_vx_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f)
+GEN_VEXT_SHIFT_VX(vnsra_vx_b, int8_t, int16_t, H1, H2, DO_SRL, 0xf)
+GEN_VEXT_SHIFT_VX(vnsra_vx_h, int16_t, int32_t, H2, H4, DO_SRL, 0x1f)
+GEN_VEXT_SHIFT_VX(vnsra_vx_w, int32_t, int64_t, H4, H8, DO_SRL, 0x3f)
/* Vector Integer Comparison Instructions */
#define DO_MSEQ(N, M) (N == M)
@@ -1575,22 +1478,22 @@ RVVCALL(OPIVV2, vmax_vv_b, OP_SSS_B, H1, H1, H1, DO_MAX)
RVVCALL(OPIVV2, vmax_vv_h, OP_SSS_H, H2, H2, H2, DO_MAX)
RVVCALL(OPIVV2, vmax_vv_w, OP_SSS_W, H4, H4, H4, DO_MAX)
RVVCALL(OPIVV2, vmax_vv_d, OP_SSS_D, H8, H8, H8, DO_MAX)
-GEN_VEXT_VV(vminu_vv_b, 1, 1, clearb)
-GEN_VEXT_VV(vminu_vv_h, 2, 2, clearh)
-GEN_VEXT_VV(vminu_vv_w, 4, 4, clearl)
-GEN_VEXT_VV(vminu_vv_d, 8, 8, clearq)
-GEN_VEXT_VV(vmin_vv_b, 1, 1, clearb)
-GEN_VEXT_VV(vmin_vv_h, 2, 2, clearh)
-GEN_VEXT_VV(vmin_vv_w, 4, 4, clearl)
-GEN_VEXT_VV(vmin_vv_d, 8, 8, clearq)
-GEN_VEXT_VV(vmaxu_vv_b, 1, 1, clearb)
-GEN_VEXT_VV(vmaxu_vv_h, 2, 2, clearh)
-GEN_VEXT_VV(vmaxu_vv_w, 4, 4, clearl)
-GEN_VEXT_VV(vmaxu_vv_d, 8, 8, clearq)
-GEN_VEXT_VV(vmax_vv_b, 1, 1, clearb)
-GEN_VEXT_VV(vmax_vv_h, 2, 2, clearh)
-GEN_VEXT_VV(vmax_vv_w, 4, 4, clearl)
-GEN_VEXT_VV(vmax_vv_d, 8, 8, clearq)
+GEN_VEXT_VV(vminu_vv_b, 1, 1)
+GEN_VEXT_VV(vminu_vv_h, 2, 2)
+GEN_VEXT_VV(vminu_vv_w, 4, 4)
+GEN_VEXT_VV(vminu_vv_d, 8, 8)
+GEN_VEXT_VV(vmin_vv_b, 1, 1)
+GEN_VEXT_VV(vmin_vv_h, 2, 2)
+GEN_VEXT_VV(vmin_vv_w, 4, 4)
+GEN_VEXT_VV(vmin_vv_d, 8, 8)
+GEN_VEXT_VV(vmaxu_vv_b, 1, 1)
+GEN_VEXT_VV(vmaxu_vv_h, 2, 2)
+GEN_VEXT_VV(vmaxu_vv_w, 4, 4)
+GEN_VEXT_VV(vmaxu_vv_d, 8, 8)
+GEN_VEXT_VV(vmax_vv_b, 1, 1)
+GEN_VEXT_VV(vmax_vv_h, 2, 2)
+GEN_VEXT_VV(vmax_vv_w, 4, 4)
+GEN_VEXT_VV(vmax_vv_d, 8, 8)
RVVCALL(OPIVX2, vminu_vx_b, OP_UUU_B, H1, H1, DO_MIN)
RVVCALL(OPIVX2, vminu_vx_h, OP_UUU_H, H2, H2, DO_MIN)
@@ -1608,22 +1511,22 @@ RVVCALL(OPIVX2, vmax_vx_b, OP_SSS_B, H1, H1, DO_MAX)
RVVCALL(OPIVX2, vmax_vx_h, OP_SSS_H, H2, H2, DO_MAX)
RVVCALL(OPIVX2, vmax_vx_w, OP_SSS_W, H4, H4, DO_MAX)
RVVCALL(OPIVX2, vmax_vx_d, OP_SSS_D, H8, H8, DO_MAX)
-GEN_VEXT_VX(vminu_vx_b, 1, 1, clearb)
-GEN_VEXT_VX(vminu_vx_h, 2, 2, clearh)
-GEN_VEXT_VX(vminu_vx_w, 4, 4, clearl)
-GEN_VEXT_VX(vminu_vx_d, 8, 8, clearq)
-GEN_VEXT_VX(vmin_vx_b, 1, 1, clearb)
-GEN_VEXT_VX(vmin_vx_h, 2, 2, clearh)
-GEN_VEXT_VX(vmin_vx_w, 4, 4, clearl)
-GEN_VEXT_VX(vmin_vx_d, 8, 8, clearq)
-GEN_VEXT_VX(vmaxu_vx_b, 1, 1, clearb)
-GEN_VEXT_VX(vmaxu_vx_h, 2, 2, clearh)
-GEN_VEXT_VX(vmaxu_vx_w, 4, 4, clearl)
-GEN_VEXT_VX(vmaxu_vx_d, 8, 8, clearq)
-GEN_VEXT_VX(vmax_vx_b, 1, 1, clearb)
-GEN_VEXT_VX(vmax_vx_h, 2, 2, clearh)
-GEN_VEXT_VX(vmax_vx_w, 4, 4, clearl)
-GEN_VEXT_VX(vmax_vx_d, 8, 8, clearq)
+GEN_VEXT_VX(vminu_vx_b, 1, 1)
+GEN_VEXT_VX(vminu_vx_h, 2, 2)
+GEN_VEXT_VX(vminu_vx_w, 4, 4)
+GEN_VEXT_VX(vminu_vx_d, 8, 8)
+GEN_VEXT_VX(vmin_vx_b, 1, 1)
+GEN_VEXT_VX(vmin_vx_h, 2, 2)
+GEN_VEXT_VX(vmin_vx_w, 4, 4)
+GEN_VEXT_VX(vmin_vx_d, 8, 8)
+GEN_VEXT_VX(vmaxu_vx_b, 1, 1)
+GEN_VEXT_VX(vmaxu_vx_h, 2, 2)
+GEN_VEXT_VX(vmaxu_vx_w, 4, 4)
+GEN_VEXT_VX(vmaxu_vx_d, 8, 8)
+GEN_VEXT_VX(vmax_vx_b, 1, 1)
+GEN_VEXT_VX(vmax_vx_h, 2, 2)
+GEN_VEXT_VX(vmax_vx_w, 4, 4)
+GEN_VEXT_VX(vmax_vx_d, 8, 8)
/* Vector Single-Width Integer Multiply Instructions */
#define DO_MUL(N, M) (N * M)
@@ -1631,10 +1534,10 @@ RVVCALL(OPIVV2, vmul_vv_b, OP_SSS_B, H1, H1, H1, DO_MUL)
RVVCALL(OPIVV2, vmul_vv_h, OP_SSS_H, H2, H2, H2, DO_MUL)
RVVCALL(OPIVV2, vmul_vv_w, OP_SSS_W, H4, H4, H4, DO_MUL)
RVVCALL(OPIVV2, vmul_vv_d, OP_SSS_D, H8, H8, H8, DO_MUL)
-GEN_VEXT_VV(vmul_vv_b, 1, 1, clearb)
-GEN_VEXT_VV(vmul_vv_h, 2, 2, clearh)
-GEN_VEXT_VV(vmul_vv_w, 4, 4, clearl)
-GEN_VEXT_VV(vmul_vv_d, 8, 8, clearq)
+GEN_VEXT_VV(vmul_vv_b, 1, 1)
+GEN_VEXT_VV(vmul_vv_h, 2, 2)
+GEN_VEXT_VV(vmul_vv_w, 4, 4)
+GEN_VEXT_VV(vmul_vv_d, 8, 8)
static int8_t do_mulh_b(int8_t s2, int8_t s1)
{
@@ -1738,18 +1641,18 @@ RVVCALL(OPIVV2, vmulhsu_vv_b, OP_SUS_B, H1, H1, H1, do_mulhsu_b)
RVVCALL(OPIVV2, vmulhsu_vv_h, OP_SUS_H, H2, H2, H2, do_mulhsu_h)
RVVCALL(OPIVV2, vmulhsu_vv_w, OP_SUS_W, H4, H4, H4, do_mulhsu_w)
RVVCALL(OPIVV2, vmulhsu_vv_d, OP_SUS_D, H8, H8, H8, do_mulhsu_d)
-GEN_VEXT_VV(vmulh_vv_b, 1, 1, clearb)
-GEN_VEXT_VV(vmulh_vv_h, 2, 2, clearh)
-GEN_VEXT_VV(vmulh_vv_w, 4, 4, clearl)
-GEN_VEXT_VV(vmulh_vv_d, 8, 8, clearq)
-GEN_VEXT_VV(vmulhu_vv_b, 1, 1, clearb)
-GEN_VEXT_VV(vmulhu_vv_h, 2, 2, clearh)
-GEN_VEXT_VV(vmulhu_vv_w, 4, 4, clearl)
-GEN_VEXT_VV(vmulhu_vv_d, 8, 8, clearq)
-GEN_VEXT_VV(vmulhsu_vv_b, 1, 1, clearb)
-GEN_VEXT_VV(vmulhsu_vv_h, 2, 2, clearh)
-GEN_VEXT_VV(vmulhsu_vv_w, 4, 4, clearl)
-GEN_VEXT_VV(vmulhsu_vv_d, 8, 8, clearq)
+GEN_VEXT_VV(vmulh_vv_b, 1, 1)
+GEN_VEXT_VV(vmulh_vv_h, 2, 2)
+GEN_VEXT_VV(vmulh_vv_w, 4, 4)
+GEN_VEXT_VV(vmulh_vv_d, 8, 8)
+GEN_VEXT_VV(vmulhu_vv_b, 1, 1)
+GEN_VEXT_VV(vmulhu_vv_h, 2, 2)
+GEN_VEXT_VV(vmulhu_vv_w, 4, 4)
+GEN_VEXT_VV(vmulhu_vv_d, 8, 8)
+GEN_VEXT_VV(vmulhsu_vv_b, 1, 1)
+GEN_VEXT_VV(vmulhsu_vv_h, 2, 2)
+GEN_VEXT_VV(vmulhsu_vv_w, 4, 4)
+GEN_VEXT_VV(vmulhsu_vv_d, 8, 8)
RVVCALL(OPIVX2, vmul_vx_b, OP_SSS_B, H1, H1, DO_MUL)
RVVCALL(OPIVX2, vmul_vx_h, OP_SSS_H, H2, H2, DO_MUL)
@@ -1767,22 +1670,22 @@ RVVCALL(OPIVX2, vmulhsu_vx_b, OP_SUS_B, H1, H1, do_mulhsu_b)
RVVCALL(OPIVX2, vmulhsu_vx_h, OP_SUS_H, H2, H2, do_mulhsu_h)
RVVCALL(OPIVX2, vmulhsu_vx_w, OP_SUS_W, H4, H4, do_mulhsu_w)
RVVCALL(OPIVX2, vmulhsu_vx_d, OP_SUS_D, H8, H8, do_mulhsu_d)
-GEN_VEXT_VX(vmul_vx_b, 1, 1, clearb)
-GEN_VEXT_VX(vmul_vx_h, 2, 2, clearh)
-GEN_VEXT_VX(vmul_vx_w, 4, 4, clearl)
-GEN_VEXT_VX(vmul_vx_d, 8, 8, clearq)
-GEN_VEXT_VX(vmulh_vx_b, 1, 1, clearb)
-GEN_VEXT_VX(vmulh_vx_h, 2, 2, clearh)
-GEN_VEXT_VX(vmulh_vx_w, 4, 4, clearl)
-GEN_VEXT_VX(vmulh_vx_d, 8, 8, clearq)
-GEN_VEXT_VX(vmulhu_vx_b, 1, 1, clearb)
-GEN_VEXT_VX(vmulhu_vx_h, 2, 2, clearh)
-GEN_VEXT_VX(vmulhu_vx_w, 4, 4, clearl)
-GEN_VEXT_VX(vmulhu_vx_d, 8, 8, clearq)
-GEN_VEXT_VX(vmulhsu_vx_b, 1, 1, clearb)
-GEN_VEXT_VX(vmulhsu_vx_h, 2, 2, clearh)
-GEN_VEXT_VX(vmulhsu_vx_w, 4, 4, clearl)
-GEN_VEXT_VX(vmulhsu_vx_d, 8, 8, clearq)
+GEN_VEXT_VX(vmul_vx_b, 1, 1)
+GEN_VEXT_VX(vmul_vx_h, 2, 2)
+GEN_VEXT_VX(vmul_vx_w, 4, 4)
+GEN_VEXT_VX(vmul_vx_d, 8, 8)
+GEN_VEXT_VX(vmulh_vx_b, 1, 1)
+GEN_VEXT_VX(vmulh_vx_h, 2, 2)
+GEN_VEXT_VX(vmulh_vx_w, 4, 4)
+GEN_VEXT_VX(vmulh_vx_d, 8, 8)
+GEN_VEXT_VX(vmulhu_vx_b, 1, 1)
+GEN_VEXT_VX(vmulhu_vx_h, 2, 2)
+GEN_VEXT_VX(vmulhu_vx_w, 4, 4)
+GEN_VEXT_VX(vmulhu_vx_d, 8, 8)
+GEN_VEXT_VX(vmulhsu_vx_b, 1, 1)
+GEN_VEXT_VX(vmulhsu_vx_h, 2, 2)
+GEN_VEXT_VX(vmulhsu_vx_w, 4, 4)
+GEN_VEXT_VX(vmulhsu_vx_d, 8, 8)
/* Vector Integer Divide Instructions */
#define DO_DIVU(N, M) (unlikely(M == 0) ? (__typeof(N))(-1) : N / M)
@@ -1808,22 +1711,22 @@ RVVCALL(OPIVV2, vrem_vv_b, OP_SSS_B, H1, H1, H1, DO_REM)
RVVCALL(OPIVV2, vrem_vv_h, OP_SSS_H, H2, H2, H2, DO_REM)
RVVCALL(OPIVV2, vrem_vv_w, OP_SSS_W, H4, H4, H4, DO_REM)
RVVCALL(OPIVV2, vrem_vv_d, OP_SSS_D, H8, H8, H8, DO_REM)
-GEN_VEXT_VV(vdivu_vv_b, 1, 1, clearb)
-GEN_VEXT_VV(vdivu_vv_h, 2, 2, clearh)
-GEN_VEXT_VV(vdivu_vv_w, 4, 4, clearl)
-GEN_VEXT_VV(vdivu_vv_d, 8, 8, clearq)
-GEN_VEXT_VV(vdiv_vv_b, 1, 1, clearb)
-GEN_VEXT_VV(vdiv_vv_h, 2, 2, clearh)
-GEN_VEXT_VV(vdiv_vv_w, 4, 4, clearl)
-GEN_VEXT_VV(vdiv_vv_d, 8, 8, clearq)
-GEN_VEXT_VV(vremu_vv_b, 1, 1, clearb)
-GEN_VEXT_VV(vremu_vv_h, 2, 2, clearh)
-GEN_VEXT_VV(vremu_vv_w, 4, 4, clearl)
-GEN_VEXT_VV(vremu_vv_d, 8, 8, clearq)
-GEN_VEXT_VV(vrem_vv_b, 1, 1, clearb)
-GEN_VEXT_VV(vrem_vv_h, 2, 2, clearh)
-GEN_VEXT_VV(vrem_vv_w, 4, 4, clearl)
-GEN_VEXT_VV(vrem_vv_d, 8, 8, clearq)
+GEN_VEXT_VV(vdivu_vv_b, 1, 1)
+GEN_VEXT_VV(vdivu_vv_h, 2, 2)
+GEN_VEXT_VV(vdivu_vv_w, 4, 4)
+GEN_VEXT_VV(vdivu_vv_d, 8, 8)
+GEN_VEXT_VV(vdiv_vv_b, 1, 1)
+GEN_VEXT_VV(vdiv_vv_h, 2, 2)
+GEN_VEXT_VV(vdiv_vv_w, 4, 4)
+GEN_VEXT_VV(vdiv_vv_d, 8, 8)
+GEN_VEXT_VV(vremu_vv_b, 1, 1)
+GEN_VEXT_VV(vremu_vv_h, 2, 2)
+GEN_VEXT_VV(vremu_vv_w, 4, 4)
+GEN_VEXT_VV(vremu_vv_d, 8, 8)
+GEN_VEXT_VV(vrem_vv_b, 1, 1)
+GEN_VEXT_VV(vrem_vv_h, 2, 2)
+GEN_VEXT_VV(vrem_vv_w, 4, 4)
+GEN_VEXT_VV(vrem_vv_d, 8, 8)
RVVCALL(OPIVX2, vdivu_vx_b, OP_UUU_B, H1, H1, DO_DIVU)
RVVCALL(OPIVX2, vdivu_vx_h, OP_UUU_H, H2, H2, DO_DIVU)
@@ -1841,22 +1744,22 @@ RVVCALL(OPIVX2, vrem_vx_b, OP_SSS_B, H1, H1, DO_REM)
RVVCALL(OPIVX2, vrem_vx_h, OP_SSS_H, H2, H2, DO_REM)
RVVCALL(OPIVX2, vrem_vx_w, OP_SSS_W, H4, H4, DO_REM)
RVVCALL(OPIVX2, vrem_vx_d, OP_SSS_D, H8, H8, DO_REM)
-GEN_VEXT_VX(vdivu_vx_b, 1, 1, clearb)
-GEN_VEXT_VX(vdivu_vx_h, 2, 2, clearh)
-GEN_VEXT_VX(vdivu_vx_w, 4, 4, clearl)
-GEN_VEXT_VX(vdivu_vx_d, 8, 8, clearq)
-GEN_VEXT_VX(vdiv_vx_b, 1, 1, clearb)
-GEN_VEXT_VX(vdiv_vx_h, 2, 2, clearh)
-GEN_VEXT_VX(vdiv_vx_w, 4, 4, clearl)
-GEN_VEXT_VX(vdiv_vx_d, 8, 8, clearq)
-GEN_VEXT_VX(vremu_vx_b, 1, 1, clearb)
-GEN_VEXT_VX(vremu_vx_h, 2, 2, clearh)
-GEN_VEXT_VX(vremu_vx_w, 4, 4, clearl)
-GEN_VEXT_VX(vremu_vx_d, 8, 8, clearq)
-GEN_VEXT_VX(vrem_vx_b, 1, 1, clearb)
-GEN_VEXT_VX(vrem_vx_h, 2, 2, clearh)
-GEN_VEXT_VX(vrem_vx_w, 4, 4, clearl)
-GEN_VEXT_VX(vrem_vx_d, 8, 8, clearq)
+GEN_VEXT_VX(vdivu_vx_b, 1, 1)
+GEN_VEXT_VX(vdivu_vx_h, 2, 2)
+GEN_VEXT_VX(vdivu_vx_w, 4, 4)
+GEN_VEXT_VX(vdivu_vx_d, 8, 8)
+GEN_VEXT_VX(vdiv_vx_b, 1, 1)
+GEN_VEXT_VX(vdiv_vx_h, 2, 2)
+GEN_VEXT_VX(vdiv_vx_w, 4, 4)
+GEN_VEXT_VX(vdiv_vx_d, 8, 8)
+GEN_VEXT_VX(vremu_vx_b, 1, 1)
+GEN_VEXT_VX(vremu_vx_h, 2, 2)
+GEN_VEXT_VX(vremu_vx_w, 4, 4)
+GEN_VEXT_VX(vremu_vx_d, 8, 8)
+GEN_VEXT_VX(vrem_vx_b, 1, 1)
+GEN_VEXT_VX(vrem_vx_h, 2, 2)
+GEN_VEXT_VX(vrem_vx_w, 4, 4)
+GEN_VEXT_VX(vrem_vx_d, 8, 8)
/* Vector Widening Integer Multiply Instructions */
RVVCALL(OPIVV2, vwmul_vv_b, WOP_SSS_B, H2, H1, H1, DO_MUL)
@@ -1868,15 +1771,15 @@ RVVCALL(OPIVV2, vwmulu_vv_w, WOP_UUU_W, H8, H4, H4, DO_MUL)
RVVCALL(OPIVV2, vwmulsu_vv_b, WOP_SUS_B, H2, H1, H1, DO_MUL)
RVVCALL(OPIVV2, vwmulsu_vv_h, WOP_SUS_H, H4, H2, H2, DO_MUL)
RVVCALL(OPIVV2, vwmulsu_vv_w, WOP_SUS_W, H8, H4, H4, DO_MUL)
-GEN_VEXT_VV(vwmul_vv_b, 1, 2, clearh)
-GEN_VEXT_VV(vwmul_vv_h, 2, 4, clearl)
-GEN_VEXT_VV(vwmul_vv_w, 4, 8, clearq)
-GEN_VEXT_VV(vwmulu_vv_b, 1, 2, clearh)
-GEN_VEXT_VV(vwmulu_vv_h, 2, 4, clearl)
-GEN_VEXT_VV(vwmulu_vv_w, 4, 8, clearq)
-GEN_VEXT_VV(vwmulsu_vv_b, 1, 2, clearh)
-GEN_VEXT_VV(vwmulsu_vv_h, 2, 4, clearl)
-GEN_VEXT_VV(vwmulsu_vv_w, 4, 8, clearq)
+GEN_VEXT_VV(vwmul_vv_b, 1, 2)
+GEN_VEXT_VV(vwmul_vv_h, 2, 4)
+GEN_VEXT_VV(vwmul_vv_w, 4, 8)
+GEN_VEXT_VV(vwmulu_vv_b, 1, 2)
+GEN_VEXT_VV(vwmulu_vv_h, 2, 4)
+GEN_VEXT_VV(vwmulu_vv_w, 4, 8)
+GEN_VEXT_VV(vwmulsu_vv_b, 1, 2)
+GEN_VEXT_VV(vwmulsu_vv_h, 2, 4)
+GEN_VEXT_VV(vwmulsu_vv_w, 4, 8)
RVVCALL(OPIVX2, vwmul_vx_b, WOP_SSS_B, H2, H1, DO_MUL)
RVVCALL(OPIVX2, vwmul_vx_h, WOP_SSS_H, H4, H2, DO_MUL)
@@ -1887,15 +1790,15 @@ RVVCALL(OPIVX2, vwmulu_vx_w, WOP_UUU_W, H8, H4, DO_MUL)
RVVCALL(OPIVX2, vwmulsu_vx_b, WOP_SUS_B, H2, H1, DO_MUL)
RVVCALL(OPIVX2, vwmulsu_vx_h, WOP_SUS_H, H4, H2, DO_MUL)
RVVCALL(OPIVX2, vwmulsu_vx_w, WOP_SUS_W, H8, H4, DO_MUL)
-GEN_VEXT_VX(vwmul_vx_b, 1, 2, clearh)
-GEN_VEXT_VX(vwmul_vx_h, 2, 4, clearl)
-GEN_VEXT_VX(vwmul_vx_w, 4, 8, clearq)
-GEN_VEXT_VX(vwmulu_vx_b, 1, 2, clearh)
-GEN_VEXT_VX(vwmulu_vx_h, 2, 4, clearl)
-GEN_VEXT_VX(vwmulu_vx_w, 4, 8, clearq)
-GEN_VEXT_VX(vwmulsu_vx_b, 1, 2, clearh)
-GEN_VEXT_VX(vwmulsu_vx_h, 2, 4, clearl)
-GEN_VEXT_VX(vwmulsu_vx_w, 4, 8, clearq)
+GEN_VEXT_VX(vwmul_vx_b, 1, 2)
+GEN_VEXT_VX(vwmul_vx_h, 2, 4)
+GEN_VEXT_VX(vwmul_vx_w, 4, 8)
+GEN_VEXT_VX(vwmulu_vx_b, 1, 2)
+GEN_VEXT_VX(vwmulu_vx_h, 2, 4)
+GEN_VEXT_VX(vwmulu_vx_w, 4, 8)
+GEN_VEXT_VX(vwmulsu_vx_b, 1, 2)
+GEN_VEXT_VX(vwmulsu_vx_h, 2, 4)
+GEN_VEXT_VX(vwmulsu_vx_w, 4, 8)
/* Vector Single-Width Integer Multiply-Add Instructions */
#define OPIVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \
@@ -1927,22 +1830,22 @@ RVVCALL(OPIVV3, vnmsub_vv_b, OP_SSS_B, H1, H1, H1, DO_NMSUB)
RVVCALL(OPIVV3, vnmsub_vv_h, OP_SSS_H, H2, H2, H2, DO_NMSUB)
RVVCALL(OPIVV3, vnmsub_vv_w, OP_SSS_W, H4, H4, H4, DO_NMSUB)
RVVCALL(OPIVV3, vnmsub_vv_d, OP_SSS_D, H8, H8, H8, DO_NMSUB)
-GEN_VEXT_VV(vmacc_vv_b, 1, 1, clearb)
-GEN_VEXT_VV(vmacc_vv_h, 2, 2, clearh)
-GEN_VEXT_VV(vmacc_vv_w, 4, 4, clearl)
-GEN_VEXT_VV(vmacc_vv_d, 8, 8, clearq)
-GEN_VEXT_VV(vnmsac_vv_b, 1, 1, clearb)
-GEN_VEXT_VV(vnmsac_vv_h, 2, 2, clearh)
-GEN_VEXT_VV(vnmsac_vv_w, 4, 4, clearl)
-GEN_VEXT_VV(vnmsac_vv_d, 8, 8, clearq)
-GEN_VEXT_VV(vmadd_vv_b, 1, 1, clearb)
-GEN_VEXT_VV(vmadd_vv_h, 2, 2, clearh)
-GEN_VEXT_VV(vmadd_vv_w, 4, 4, clearl)
-GEN_VEXT_VV(vmadd_vv_d, 8, 8, clearq)
-GEN_VEXT_VV(vnmsub_vv_b, 1, 1, clearb)
-GEN_VEXT_VV(vnmsub_vv_h, 2, 2, clearh)
-GEN_VEXT_VV(vnmsub_vv_w, 4, 4, clearl)
-GEN_VEXT_VV(vnmsub_vv_d, 8, 8, clearq)
+GEN_VEXT_VV(vmacc_vv_b, 1, 1)
+GEN_VEXT_VV(vmacc_vv_h, 2, 2)
+GEN_VEXT_VV(vmacc_vv_w, 4, 4)
+GEN_VEXT_VV(vmacc_vv_d, 8, 8)
+GEN_VEXT_VV(vnmsac_vv_b, 1, 1)
+GEN_VEXT_VV(vnmsac_vv_h, 2, 2)
+GEN_VEXT_VV(vnmsac_vv_w, 4, 4)
+GEN_VEXT_VV(vnmsac_vv_d, 8, 8)
+GEN_VEXT_VV(vmadd_vv_b, 1, 1)
+GEN_VEXT_VV(vmadd_vv_h, 2, 2)
+GEN_VEXT_VV(vmadd_vv_w, 4, 4)
+GEN_VEXT_VV(vmadd_vv_d, 8, 8)
+GEN_VEXT_VV(vnmsub_vv_b, 1, 1)
+GEN_VEXT_VV(vnmsub_vv_h, 2, 2)
+GEN_VEXT_VV(vnmsub_vv_w, 4, 4)
+GEN_VEXT_VV(vnmsub_vv_d, 8, 8)
#define OPIVX3(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \
static void do_##NAME(void *vd, target_long s1, void *vs2, int i) \
@@ -1968,22 +1871,22 @@ RVVCALL(OPIVX3, vnmsub_vx_b, OP_SSS_B, H1, H1, DO_NMSUB)
RVVCALL(OPIVX3, vnmsub_vx_h, OP_SSS_H, H2, H2, DO_NMSUB)
RVVCALL(OPIVX3, vnmsub_vx_w, OP_SSS_W, H4, H4, DO_NMSUB)
RVVCALL(OPIVX3, vnmsub_vx_d, OP_SSS_D, H8, H8, DO_NMSUB)
-GEN_VEXT_VX(vmacc_vx_b, 1, 1, clearb)
-GEN_VEXT_VX(vmacc_vx_h, 2, 2, clearh)
-GEN_VEXT_VX(vmacc_vx_w, 4, 4, clearl)
-GEN_VEXT_VX(vmacc_vx_d, 8, 8, clearq)
-GEN_VEXT_VX(vnmsac_vx_b, 1, 1, clearb)
-GEN_VEXT_VX(vnmsac_vx_h, 2, 2, clearh)
-GEN_VEXT_VX(vnmsac_vx_w, 4, 4, clearl)
-GEN_VEXT_VX(vnmsac_vx_d, 8, 8, clearq)
-GEN_VEXT_VX(vmadd_vx_b, 1, 1, clearb)
-GEN_VEXT_VX(vmadd_vx_h, 2, 2, clearh)
-GEN_VEXT_VX(vmadd_vx_w, 4, 4, clearl)
-GEN_VEXT_VX(vmadd_vx_d, 8, 8, clearq)
-GEN_VEXT_VX(vnmsub_vx_b, 1, 1, clearb)
-GEN_VEXT_VX(vnmsub_vx_h, 2, 2, clearh)
-GEN_VEXT_VX(vnmsub_vx_w, 4, 4, clearl)
-GEN_VEXT_VX(vnmsub_vx_d, 8, 8, clearq)
+GEN_VEXT_VX(vmacc_vx_b, 1, 1)
+GEN_VEXT_VX(vmacc_vx_h, 2, 2)
+GEN_VEXT_VX(vmacc_vx_w, 4, 4)
+GEN_VEXT_VX(vmacc_vx_d, 8, 8)
+GEN_VEXT_VX(vnmsac_vx_b, 1, 1)
+GEN_VEXT_VX(vnmsac_vx_h, 2, 2)
+GEN_VEXT_VX(vnmsac_vx_w, 4, 4)
+GEN_VEXT_VX(vnmsac_vx_d, 8, 8)
+GEN_VEXT_VX(vmadd_vx_b, 1, 1)
+GEN_VEXT_VX(vmadd_vx_h, 2, 2)
+GEN_VEXT_VX(vmadd_vx_w, 4, 4)
+GEN_VEXT_VX(vmadd_vx_d, 8, 8)
+GEN_VEXT_VX(vnmsub_vx_b, 1, 1)
+GEN_VEXT_VX(vnmsub_vx_h, 2, 2)
+GEN_VEXT_VX(vnmsub_vx_w, 4, 4)
+GEN_VEXT_VX(vnmsub_vx_d, 8, 8)
/* Vector Widening Integer Multiply-Add Instructions */
RVVCALL(OPIVV3, vwmaccu_vv_b, WOP_UUU_B, H2, H1, H1, DO_MACC)
@@ -1995,15 +1898,15 @@ RVVCALL(OPIVV3, vwmacc_vv_w, WOP_SSS_W, H8, H4, H4, DO_MACC)
RVVCALL(OPIVV3, vwmaccsu_vv_b, WOP_SSU_B, H2, H1, H1, DO_MACC)
RVVCALL(OPIVV3, vwmaccsu_vv_h, WOP_SSU_H, H4, H2, H2, DO_MACC)
RVVCALL(OPIVV3, vwmaccsu_vv_w, WOP_SSU_W, H8, H4, H4, DO_MACC)
-GEN_VEXT_VV(vwmaccu_vv_b, 1, 2, clearh)
-GEN_VEXT_VV(vwmaccu_vv_h, 2, 4, clearl)
-GEN_VEXT_VV(vwmaccu_vv_w, 4, 8, clearq)
-GEN_VEXT_VV(vwmacc_vv_b, 1, 2, clearh)
-GEN_VEXT_VV(vwmacc_vv_h, 2, 4, clearl)
-GEN_VEXT_VV(vwmacc_vv_w, 4, 8, clearq)
-GEN_VEXT_VV(vwmaccsu_vv_b, 1, 2, clearh)
-GEN_VEXT_VV(vwmaccsu_vv_h, 2, 4, clearl)
-GEN_VEXT_VV(vwmaccsu_vv_w, 4, 8, clearq)
+GEN_VEXT_VV(vwmaccu_vv_b, 1, 2)
+GEN_VEXT_VV(vwmaccu_vv_h, 2, 4)
+GEN_VEXT_VV(vwmaccu_vv_w, 4, 8)
+GEN_VEXT_VV(vwmacc_vv_b, 1, 2)
+GEN_VEXT_VV(vwmacc_vv_h, 2, 4)
+GEN_VEXT_VV(vwmacc_vv_w, 4, 8)
+GEN_VEXT_VV(vwmaccsu_vv_b, 1, 2)
+GEN_VEXT_VV(vwmaccsu_vv_h, 2, 4)
+GEN_VEXT_VV(vwmaccsu_vv_w, 4, 8)
RVVCALL(OPIVX3, vwmaccu_vx_b, WOP_UUU_B, H2, H1, DO_MACC)
RVVCALL(OPIVX3, vwmaccu_vx_h, WOP_UUU_H, H4, H2, DO_MACC)
@@ -2017,89 +1920,78 @@ RVVCALL(OPIVX3, vwmaccsu_vx_w, WOP_SSU_W, H8, H4, DO_MACC)
RVVCALL(OPIVX3, vwmaccus_vx_b, WOP_SUS_B, H2, H1, DO_MACC)
RVVCALL(OPIVX3, vwmaccus_vx_h, WOP_SUS_H, H4, H2, DO_MACC)
RVVCALL(OPIVX3, vwmaccus_vx_w, WOP_SUS_W, H8, H4, DO_MACC)
-GEN_VEXT_VX(vwmaccu_vx_b, 1, 2, clearh)
-GEN_VEXT_VX(vwmaccu_vx_h, 2, 4, clearl)
-GEN_VEXT_VX(vwmaccu_vx_w, 4, 8, clearq)
-GEN_VEXT_VX(vwmacc_vx_b, 1, 2, clearh)
-GEN_VEXT_VX(vwmacc_vx_h, 2, 4, clearl)
-GEN_VEXT_VX(vwmacc_vx_w, 4, 8, clearq)
-GEN_VEXT_VX(vwmaccsu_vx_b, 1, 2, clearh)
-GEN_VEXT_VX(vwmaccsu_vx_h, 2, 4, clearl)
-GEN_VEXT_VX(vwmaccsu_vx_w, 4, 8, clearq)
-GEN_VEXT_VX(vwmaccus_vx_b, 1, 2, clearh)
-GEN_VEXT_VX(vwmaccus_vx_h, 2, 4, clearl)
-GEN_VEXT_VX(vwmaccus_vx_w, 4, 8, clearq)
+GEN_VEXT_VX(vwmaccu_vx_b, 1, 2)
+GEN_VEXT_VX(vwmaccu_vx_h, 2, 4)
+GEN_VEXT_VX(vwmaccu_vx_w, 4, 8)
+GEN_VEXT_VX(vwmacc_vx_b, 1, 2)
+GEN_VEXT_VX(vwmacc_vx_h, 2, 4)
+GEN_VEXT_VX(vwmacc_vx_w, 4, 8)
+GEN_VEXT_VX(vwmaccsu_vx_b, 1, 2)
+GEN_VEXT_VX(vwmaccsu_vx_h, 2, 4)
+GEN_VEXT_VX(vwmaccsu_vx_w, 4, 8)
+GEN_VEXT_VX(vwmaccus_vx_b, 1, 2)
+GEN_VEXT_VX(vwmaccus_vx_h, 2, 4)
+GEN_VEXT_VX(vwmaccus_vx_w, 4, 8)
/* Vector Integer Merge and Move Instructions */
-#define GEN_VEXT_VMV_VV(NAME, ETYPE, H, CLEAR_FN) \
+#define GEN_VEXT_VMV_VV(NAME, ETYPE, H) \
void HELPER(NAME)(void *vd, void *vs1, CPURISCVState *env, \
uint32_t desc) \
{ \
uint32_t vl = env->vl; \
- uint32_t esz = sizeof(ETYPE); \
- uint32_t vlmax = vext_maxsz(desc) / esz; \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
*((ETYPE *)vd + H(i)) = s1; \
} \
- CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
}
-GEN_VEXT_VMV_VV(vmv_v_v_b, int8_t, H1, clearb)
-GEN_VEXT_VMV_VV(vmv_v_v_h, int16_t, H2, clearh)
-GEN_VEXT_VMV_VV(vmv_v_v_w, int32_t, H4, clearl)
-GEN_VEXT_VMV_VV(vmv_v_v_d, int64_t, H8, clearq)
+GEN_VEXT_VMV_VV(vmv_v_v_b, int8_t, H1)
+GEN_VEXT_VMV_VV(vmv_v_v_h, int16_t, H2)
+GEN_VEXT_VMV_VV(vmv_v_v_w, int32_t, H4)
+GEN_VEXT_VMV_VV(vmv_v_v_d, int64_t, H8)
-#define GEN_VEXT_VMV_VX(NAME, ETYPE, H, CLEAR_FN) \
+#define GEN_VEXT_VMV_VX(NAME, ETYPE, H) \
void HELPER(NAME)(void *vd, uint64_t s1, CPURISCVState *env, \
uint32_t desc) \
{ \
uint32_t vl = env->vl; \
- uint32_t esz = sizeof(ETYPE); \
- uint32_t vlmax = vext_maxsz(desc) / esz; \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
*((ETYPE *)vd + H(i)) = (ETYPE)s1; \
} \
- CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
}
-GEN_VEXT_VMV_VX(vmv_v_x_b, int8_t, H1, clearb)
-GEN_VEXT_VMV_VX(vmv_v_x_h, int16_t, H2, clearh)
-GEN_VEXT_VMV_VX(vmv_v_x_w, int32_t, H4, clearl)
-GEN_VEXT_VMV_VX(vmv_v_x_d, int64_t, H8, clearq)
+GEN_VEXT_VMV_VX(vmv_v_x_b, int8_t, H1)
+GEN_VEXT_VMV_VX(vmv_v_x_h, int16_t, H2)
+GEN_VEXT_VMV_VX(vmv_v_x_w, int32_t, H4)
+GEN_VEXT_VMV_VX(vmv_v_x_d, int64_t, H8)
-#define GEN_VEXT_VMERGE_VV(NAME, ETYPE, H, CLEAR_FN) \
+#define GEN_VEXT_VMERGE_VV(NAME, ETYPE, H) \
void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
uint32_t vl = env->vl; \
- uint32_t esz = sizeof(ETYPE); \
- uint32_t vlmax = vext_maxsz(desc) / esz; \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
ETYPE *vt = (!vext_elem_mask(v0, i) ? vs2 : vs1); \
*((ETYPE *)vd + H(i)) = *(vt + H(i)); \
} \
- CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
}
-GEN_VEXT_VMERGE_VV(vmerge_vvm_b, int8_t, H1, clearb)
-GEN_VEXT_VMERGE_VV(vmerge_vvm_h, int16_t, H2, clearh)
-GEN_VEXT_VMERGE_VV(vmerge_vvm_w, int32_t, H4, clearl)
-GEN_VEXT_VMERGE_VV(vmerge_vvm_d, int64_t, H8, clearq)
+GEN_VEXT_VMERGE_VV(vmerge_vvm_b, int8_t, H1)
+GEN_VEXT_VMERGE_VV(vmerge_vvm_h, int16_t, H2)
+GEN_VEXT_VMERGE_VV(vmerge_vvm_w, int32_t, H4)
+GEN_VEXT_VMERGE_VV(vmerge_vvm_d, int64_t, H8)
-#define GEN_VEXT_VMERGE_VX(NAME, ETYPE, H, CLEAR_FN) \
+#define GEN_VEXT_VMERGE_VX(NAME, ETYPE, H) \
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
uint32_t vl = env->vl; \
- uint32_t esz = sizeof(ETYPE); \
- uint32_t vlmax = vext_maxsz(desc) / esz; \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
@@ -2108,13 +2000,12 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
(ETYPE)(target_long)s1); \
*((ETYPE *)vd + H(i)) = d; \
} \
- CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
}
-GEN_VEXT_VMERGE_VX(vmerge_vxm_b, int8_t, H1, clearb)
-GEN_VEXT_VMERGE_VX(vmerge_vxm_h, int16_t, H2, clearh)
-GEN_VEXT_VMERGE_VX(vmerge_vxm_w, int32_t, H4, clearl)
-GEN_VEXT_VMERGE_VX(vmerge_vxm_d, int64_t, H8, clearq)
+GEN_VEXT_VMERGE_VX(vmerge_vxm_b, int8_t, H1)
+GEN_VEXT_VMERGE_VX(vmerge_vxm_h, int16_t, H2)
+GEN_VEXT_VMERGE_VX(vmerge_vxm_w, int32_t, H4)
+GEN_VEXT_VMERGE_VX(vmerge_vxm_d, int64_t, H8)
/*
*** Vector Fixed-Point Arithmetic Instructions
@@ -2157,9 +2048,8 @@ static inline void
vext_vv_rm_2(void *vd, void *v0, void *vs1, void *vs2,
CPURISCVState *env,
uint32_t desc, uint32_t esz, uint32_t dsz,
- opivv2_rm_fn *fn, clear_fn *clearfn)
+ opivv2_rm_fn *fn)
{
- uint32_t vlmax = vext_maxsz(desc) / esz;
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
@@ -2181,17 +2071,15 @@ vext_vv_rm_2(void *vd, void *v0, void *vs1, void *vs2,
env, vl, vm, 3, fn);
break;
}
-
- clearfn(vd, vl, vl * dsz, vlmax * dsz);
}
/* generate helpers for fixed point instructions with OPIVV format */
-#define GEN_VEXT_VV_RM(NAME, ESZ, DSZ, CLEAR_FN) \
+#define GEN_VEXT_VV_RM(NAME, ESZ, DSZ) \
void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
vext_vv_rm_2(vd, v0, vs1, vs2, env, desc, ESZ, DSZ, \
- do_##NAME, CLEAR_FN); \
+ do_##NAME); \
}
static inline uint8_t saddu8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b)
@@ -2241,10 +2129,10 @@ RVVCALL(OPIVV2_RM, vsaddu_vv_b, OP_UUU_B, H1, H1, H1, saddu8)
RVVCALL(OPIVV2_RM, vsaddu_vv_h, OP_UUU_H, H2, H2, H2, saddu16)
RVVCALL(OPIVV2_RM, vsaddu_vv_w, OP_UUU_W, H4, H4, H4, saddu32)
RVVCALL(OPIVV2_RM, vsaddu_vv_d, OP_UUU_D, H8, H8, H8, saddu64)
-GEN_VEXT_VV_RM(vsaddu_vv_b, 1, 1, clearb)
-GEN_VEXT_VV_RM(vsaddu_vv_h, 2, 2, clearh)
-GEN_VEXT_VV_RM(vsaddu_vv_w, 4, 4, clearl)
-GEN_VEXT_VV_RM(vsaddu_vv_d, 8, 8, clearq)
+GEN_VEXT_VV_RM(vsaddu_vv_b, 1, 1)
+GEN_VEXT_VV_RM(vsaddu_vv_h, 2, 2)
+GEN_VEXT_VV_RM(vsaddu_vv_w, 4, 4)
+GEN_VEXT_VV_RM(vsaddu_vv_d, 8, 8)
typedef void opivx2_rm_fn(void *vd, target_long s1, void *vs2, int i,
CPURISCVState *env, int vxrm);
@@ -2276,9 +2164,8 @@ static inline void
vext_vx_rm_2(void *vd, void *v0, target_long s1, void *vs2,
CPURISCVState *env,
uint32_t desc, uint32_t esz, uint32_t dsz,
- opivx2_rm_fn *fn, clear_fn *clearfn)
+ opivx2_rm_fn *fn)
{
- uint32_t vlmax = vext_maxsz(desc) / esz;
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
@@ -2300,27 +2187,25 @@ vext_vx_rm_2(void *vd, void *v0, target_long s1, void *vs2,
env, vl, vm, 3, fn);
break;
}
-
- clearfn(vd, vl, vl * dsz, vlmax * dsz);
}
/* generate helpers for fixed point instructions with OPIVX format */
-#define GEN_VEXT_VX_RM(NAME, ESZ, DSZ, CLEAR_FN) \
+#define GEN_VEXT_VX_RM(NAME, ESZ, DSZ) \
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
vext_vx_rm_2(vd, v0, s1, vs2, env, desc, ESZ, DSZ, \
- do_##NAME, CLEAR_FN); \
+ do_##NAME); \
}
RVVCALL(OPIVX2_RM, vsaddu_vx_b, OP_UUU_B, H1, H1, saddu8)
RVVCALL(OPIVX2_RM, vsaddu_vx_h, OP_UUU_H, H2, H2, saddu16)
RVVCALL(OPIVX2_RM, vsaddu_vx_w, OP_UUU_W, H4, H4, saddu32)
RVVCALL(OPIVX2_RM, vsaddu_vx_d, OP_UUU_D, H8, H8, saddu64)
-GEN_VEXT_VX_RM(vsaddu_vx_b, 1, 1, clearb)
-GEN_VEXT_VX_RM(vsaddu_vx_h, 2, 2, clearh)
-GEN_VEXT_VX_RM(vsaddu_vx_w, 4, 4, clearl)
-GEN_VEXT_VX_RM(vsaddu_vx_d, 8, 8, clearq)
+GEN_VEXT_VX_RM(vsaddu_vx_b, 1, 1)
+GEN_VEXT_VX_RM(vsaddu_vx_h, 2, 2)
+GEN_VEXT_VX_RM(vsaddu_vx_w, 4, 4)
+GEN_VEXT_VX_RM(vsaddu_vx_d, 8, 8)
static inline int8_t sadd8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
{
@@ -2366,19 +2251,19 @@ RVVCALL(OPIVV2_RM, vsadd_vv_b, OP_SSS_B, H1, H1, H1, sadd8)
RVVCALL(OPIVV2_RM, vsadd_vv_h, OP_SSS_H, H2, H2, H2, sadd16)
RVVCALL(OPIVV2_RM, vsadd_vv_w, OP_SSS_W, H4, H4, H4, sadd32)
RVVCALL(OPIVV2_RM, vsadd_vv_d, OP_SSS_D, H8, H8, H8, sadd64)
-GEN_VEXT_VV_RM(vsadd_vv_b, 1, 1, clearb)
-GEN_VEXT_VV_RM(vsadd_vv_h, 2, 2, clearh)
-GEN_VEXT_VV_RM(vsadd_vv_w, 4, 4, clearl)
-GEN_VEXT_VV_RM(vsadd_vv_d, 8, 8, clearq)
+GEN_VEXT_VV_RM(vsadd_vv_b, 1, 1)
+GEN_VEXT_VV_RM(vsadd_vv_h, 2, 2)
+GEN_VEXT_VV_RM(vsadd_vv_w, 4, 4)
+GEN_VEXT_VV_RM(vsadd_vv_d, 8, 8)
RVVCALL(OPIVX2_RM, vsadd_vx_b, OP_SSS_B, H1, H1, sadd8)
RVVCALL(OPIVX2_RM, vsadd_vx_h, OP_SSS_H, H2, H2, sadd16)
RVVCALL(OPIVX2_RM, vsadd_vx_w, OP_SSS_W, H4, H4, sadd32)
RVVCALL(OPIVX2_RM, vsadd_vx_d, OP_SSS_D, H8, H8, sadd64)
-GEN_VEXT_VX_RM(vsadd_vx_b, 1, 1, clearb)
-GEN_VEXT_VX_RM(vsadd_vx_h, 2, 2, clearh)
-GEN_VEXT_VX_RM(vsadd_vx_w, 4, 4, clearl)
-GEN_VEXT_VX_RM(vsadd_vx_d, 8, 8, clearq)
+GEN_VEXT_VX_RM(vsadd_vx_b, 1, 1)
+GEN_VEXT_VX_RM(vsadd_vx_h, 2, 2)
+GEN_VEXT_VX_RM(vsadd_vx_w, 4, 4)
+GEN_VEXT_VX_RM(vsadd_vx_d, 8, 8)
static inline uint8_t ssubu8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b)
{
@@ -2427,19 +2312,19 @@ RVVCALL(OPIVV2_RM, vssubu_vv_b, OP_UUU_B, H1, H1, H1, ssubu8)
RVVCALL(OPIVV2_RM, vssubu_vv_h, OP_UUU_H, H2, H2, H2, ssubu16)
RVVCALL(OPIVV2_RM, vssubu_vv_w, OP_UUU_W, H4, H4, H4, ssubu32)
RVVCALL(OPIVV2_RM, vssubu_vv_d, OP_UUU_D, H8, H8, H8, ssubu64)
-GEN_VEXT_VV_RM(vssubu_vv_b, 1, 1, clearb)
-GEN_VEXT_VV_RM(vssubu_vv_h, 2, 2, clearh)
-GEN_VEXT_VV_RM(vssubu_vv_w, 4, 4, clearl)
-GEN_VEXT_VV_RM(vssubu_vv_d, 8, 8, clearq)
+GEN_VEXT_VV_RM(vssubu_vv_b, 1, 1)
+GEN_VEXT_VV_RM(vssubu_vv_h, 2, 2)
+GEN_VEXT_VV_RM(vssubu_vv_w, 4, 4)
+GEN_VEXT_VV_RM(vssubu_vv_d, 8, 8)
RVVCALL(OPIVX2_RM, vssubu_vx_b, OP_UUU_B, H1, H1, ssubu8)
RVVCALL(OPIVX2_RM, vssubu_vx_h, OP_UUU_H, H2, H2, ssubu16)
RVVCALL(OPIVX2_RM, vssubu_vx_w, OP_UUU_W, H4, H4, ssubu32)
RVVCALL(OPIVX2_RM, vssubu_vx_d, OP_UUU_D, H8, H8, ssubu64)
-GEN_VEXT_VX_RM(vssubu_vx_b, 1, 1, clearb)
-GEN_VEXT_VX_RM(vssubu_vx_h, 2, 2, clearh)
-GEN_VEXT_VX_RM(vssubu_vx_w, 4, 4, clearl)
-GEN_VEXT_VX_RM(vssubu_vx_d, 8, 8, clearq)
+GEN_VEXT_VX_RM(vssubu_vx_b, 1, 1)
+GEN_VEXT_VX_RM(vssubu_vx_h, 2, 2)
+GEN_VEXT_VX_RM(vssubu_vx_w, 4, 4)
+GEN_VEXT_VX_RM(vssubu_vx_d, 8, 8)
static inline int8_t ssub8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
{
@@ -2485,19 +2370,19 @@ RVVCALL(OPIVV2_RM, vssub_vv_b, OP_SSS_B, H1, H1, H1, ssub8)
RVVCALL(OPIVV2_RM, vssub_vv_h, OP_SSS_H, H2, H2, H2, ssub16)
RVVCALL(OPIVV2_RM, vssub_vv_w, OP_SSS_W, H4, H4, H4, ssub32)
RVVCALL(OPIVV2_RM, vssub_vv_d, OP_SSS_D, H8, H8, H8, ssub64)
-GEN_VEXT_VV_RM(vssub_vv_b, 1, 1, clearb)
-GEN_VEXT_VV_RM(vssub_vv_h, 2, 2, clearh)
-GEN_VEXT_VV_RM(vssub_vv_w, 4, 4, clearl)
-GEN_VEXT_VV_RM(vssub_vv_d, 8, 8, clearq)
+GEN_VEXT_VV_RM(vssub_vv_b, 1, 1)
+GEN_VEXT_VV_RM(vssub_vv_h, 2, 2)
+GEN_VEXT_VV_RM(vssub_vv_w, 4, 4)
+GEN_VEXT_VV_RM(vssub_vv_d, 8, 8)
RVVCALL(OPIVX2_RM, vssub_vx_b, OP_SSS_B, H1, H1, ssub8)
RVVCALL(OPIVX2_RM, vssub_vx_h, OP_SSS_H, H2, H2, ssub16)
RVVCALL(OPIVX2_RM, vssub_vx_w, OP_SSS_W, H4, H4, ssub32)
RVVCALL(OPIVX2_RM, vssub_vx_d, OP_SSS_D, H8, H8, ssub64)
-GEN_VEXT_VX_RM(vssub_vx_b, 1, 1, clearb)
-GEN_VEXT_VX_RM(vssub_vx_h, 2, 2, clearh)
-GEN_VEXT_VX_RM(vssub_vx_w, 4, 4, clearl)
-GEN_VEXT_VX_RM(vssub_vx_d, 8, 8, clearq)
+GEN_VEXT_VX_RM(vssub_vx_b, 1, 1)
+GEN_VEXT_VX_RM(vssub_vx_h, 2, 2)
+GEN_VEXT_VX_RM(vssub_vx_w, 4, 4)
+GEN_VEXT_VX_RM(vssub_vx_d, 8, 8)
/* Vector Single-Width Averaging Add and Subtract */
static inline uint8_t get_round(int vxrm, uint64_t v, uint8_t shift)
@@ -2549,19 +2434,19 @@ RVVCALL(OPIVV2_RM, vaadd_vv_b, OP_SSS_B, H1, H1, H1, aadd32)
RVVCALL(OPIVV2_RM, vaadd_vv_h, OP_SSS_H, H2, H2, H2, aadd32)
RVVCALL(OPIVV2_RM, vaadd_vv_w, OP_SSS_W, H4, H4, H4, aadd32)
RVVCALL(OPIVV2_RM, vaadd_vv_d, OP_SSS_D, H8, H8, H8, aadd64)
-GEN_VEXT_VV_RM(vaadd_vv_b, 1, 1, clearb)
-GEN_VEXT_VV_RM(vaadd_vv_h, 2, 2, clearh)
-GEN_VEXT_VV_RM(vaadd_vv_w, 4, 4, clearl)
-GEN_VEXT_VV_RM(vaadd_vv_d, 8, 8, clearq)
+GEN_VEXT_VV_RM(vaadd_vv_b, 1, 1)
+GEN_VEXT_VV_RM(vaadd_vv_h, 2, 2)
+GEN_VEXT_VV_RM(vaadd_vv_w, 4, 4)
+GEN_VEXT_VV_RM(vaadd_vv_d, 8, 8)
RVVCALL(OPIVX2_RM, vaadd_vx_b, OP_SSS_B, H1, H1, aadd32)
RVVCALL(OPIVX2_RM, vaadd_vx_h, OP_SSS_H, H2, H2, aadd32)
RVVCALL(OPIVX2_RM, vaadd_vx_w, OP_SSS_W, H4, H4, aadd32)
RVVCALL(OPIVX2_RM, vaadd_vx_d, OP_SSS_D, H8, H8, aadd64)
-GEN_VEXT_VX_RM(vaadd_vx_b, 1, 1, clearb)
-GEN_VEXT_VX_RM(vaadd_vx_h, 2, 2, clearh)
-GEN_VEXT_VX_RM(vaadd_vx_w, 4, 4, clearl)
-GEN_VEXT_VX_RM(vaadd_vx_d, 8, 8, clearq)
+GEN_VEXT_VX_RM(vaadd_vx_b, 1, 1)
+GEN_VEXT_VX_RM(vaadd_vx_h, 2, 2)
+GEN_VEXT_VX_RM(vaadd_vx_w, 4, 4)
+GEN_VEXT_VX_RM(vaadd_vx_d, 8, 8)
static inline int32_t asub32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
{
@@ -2585,19 +2470,19 @@ RVVCALL(OPIVV2_RM, vasub_vv_b, OP_SSS_B, H1, H1, H1, asub32)
RVVCALL(OPIVV2_RM, vasub_vv_h, OP_SSS_H, H2, H2, H2, asub32)
RVVCALL(OPIVV2_RM, vasub_vv_w, OP_SSS_W, H4, H4, H4, asub32)
RVVCALL(OPIVV2_RM, vasub_vv_d, OP_SSS_D, H8, H8, H8, asub64)
-GEN_VEXT_VV_RM(vasub_vv_b, 1, 1, clearb)
-GEN_VEXT_VV_RM(vasub_vv_h, 2, 2, clearh)
-GEN_VEXT_VV_RM(vasub_vv_w, 4, 4, clearl)
-GEN_VEXT_VV_RM(vasub_vv_d, 8, 8, clearq)
+GEN_VEXT_VV_RM(vasub_vv_b, 1, 1)
+GEN_VEXT_VV_RM(vasub_vv_h, 2, 2)
+GEN_VEXT_VV_RM(vasub_vv_w, 4, 4)
+GEN_VEXT_VV_RM(vasub_vv_d, 8, 8)
RVVCALL(OPIVX2_RM, vasub_vx_b, OP_SSS_B, H1, H1, asub32)
RVVCALL(OPIVX2_RM, vasub_vx_h, OP_SSS_H, H2, H2, asub32)
RVVCALL(OPIVX2_RM, vasub_vx_w, OP_SSS_W, H4, H4, asub32)
RVVCALL(OPIVX2_RM, vasub_vx_d, OP_SSS_D, H8, H8, asub64)
-GEN_VEXT_VX_RM(vasub_vx_b, 1, 1, clearb)
-GEN_VEXT_VX_RM(vasub_vx_h, 2, 2, clearh)
-GEN_VEXT_VX_RM(vasub_vx_w, 4, 4, clearl)
-GEN_VEXT_VX_RM(vasub_vx_d, 8, 8, clearq)
+GEN_VEXT_VX_RM(vasub_vx_b, 1, 1)
+GEN_VEXT_VX_RM(vasub_vx_h, 2, 2)
+GEN_VEXT_VX_RM(vasub_vx_w, 4, 4)
+GEN_VEXT_VX_RM(vasub_vx_d, 8, 8)
/* Vector Single-Width Fractional Multiply with Rounding and Saturation */
static inline int8_t vsmul8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
@@ -2692,19 +2577,19 @@ RVVCALL(OPIVV2_RM, vsmul_vv_b, OP_SSS_B, H1, H1, H1, vsmul8)
RVVCALL(OPIVV2_RM, vsmul_vv_h, OP_SSS_H, H2, H2, H2, vsmul16)
RVVCALL(OPIVV2_RM, vsmul_vv_w, OP_SSS_W, H4, H4, H4, vsmul32)
RVVCALL(OPIVV2_RM, vsmul_vv_d, OP_SSS_D, H8, H8, H8, vsmul64)
-GEN_VEXT_VV_RM(vsmul_vv_b, 1, 1, clearb)
-GEN_VEXT_VV_RM(vsmul_vv_h, 2, 2, clearh)
-GEN_VEXT_VV_RM(vsmul_vv_w, 4, 4, clearl)
-GEN_VEXT_VV_RM(vsmul_vv_d, 8, 8, clearq)
+GEN_VEXT_VV_RM(vsmul_vv_b, 1, 1)
+GEN_VEXT_VV_RM(vsmul_vv_h, 2, 2)
+GEN_VEXT_VV_RM(vsmul_vv_w, 4, 4)
+GEN_VEXT_VV_RM(vsmul_vv_d, 8, 8)
RVVCALL(OPIVX2_RM, vsmul_vx_b, OP_SSS_B, H1, H1, vsmul8)
RVVCALL(OPIVX2_RM, vsmul_vx_h, OP_SSS_H, H2, H2, vsmul16)
RVVCALL(OPIVX2_RM, vsmul_vx_w, OP_SSS_W, H4, H4, vsmul32)
RVVCALL(OPIVX2_RM, vsmul_vx_d, OP_SSS_D, H8, H8, vsmul64)
-GEN_VEXT_VX_RM(vsmul_vx_b, 1, 1, clearb)
-GEN_VEXT_VX_RM(vsmul_vx_h, 2, 2, clearh)
-GEN_VEXT_VX_RM(vsmul_vx_w, 4, 4, clearl)
-GEN_VEXT_VX_RM(vsmul_vx_d, 8, 8, clearq)
+GEN_VEXT_VX_RM(vsmul_vx_b, 1, 1)
+GEN_VEXT_VX_RM(vsmul_vx_h, 2, 2)
+GEN_VEXT_VX_RM(vsmul_vx_w, 4, 4)
+GEN_VEXT_VX_RM(vsmul_vx_d, 8, 8)
/* Vector Widening Saturating Scaled Multiply-Add */
static inline uint16_t
@@ -2757,9 +2642,9 @@ do_##NAME(void *vd, void *vs1, void *vs2, int i, \
RVVCALL(OPIVV3_RM, vwsmaccu_vv_b, WOP_UUU_B, H2, H1, H1, vwsmaccu8)
RVVCALL(OPIVV3_RM, vwsmaccu_vv_h, WOP_UUU_H, H4, H2, H2, vwsmaccu16)
RVVCALL(OPIVV3_RM, vwsmaccu_vv_w, WOP_UUU_W, H8, H4, H4, vwsmaccu32)
-GEN_VEXT_VV_RM(vwsmaccu_vv_b, 1, 2, clearh)
-GEN_VEXT_VV_RM(vwsmaccu_vv_h, 2, 4, clearl)
-GEN_VEXT_VV_RM(vwsmaccu_vv_w, 4, 8, clearq)
+GEN_VEXT_VV_RM(vwsmaccu_vv_b, 1, 2)
+GEN_VEXT_VV_RM(vwsmaccu_vv_h, 2, 4)
+GEN_VEXT_VV_RM(vwsmaccu_vv_w, 4, 8)
#define OPIVX3_RM(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \
static inline void \
@@ -2774,9 +2659,9 @@ do_##NAME(void *vd, target_long s1, void *vs2, int i, \
RVVCALL(OPIVX3_RM, vwsmaccu_vx_b, WOP_UUU_B, H2, H1, vwsmaccu8)
RVVCALL(OPIVX3_RM, vwsmaccu_vx_h, WOP_UUU_H, H4, H2, vwsmaccu16)
RVVCALL(OPIVX3_RM, vwsmaccu_vx_w, WOP_UUU_W, H8, H4, vwsmaccu32)
-GEN_VEXT_VX_RM(vwsmaccu_vx_b, 1, 2, clearh)
-GEN_VEXT_VX_RM(vwsmaccu_vx_h, 2, 4, clearl)
-GEN_VEXT_VX_RM(vwsmaccu_vx_w, 4, 8, clearq)
+GEN_VEXT_VX_RM(vwsmaccu_vx_b, 1, 2)
+GEN_VEXT_VX_RM(vwsmaccu_vx_h, 2, 4)
+GEN_VEXT_VX_RM(vwsmaccu_vx_w, 4, 8)
static inline int16_t
vwsmacc8(CPURISCVState *env, int vxrm, int8_t a, int8_t b, int16_t c)
@@ -2815,15 +2700,15 @@ vwsmacc32(CPURISCVState *env, int vxrm, int32_t a, int32_t b, int64_t c)
RVVCALL(OPIVV3_RM, vwsmacc_vv_b, WOP_SSS_B, H2, H1, H1, vwsmacc8)
RVVCALL(OPIVV3_RM, vwsmacc_vv_h, WOP_SSS_H, H4, H2, H2, vwsmacc16)
RVVCALL(OPIVV3_RM, vwsmacc_vv_w, WOP_SSS_W, H8, H4, H4, vwsmacc32)
-GEN_VEXT_VV_RM(vwsmacc_vv_b, 1, 2, clearh)
-GEN_VEXT_VV_RM(vwsmacc_vv_h, 2, 4, clearl)
-GEN_VEXT_VV_RM(vwsmacc_vv_w, 4, 8, clearq)
+GEN_VEXT_VV_RM(vwsmacc_vv_b, 1, 2)
+GEN_VEXT_VV_RM(vwsmacc_vv_h, 2, 4)
+GEN_VEXT_VV_RM(vwsmacc_vv_w, 4, 8)
RVVCALL(OPIVX3_RM, vwsmacc_vx_b, WOP_SSS_B, H2, H1, vwsmacc8)
RVVCALL(OPIVX3_RM, vwsmacc_vx_h, WOP_SSS_H, H4, H2, vwsmacc16)
RVVCALL(OPIVX3_RM, vwsmacc_vx_w, WOP_SSS_W, H8, H4, vwsmacc32)
-GEN_VEXT_VX_RM(vwsmacc_vx_b, 1, 2, clearh)
-GEN_VEXT_VX_RM(vwsmacc_vx_h, 2, 4, clearl)
-GEN_VEXT_VX_RM(vwsmacc_vx_w, 4, 8, clearq)
+GEN_VEXT_VX_RM(vwsmacc_vx_b, 1, 2)
+GEN_VEXT_VX_RM(vwsmacc_vx_h, 2, 4)
+GEN_VEXT_VX_RM(vwsmacc_vx_w, 4, 8)
static inline int16_t
vwsmaccsu8(CPURISCVState *env, int vxrm, uint8_t a, int8_t b, int16_t c)
@@ -2861,15 +2746,15 @@ vwsmaccsu32(CPURISCVState *env, int vxrm, uint32_t a, int32_t b, int64_t c)
RVVCALL(OPIVV3_RM, vwsmaccsu_vv_b, WOP_SSU_B, H2, H1, H1, vwsmaccsu8)
RVVCALL(OPIVV3_RM, vwsmaccsu_vv_h, WOP_SSU_H, H4, H2, H2, vwsmaccsu16)
RVVCALL(OPIVV3_RM, vwsmaccsu_vv_w, WOP_SSU_W, H8, H4, H4, vwsmaccsu32)
-GEN_VEXT_VV_RM(vwsmaccsu_vv_b, 1, 2, clearh)
-GEN_VEXT_VV_RM(vwsmaccsu_vv_h, 2, 4, clearl)
-GEN_VEXT_VV_RM(vwsmaccsu_vv_w, 4, 8, clearq)
+GEN_VEXT_VV_RM(vwsmaccsu_vv_b, 1, 2)
+GEN_VEXT_VV_RM(vwsmaccsu_vv_h, 2, 4)
+GEN_VEXT_VV_RM(vwsmaccsu_vv_w, 4, 8)
RVVCALL(OPIVX3_RM, vwsmaccsu_vx_b, WOP_SSU_B, H2, H1, vwsmaccsu8)
RVVCALL(OPIVX3_RM, vwsmaccsu_vx_h, WOP_SSU_H, H4, H2, vwsmaccsu16)
RVVCALL(OPIVX3_RM, vwsmaccsu_vx_w, WOP_SSU_W, H8, H4, vwsmaccsu32)
-GEN_VEXT_VX_RM(vwsmaccsu_vx_b, 1, 2, clearh)
-GEN_VEXT_VX_RM(vwsmaccsu_vx_h, 2, 4, clearl)
-GEN_VEXT_VX_RM(vwsmaccsu_vx_w, 4, 8, clearq)
+GEN_VEXT_VX_RM(vwsmaccsu_vx_b, 1, 2)
+GEN_VEXT_VX_RM(vwsmaccsu_vx_h, 2, 4)
+GEN_VEXT_VX_RM(vwsmaccsu_vx_w, 4, 8)
static inline int16_t
vwsmaccus8(CPURISCVState *env, int vxrm, int8_t a, uint8_t b, int16_t c)
@@ -2907,9 +2792,9 @@ vwsmaccus32(CPURISCVState *env, int vxrm, int32_t a, uint32_t b, int64_t c)
RVVCALL(OPIVX3_RM, vwsmaccus_vx_b, WOP_SUS_B, H2, H1, vwsmaccus8)
RVVCALL(OPIVX3_RM, vwsmaccus_vx_h, WOP_SUS_H, H4, H2, vwsmaccus16)
RVVCALL(OPIVX3_RM, vwsmaccus_vx_w, WOP_SUS_W, H8, H4, vwsmaccus32)
-GEN_VEXT_VX_RM(vwsmaccus_vx_b, 1, 2, clearh)
-GEN_VEXT_VX_RM(vwsmaccus_vx_h, 2, 4, clearl)
-GEN_VEXT_VX_RM(vwsmaccus_vx_w, 4, 8, clearq)
+GEN_VEXT_VX_RM(vwsmaccus_vx_b, 1, 2)
+GEN_VEXT_VX_RM(vwsmaccus_vx_h, 2, 4)
+GEN_VEXT_VX_RM(vwsmaccus_vx_w, 4, 8)
/* Vector Single-Width Scaling Shift Instructions */
static inline uint8_t
@@ -2956,19 +2841,19 @@ RVVCALL(OPIVV2_RM, vssrl_vv_b, OP_UUU_B, H1, H1, H1, vssrl8)
RVVCALL(OPIVV2_RM, vssrl_vv_h, OP_UUU_H, H2, H2, H2, vssrl16)
RVVCALL(OPIVV2_RM, vssrl_vv_w, OP_UUU_W, H4, H4, H4, vssrl32)
RVVCALL(OPIVV2_RM, vssrl_vv_d, OP_UUU_D, H8, H8, H8, vssrl64)
-GEN_VEXT_VV_RM(vssrl_vv_b, 1, 1, clearb)
-GEN_VEXT_VV_RM(vssrl_vv_h, 2, 2, clearh)
-GEN_VEXT_VV_RM(vssrl_vv_w, 4, 4, clearl)
-GEN_VEXT_VV_RM(vssrl_vv_d, 8, 8, clearq)
+GEN_VEXT_VV_RM(vssrl_vv_b, 1, 1)
+GEN_VEXT_VV_RM(vssrl_vv_h, 2, 2)
+GEN_VEXT_VV_RM(vssrl_vv_w, 4, 4)
+GEN_VEXT_VV_RM(vssrl_vv_d, 8, 8)
RVVCALL(OPIVX2_RM, vssrl_vx_b, OP_UUU_B, H1, H1, vssrl8)
RVVCALL(OPIVX2_RM, vssrl_vx_h, OP_UUU_H, H2, H2, vssrl16)
RVVCALL(OPIVX2_RM, vssrl_vx_w, OP_UUU_W, H4, H4, vssrl32)
RVVCALL(OPIVX2_RM, vssrl_vx_d, OP_UUU_D, H8, H8, vssrl64)
-GEN_VEXT_VX_RM(vssrl_vx_b, 1, 1, clearb)
-GEN_VEXT_VX_RM(vssrl_vx_h, 2, 2, clearh)
-GEN_VEXT_VX_RM(vssrl_vx_w, 4, 4, clearl)
-GEN_VEXT_VX_RM(vssrl_vx_d, 8, 8, clearq)
+GEN_VEXT_VX_RM(vssrl_vx_b, 1, 1)
+GEN_VEXT_VX_RM(vssrl_vx_h, 2, 2)
+GEN_VEXT_VX_RM(vssrl_vx_w, 4, 4)
+GEN_VEXT_VX_RM(vssrl_vx_d, 8, 8)
static inline int8_t
vssra8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
@@ -3015,19 +2900,19 @@ RVVCALL(OPIVV2_RM, vssra_vv_b, OP_SSS_B, H1, H1, H1, vssra8)
RVVCALL(OPIVV2_RM, vssra_vv_h, OP_SSS_H, H2, H2, H2, vssra16)
RVVCALL(OPIVV2_RM, vssra_vv_w, OP_SSS_W, H4, H4, H4, vssra32)
RVVCALL(OPIVV2_RM, vssra_vv_d, OP_SSS_D, H8, H8, H8, vssra64)
-GEN_VEXT_VV_RM(vssra_vv_b, 1, 1, clearb)
-GEN_VEXT_VV_RM(vssra_vv_h, 2, 2, clearh)
-GEN_VEXT_VV_RM(vssra_vv_w, 4, 4, clearl)
-GEN_VEXT_VV_RM(vssra_vv_d, 8, 8, clearq)
+GEN_VEXT_VV_RM(vssra_vv_b, 1, 1)
+GEN_VEXT_VV_RM(vssra_vv_h, 2, 2)
+GEN_VEXT_VV_RM(vssra_vv_w, 4, 4)
+GEN_VEXT_VV_RM(vssra_vv_d, 8, 8)
RVVCALL(OPIVX2_RM, vssra_vx_b, OP_SSS_B, H1, H1, vssra8)
RVVCALL(OPIVX2_RM, vssra_vx_h, OP_SSS_H, H2, H2, vssra16)
RVVCALL(OPIVX2_RM, vssra_vx_w, OP_SSS_W, H4, H4, vssra32)
RVVCALL(OPIVX2_RM, vssra_vx_d, OP_SSS_D, H8, H8, vssra64)
-GEN_VEXT_VX_RM(vssra_vx_b, 1, 1, clearb)
-GEN_VEXT_VX_RM(vssra_vx_h, 2, 2, clearh)
-GEN_VEXT_VX_RM(vssra_vx_w, 4, 4, clearl)
-GEN_VEXT_VX_RM(vssra_vx_d, 8, 8, clearq)
+GEN_VEXT_VX_RM(vssra_vx_b, 1, 1)
+GEN_VEXT_VX_RM(vssra_vx_h, 2, 2)
+GEN_VEXT_VX_RM(vssra_vx_w, 4, 4)
+GEN_VEXT_VX_RM(vssra_vx_d, 8, 8)
/* Vector Narrowing Fixed-Point Clip Instructions */
static inline int8_t
@@ -3090,16 +2975,16 @@ vnclip32(CPURISCVState *env, int vxrm, int64_t a, int32_t b)
RVVCALL(OPIVV2_RM, vnclip_vv_b, NOP_SSS_B, H1, H2, H1, vnclip8)
RVVCALL(OPIVV2_RM, vnclip_vv_h, NOP_SSS_H, H2, H4, H2, vnclip16)
RVVCALL(OPIVV2_RM, vnclip_vv_w, NOP_SSS_W, H4, H8, H4, vnclip32)
-GEN_VEXT_VV_RM(vnclip_vv_b, 1, 1, clearb)
-GEN_VEXT_VV_RM(vnclip_vv_h, 2, 2, clearh)
-GEN_VEXT_VV_RM(vnclip_vv_w, 4, 4, clearl)
+GEN_VEXT_VV_RM(vnclip_vv_b, 1, 1)
+GEN_VEXT_VV_RM(vnclip_vv_h, 2, 2)
+GEN_VEXT_VV_RM(vnclip_vv_w, 4, 4)
RVVCALL(OPIVX2_RM, vnclip_vx_b, NOP_SSS_B, H1, H2, vnclip8)
RVVCALL(OPIVX2_RM, vnclip_vx_h, NOP_SSS_H, H2, H4, vnclip16)
RVVCALL(OPIVX2_RM, vnclip_vx_w, NOP_SSS_W, H4, H8, vnclip32)
-GEN_VEXT_VX_RM(vnclip_vx_b, 1, 1, clearb)
-GEN_VEXT_VX_RM(vnclip_vx_h, 2, 2, clearh)
-GEN_VEXT_VX_RM(vnclip_vx_w, 4, 4, clearl)
+GEN_VEXT_VX_RM(vnclip_vx_b, 1, 1)
+GEN_VEXT_VX_RM(vnclip_vx_h, 2, 2)
+GEN_VEXT_VX_RM(vnclip_vx_w, 4, 4)
static inline uint8_t
vnclipu8(CPURISCVState *env, int vxrm, uint16_t a, uint8_t b)
@@ -3152,16 +3037,16 @@ vnclipu32(CPURISCVState *env, int vxrm, uint64_t a, uint32_t b)
RVVCALL(OPIVV2_RM, vnclipu_vv_b, NOP_UUU_B, H1, H2, H1, vnclipu8)
RVVCALL(OPIVV2_RM, vnclipu_vv_h, NOP_UUU_H, H2, H4, H2, vnclipu16)
RVVCALL(OPIVV2_RM, vnclipu_vv_w, NOP_UUU_W, H4, H8, H4, vnclipu32)
-GEN_VEXT_VV_RM(vnclipu_vv_b, 1, 1, clearb)
-GEN_VEXT_VV_RM(vnclipu_vv_h, 2, 2, clearh)
-GEN_VEXT_VV_RM(vnclipu_vv_w, 4, 4, clearl)
+GEN_VEXT_VV_RM(vnclipu_vv_b, 1, 1)
+GEN_VEXT_VV_RM(vnclipu_vv_h, 2, 2)
+GEN_VEXT_VV_RM(vnclipu_vv_w, 4, 4)
RVVCALL(OPIVX2_RM, vnclipu_vx_b, NOP_UUU_B, H1, H2, vnclipu8)
RVVCALL(OPIVX2_RM, vnclipu_vx_h, NOP_UUU_H, H2, H4, vnclipu16)
RVVCALL(OPIVX2_RM, vnclipu_vx_w, NOP_UUU_W, H4, H8, vnclipu32)
-GEN_VEXT_VX_RM(vnclipu_vx_b, 1, 1, clearb)
-GEN_VEXT_VX_RM(vnclipu_vx_h, 2, 2, clearh)
-GEN_VEXT_VX_RM(vnclipu_vx_w, 4, 4, clearl)
+GEN_VEXT_VX_RM(vnclipu_vx_b, 1, 1)
+GEN_VEXT_VX_RM(vnclipu_vx_h, 2, 2)
+GEN_VEXT_VX_RM(vnclipu_vx_w, 4, 4)
/*
*** Vector Float Point Arithmetic Instructions
@@ -3176,12 +3061,11 @@ static void do_##NAME(void *vd, void *vs1, void *vs2, int i, \
*((TD *)vd + HD(i)) = OP(s2, s1, &env->fp_status); \
}
-#define GEN_VEXT_VV_ENV(NAME, ESZ, DSZ, CLEAR_FN) \
+#define GEN_VEXT_VV_ENV(NAME, ESZ, DSZ) \
void HELPER(NAME)(void *vd, void *v0, void *vs1, \
void *vs2, CPURISCVState *env, \
uint32_t desc) \
{ \
- uint32_t vlmax = vext_maxsz(desc) / ESZ; \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
@@ -3192,15 +3076,14 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
} \
do_##NAME(vd, vs1, vs2, i, env); \
} \
- CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \
}
RVVCALL(OPFVV2, vfadd_vv_h, OP_UUU_H, H2, H2, H2, float16_add)
RVVCALL(OPFVV2, vfadd_vv_w, OP_UUU_W, H4, H4, H4, float32_add)
RVVCALL(OPFVV2, vfadd_vv_d, OP_UUU_D, H8, H8, H8, float64_add)
-GEN_VEXT_VV_ENV(vfadd_vv_h, 2, 2, clearh)
-GEN_VEXT_VV_ENV(vfadd_vv_w, 4, 4, clearl)
-GEN_VEXT_VV_ENV(vfadd_vv_d, 8, 8, clearq)
+GEN_VEXT_VV_ENV(vfadd_vv_h, 2, 2)
+GEN_VEXT_VV_ENV(vfadd_vv_w, 4, 4)
+GEN_VEXT_VV_ENV(vfadd_vv_d, 8, 8)
#define OPFVF2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \
static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i, \
@@ -3210,12 +3093,11 @@ static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i, \
*((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1, &env->fp_status);\
}
-#define GEN_VEXT_VF(NAME, ESZ, DSZ, CLEAR_FN) \
+#define GEN_VEXT_VF(NAME, ESZ, DSZ) \
void HELPER(NAME)(void *vd, void *v0, uint64_t s1, \
void *vs2, CPURISCVState *env, \
uint32_t desc) \
{ \
- uint32_t vlmax = vext_maxsz(desc) / ESZ; \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
@@ -3226,28 +3108,27 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, \
} \
do_##NAME(vd, s1, vs2, i, env); \
} \
- CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \
}
RVVCALL(OPFVF2, vfadd_vf_h, OP_UUU_H, H2, H2, float16_add)
RVVCALL(OPFVF2, vfadd_vf_w, OP_UUU_W, H4, H4, float32_add)
RVVCALL(OPFVF2, vfadd_vf_d, OP_UUU_D, H8, H8, float64_add)
-GEN_VEXT_VF(vfadd_vf_h, 2, 2, clearh)
-GEN_VEXT_VF(vfadd_vf_w, 4, 4, clearl)
-GEN_VEXT_VF(vfadd_vf_d, 8, 8, clearq)
+GEN_VEXT_VF(vfadd_vf_h, 2, 2)
+GEN_VEXT_VF(vfadd_vf_w, 4, 4)
+GEN_VEXT_VF(vfadd_vf_d, 8, 8)
RVVCALL(OPFVV2, vfsub_vv_h, OP_UUU_H, H2, H2, H2, float16_sub)
RVVCALL(OPFVV2, vfsub_vv_w, OP_UUU_W, H4, H4, H4, float32_sub)
RVVCALL(OPFVV2, vfsub_vv_d, OP_UUU_D, H8, H8, H8, float64_sub)
-GEN_VEXT_VV_ENV(vfsub_vv_h, 2, 2, clearh)
-GEN_VEXT_VV_ENV(vfsub_vv_w, 4, 4, clearl)
-GEN_VEXT_VV_ENV(vfsub_vv_d, 8, 8, clearq)
+GEN_VEXT_VV_ENV(vfsub_vv_h, 2, 2)
+GEN_VEXT_VV_ENV(vfsub_vv_w, 4, 4)
+GEN_VEXT_VV_ENV(vfsub_vv_d, 8, 8)
RVVCALL(OPFVF2, vfsub_vf_h, OP_UUU_H, H2, H2, float16_sub)
RVVCALL(OPFVF2, vfsub_vf_w, OP_UUU_W, H4, H4, float32_sub)
RVVCALL(OPFVF2, vfsub_vf_d, OP_UUU_D, H8, H8, float64_sub)
-GEN_VEXT_VF(vfsub_vf_h, 2, 2, clearh)
-GEN_VEXT_VF(vfsub_vf_w, 4, 4, clearl)
-GEN_VEXT_VF(vfsub_vf_d, 8, 8, clearq)
+GEN_VEXT_VF(vfsub_vf_h, 2, 2)
+GEN_VEXT_VF(vfsub_vf_w, 4, 4)
+GEN_VEXT_VF(vfsub_vf_d, 8, 8)
static uint16_t float16_rsub(uint16_t a, uint16_t b, float_status *s)
{
@@ -3267,9 +3148,9 @@ static uint64_t float64_rsub(uint64_t a, uint64_t b, float_status *s)
RVVCALL(OPFVF2, vfrsub_vf_h, OP_UUU_H, H2, H2, float16_rsub)
RVVCALL(OPFVF2, vfrsub_vf_w, OP_UUU_W, H4, H4, float32_rsub)
RVVCALL(OPFVF2, vfrsub_vf_d, OP_UUU_D, H8, H8, float64_rsub)
-GEN_VEXT_VF(vfrsub_vf_h, 2, 2, clearh)
-GEN_VEXT_VF(vfrsub_vf_w, 4, 4, clearl)
-GEN_VEXT_VF(vfrsub_vf_d, 8, 8, clearq)
+GEN_VEXT_VF(vfrsub_vf_h, 2, 2)
+GEN_VEXT_VF(vfrsub_vf_w, 4, 4)
+GEN_VEXT_VF(vfrsub_vf_d, 8, 8)
/* Vector Widening Floating-Point Add/Subtract Instructions */
static uint32_t vfwadd16(uint16_t a, uint16_t b, float_status *s)
@@ -3287,12 +3168,12 @@ static uint64_t vfwadd32(uint32_t a, uint32_t b, float_status *s)
RVVCALL(OPFVV2, vfwadd_vv_h, WOP_UUU_H, H4, H2, H2, vfwadd16)
RVVCALL(OPFVV2, vfwadd_vv_w, WOP_UUU_W, H8, H4, H4, vfwadd32)
-GEN_VEXT_VV_ENV(vfwadd_vv_h, 2, 4, clearl)
-GEN_VEXT_VV_ENV(vfwadd_vv_w, 4, 8, clearq)
+GEN_VEXT_VV_ENV(vfwadd_vv_h, 2, 4)
+GEN_VEXT_VV_ENV(vfwadd_vv_w, 4, 8)
RVVCALL(OPFVF2, vfwadd_vf_h, WOP_UUU_H, H4, H2, vfwadd16)
RVVCALL(OPFVF2, vfwadd_vf_w, WOP_UUU_W, H8, H4, vfwadd32)
-GEN_VEXT_VF(vfwadd_vf_h, 2, 4, clearl)
-GEN_VEXT_VF(vfwadd_vf_w, 4, 8, clearq)
+GEN_VEXT_VF(vfwadd_vf_h, 2, 4)
+GEN_VEXT_VF(vfwadd_vf_w, 4, 8)
static uint32_t vfwsub16(uint16_t a, uint16_t b, float_status *s)
{
@@ -3309,12 +3190,12 @@ static uint64_t vfwsub32(uint32_t a, uint32_t b, float_status *s)
RVVCALL(OPFVV2, vfwsub_vv_h, WOP_UUU_H, H4, H2, H2, vfwsub16)
RVVCALL(OPFVV2, vfwsub_vv_w, WOP_UUU_W, H8, H4, H4, vfwsub32)
-GEN_VEXT_VV_ENV(vfwsub_vv_h, 2, 4, clearl)
-GEN_VEXT_VV_ENV(vfwsub_vv_w, 4, 8, clearq)
+GEN_VEXT_VV_ENV(vfwsub_vv_h, 2, 4)
+GEN_VEXT_VV_ENV(vfwsub_vv_w, 4, 8)
RVVCALL(OPFVF2, vfwsub_vf_h, WOP_UUU_H, H4, H2, vfwsub16)
RVVCALL(OPFVF2, vfwsub_vf_w, WOP_UUU_W, H8, H4, vfwsub32)
-GEN_VEXT_VF(vfwsub_vf_h, 2, 4, clearl)
-GEN_VEXT_VF(vfwsub_vf_w, 4, 8, clearq)
+GEN_VEXT_VF(vfwsub_vf_h, 2, 4)
+GEN_VEXT_VF(vfwsub_vf_w, 4, 8)
static uint32_t vfwaddw16(uint32_t a, uint16_t b, float_status *s)
{
@@ -3328,12 +3209,12 @@ static uint64_t vfwaddw32(uint64_t a, uint32_t b, float_status *s)
RVVCALL(OPFVV2, vfwadd_wv_h, WOP_WUUU_H, H4, H2, H2, vfwaddw16)
RVVCALL(OPFVV2, vfwadd_wv_w, WOP_WUUU_W, H8, H4, H4, vfwaddw32)
-GEN_VEXT_VV_ENV(vfwadd_wv_h, 2, 4, clearl)
-GEN_VEXT_VV_ENV(vfwadd_wv_w, 4, 8, clearq)
+GEN_VEXT_VV_ENV(vfwadd_wv_h, 2, 4)
+GEN_VEXT_VV_ENV(vfwadd_wv_w, 4, 8)
RVVCALL(OPFVF2, vfwadd_wf_h, WOP_WUUU_H, H4, H2, vfwaddw16)
RVVCALL(OPFVF2, vfwadd_wf_w, WOP_WUUU_W, H8, H4, vfwaddw32)
-GEN_VEXT_VF(vfwadd_wf_h, 2, 4, clearl)
-GEN_VEXT_VF(vfwadd_wf_w, 4, 8, clearq)
+GEN_VEXT_VF(vfwadd_wf_h, 2, 4)
+GEN_VEXT_VF(vfwadd_wf_w, 4, 8)
static uint32_t vfwsubw16(uint32_t a, uint16_t b, float_status *s)
{
@@ -3347,39 +3228,39 @@ static uint64_t vfwsubw32(uint64_t a, uint32_t b, float_status *s)
RVVCALL(OPFVV2, vfwsub_wv_h, WOP_WUUU_H, H4, H2, H2, vfwsubw16)
RVVCALL(OPFVV2, vfwsub_wv_w, WOP_WUUU_W, H8, H4, H4, vfwsubw32)
-GEN_VEXT_VV_ENV(vfwsub_wv_h, 2, 4, clearl)
-GEN_VEXT_VV_ENV(vfwsub_wv_w, 4, 8, clearq)
+GEN_VEXT_VV_ENV(vfwsub_wv_h, 2, 4)
+GEN_VEXT_VV_ENV(vfwsub_wv_w, 4, 8)
RVVCALL(OPFVF2, vfwsub_wf_h, WOP_WUUU_H, H4, H2, vfwsubw16)
RVVCALL(OPFVF2, vfwsub_wf_w, WOP_WUUU_W, H8, H4, vfwsubw32)
-GEN_VEXT_VF(vfwsub_wf_h, 2, 4, clearl)
-GEN_VEXT_VF(vfwsub_wf_w, 4, 8, clearq)
+GEN_VEXT_VF(vfwsub_wf_h, 2, 4)
+GEN_VEXT_VF(vfwsub_wf_w, 4, 8)
/* Vector Single-Width Floating-Point Multiply/Divide Instructions */
RVVCALL(OPFVV2, vfmul_vv_h, OP_UUU_H, H2, H2, H2, float16_mul)
RVVCALL(OPFVV2, vfmul_vv_w, OP_UUU_W, H4, H4, H4, float32_mul)
RVVCALL(OPFVV2, vfmul_vv_d, OP_UUU_D, H8, H8, H8, float64_mul)
-GEN_VEXT_VV_ENV(vfmul_vv_h, 2, 2, clearh)
-GEN_VEXT_VV_ENV(vfmul_vv_w, 4, 4, clearl)
-GEN_VEXT_VV_ENV(vfmul_vv_d, 8, 8, clearq)
+GEN_VEXT_VV_ENV(vfmul_vv_h, 2, 2)
+GEN_VEXT_VV_ENV(vfmul_vv_w, 4, 4)
+GEN_VEXT_VV_ENV(vfmul_vv_d, 8, 8)
RVVCALL(OPFVF2, vfmul_vf_h, OP_UUU_H, H2, H2, float16_mul)
RVVCALL(OPFVF2, vfmul_vf_w, OP_UUU_W, H4, H4, float32_mul)
RVVCALL(OPFVF2, vfmul_vf_d, OP_UUU_D, H8, H8, float64_mul)
-GEN_VEXT_VF(vfmul_vf_h, 2, 2, clearh)
-GEN_VEXT_VF(vfmul_vf_w, 4, 4, clearl)
-GEN_VEXT_VF(vfmul_vf_d, 8, 8, clearq)
+GEN_VEXT_VF(vfmul_vf_h, 2, 2)
+GEN_VEXT_VF(vfmul_vf_w, 4, 4)
+GEN_VEXT_VF(vfmul_vf_d, 8, 8)
RVVCALL(OPFVV2, vfdiv_vv_h, OP_UUU_H, H2, H2, H2, float16_div)
RVVCALL(OPFVV2, vfdiv_vv_w, OP_UUU_W, H4, H4, H4, float32_div)
RVVCALL(OPFVV2, vfdiv_vv_d, OP_UUU_D, H8, H8, H8, float64_div)
-GEN_VEXT_VV_ENV(vfdiv_vv_h, 2, 2, clearh)
-GEN_VEXT_VV_ENV(vfdiv_vv_w, 4, 4, clearl)
-GEN_VEXT_VV_ENV(vfdiv_vv_d, 8, 8, clearq)
+GEN_VEXT_VV_ENV(vfdiv_vv_h, 2, 2)
+GEN_VEXT_VV_ENV(vfdiv_vv_w, 4, 4)
+GEN_VEXT_VV_ENV(vfdiv_vv_d, 8, 8)
RVVCALL(OPFVF2, vfdiv_vf_h, OP_UUU_H, H2, H2, float16_div)
RVVCALL(OPFVF2, vfdiv_vf_w, OP_UUU_W, H4, H4, float32_div)
RVVCALL(OPFVF2, vfdiv_vf_d, OP_UUU_D, H8, H8, float64_div)
-GEN_VEXT_VF(vfdiv_vf_h, 2, 2, clearh)
-GEN_VEXT_VF(vfdiv_vf_w, 4, 4, clearl)
-GEN_VEXT_VF(vfdiv_vf_d, 8, 8, clearq)
+GEN_VEXT_VF(vfdiv_vf_h, 2, 2)
+GEN_VEXT_VF(vfdiv_vf_w, 4, 4)
+GEN_VEXT_VF(vfdiv_vf_d, 8, 8)
static uint16_t float16_rdiv(uint16_t a, uint16_t b, float_status *s)
{
@@ -3399,9 +3280,9 @@ static uint64_t float64_rdiv(uint64_t a, uint64_t b, float_status *s)
RVVCALL(OPFVF2, vfrdiv_vf_h, OP_UUU_H, H2, H2, float16_rdiv)
RVVCALL(OPFVF2, vfrdiv_vf_w, OP_UUU_W, H4, H4, float32_rdiv)
RVVCALL(OPFVF2, vfrdiv_vf_d, OP_UUU_D, H8, H8, float64_rdiv)
-GEN_VEXT_VF(vfrdiv_vf_h, 2, 2, clearh)
-GEN_VEXT_VF(vfrdiv_vf_w, 4, 4, clearl)
-GEN_VEXT_VF(vfrdiv_vf_d, 8, 8, clearq)
+GEN_VEXT_VF(vfrdiv_vf_h, 2, 2)
+GEN_VEXT_VF(vfrdiv_vf_w, 4, 4)
+GEN_VEXT_VF(vfrdiv_vf_d, 8, 8)
/* Vector Widening Floating-Point Multiply */
static uint32_t vfwmul16(uint16_t a, uint16_t b, float_status *s)
@@ -3418,12 +3299,12 @@ static uint64_t vfwmul32(uint32_t a, uint32_t b, float_status *s)
}
RVVCALL(OPFVV2, vfwmul_vv_h, WOP_UUU_H, H4, H2, H2, vfwmul16)
RVVCALL(OPFVV2, vfwmul_vv_w, WOP_UUU_W, H8, H4, H4, vfwmul32)
-GEN_VEXT_VV_ENV(vfwmul_vv_h, 2, 4, clearl)
-GEN_VEXT_VV_ENV(vfwmul_vv_w, 4, 8, clearq)
+GEN_VEXT_VV_ENV(vfwmul_vv_h, 2, 4)
+GEN_VEXT_VV_ENV(vfwmul_vv_w, 4, 8)
RVVCALL(OPFVF2, vfwmul_vf_h, WOP_UUU_H, H4, H2, vfwmul16)
RVVCALL(OPFVF2, vfwmul_vf_w, WOP_UUU_W, H8, H4, vfwmul32)
-GEN_VEXT_VF(vfwmul_vf_h, 2, 4, clearl)
-GEN_VEXT_VF(vfwmul_vf_w, 4, 8, clearq)
+GEN_VEXT_VF(vfwmul_vf_h, 2, 4)
+GEN_VEXT_VF(vfwmul_vf_w, 4, 8)
/* Vector Single-Width Floating-Point Fused Multiply-Add Instructions */
#define OPFVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \
@@ -3454,9 +3335,9 @@ static uint64_t fmacc64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
RVVCALL(OPFVV3, vfmacc_vv_h, OP_UUU_H, H2, H2, H2, fmacc16)
RVVCALL(OPFVV3, vfmacc_vv_w, OP_UUU_W, H4, H4, H4, fmacc32)
RVVCALL(OPFVV3, vfmacc_vv_d, OP_UUU_D, H8, H8, H8, fmacc64)
-GEN_VEXT_VV_ENV(vfmacc_vv_h, 2, 2, clearh)
-GEN_VEXT_VV_ENV(vfmacc_vv_w, 4, 4, clearl)
-GEN_VEXT_VV_ENV(vfmacc_vv_d, 8, 8, clearq)
+GEN_VEXT_VV_ENV(vfmacc_vv_h, 2, 2)
+GEN_VEXT_VV_ENV(vfmacc_vv_w, 4, 4)
+GEN_VEXT_VV_ENV(vfmacc_vv_d, 8, 8)
#define OPFVF3(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \
static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i, \
@@ -3470,9 +3351,9 @@ static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i, \
RVVCALL(OPFVF3, vfmacc_vf_h, OP_UUU_H, H2, H2, fmacc16)
RVVCALL(OPFVF3, vfmacc_vf_w, OP_UUU_W, H4, H4, fmacc32)
RVVCALL(OPFVF3, vfmacc_vf_d, OP_UUU_D, H8, H8, fmacc64)
-GEN_VEXT_VF(vfmacc_vf_h, 2, 2, clearh)
-GEN_VEXT_VF(vfmacc_vf_w, 4, 4, clearl)
-GEN_VEXT_VF(vfmacc_vf_d, 8, 8, clearq)
+GEN_VEXT_VF(vfmacc_vf_h, 2, 2)
+GEN_VEXT_VF(vfmacc_vf_w, 4, 4)
+GEN_VEXT_VF(vfmacc_vf_d, 8, 8)
static uint16_t fnmacc16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
{
@@ -3495,15 +3376,15 @@ static uint64_t fnmacc64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
RVVCALL(OPFVV3, vfnmacc_vv_h, OP_UUU_H, H2, H2, H2, fnmacc16)
RVVCALL(OPFVV3, vfnmacc_vv_w, OP_UUU_W, H4, H4, H4, fnmacc32)
RVVCALL(OPFVV3, vfnmacc_vv_d, OP_UUU_D, H8, H8, H8, fnmacc64)
-GEN_VEXT_VV_ENV(vfnmacc_vv_h, 2, 2, clearh)
-GEN_VEXT_VV_ENV(vfnmacc_vv_w, 4, 4, clearl)
-GEN_VEXT_VV_ENV(vfnmacc_vv_d, 8, 8, clearq)
+GEN_VEXT_VV_ENV(vfnmacc_vv_h, 2, 2)
+GEN_VEXT_VV_ENV(vfnmacc_vv_w, 4, 4)
+GEN_VEXT_VV_ENV(vfnmacc_vv_d, 8, 8)
RVVCALL(OPFVF3, vfnmacc_vf_h, OP_UUU_H, H2, H2, fnmacc16)
RVVCALL(OPFVF3, vfnmacc_vf_w, OP_UUU_W, H4, H4, fnmacc32)
RVVCALL(OPFVF3, vfnmacc_vf_d, OP_UUU_D, H8, H8, fnmacc64)
-GEN_VEXT_VF(vfnmacc_vf_h, 2, 2, clearh)
-GEN_VEXT_VF(vfnmacc_vf_w, 4, 4, clearl)
-GEN_VEXT_VF(vfnmacc_vf_d, 8, 8, clearq)
+GEN_VEXT_VF(vfnmacc_vf_h, 2, 2)
+GEN_VEXT_VF(vfnmacc_vf_w, 4, 4)
+GEN_VEXT_VF(vfnmacc_vf_d, 8, 8)
static uint16_t fmsac16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
{
@@ -3523,15 +3404,15 @@ static uint64_t fmsac64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
RVVCALL(OPFVV3, vfmsac_vv_h, OP_UUU_H, H2, H2, H2, fmsac16)
RVVCALL(OPFVV3, vfmsac_vv_w, OP_UUU_W, H4, H4, H4, fmsac32)
RVVCALL(OPFVV3, vfmsac_vv_d, OP_UUU_D, H8, H8, H8, fmsac64)
-GEN_VEXT_VV_ENV(vfmsac_vv_h, 2, 2, clearh)
-GEN_VEXT_VV_ENV(vfmsac_vv_w, 4, 4, clearl)
-GEN_VEXT_VV_ENV(vfmsac_vv_d, 8, 8, clearq)
+GEN_VEXT_VV_ENV(vfmsac_vv_h, 2, 2)
+GEN_VEXT_VV_ENV(vfmsac_vv_w, 4, 4)
+GEN_VEXT_VV_ENV(vfmsac_vv_d, 8, 8)
RVVCALL(OPFVF3, vfmsac_vf_h, OP_UUU_H, H2, H2, fmsac16)
RVVCALL(OPFVF3, vfmsac_vf_w, OP_UUU_W, H4, H4, fmsac32)
RVVCALL(OPFVF3, vfmsac_vf_d, OP_UUU_D, H8, H8, fmsac64)
-GEN_VEXT_VF(vfmsac_vf_h, 2, 2, clearh)
-GEN_VEXT_VF(vfmsac_vf_w, 4, 4, clearl)
-GEN_VEXT_VF(vfmsac_vf_d, 8, 8, clearq)
+GEN_VEXT_VF(vfmsac_vf_h, 2, 2)
+GEN_VEXT_VF(vfmsac_vf_w, 4, 4)
+GEN_VEXT_VF(vfmsac_vf_d, 8, 8)
static uint16_t fnmsac16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
{
@@ -3551,15 +3432,15 @@ static uint64_t fnmsac64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
RVVCALL(OPFVV3, vfnmsac_vv_h, OP_UUU_H, H2, H2, H2, fnmsac16)
RVVCALL(OPFVV3, vfnmsac_vv_w, OP_UUU_W, H4, H4, H4, fnmsac32)
RVVCALL(OPFVV3, vfnmsac_vv_d, OP_UUU_D, H8, H8, H8, fnmsac64)
-GEN_VEXT_VV_ENV(vfnmsac_vv_h, 2, 2, clearh)
-GEN_VEXT_VV_ENV(vfnmsac_vv_w, 4, 4, clearl)
-GEN_VEXT_VV_ENV(vfnmsac_vv_d, 8, 8, clearq)
+GEN_VEXT_VV_ENV(vfnmsac_vv_h, 2, 2)
+GEN_VEXT_VV_ENV(vfnmsac_vv_w, 4, 4)
+GEN_VEXT_VV_ENV(vfnmsac_vv_d, 8, 8)
RVVCALL(OPFVF3, vfnmsac_vf_h, OP_UUU_H, H2, H2, fnmsac16)
RVVCALL(OPFVF3, vfnmsac_vf_w, OP_UUU_W, H4, H4, fnmsac32)
RVVCALL(OPFVF3, vfnmsac_vf_d, OP_UUU_D, H8, H8, fnmsac64)
-GEN_VEXT_VF(vfnmsac_vf_h, 2, 2, clearh)
-GEN_VEXT_VF(vfnmsac_vf_w, 4, 4, clearl)
-GEN_VEXT_VF(vfnmsac_vf_d, 8, 8, clearq)
+GEN_VEXT_VF(vfnmsac_vf_h, 2, 2)
+GEN_VEXT_VF(vfnmsac_vf_w, 4, 4)
+GEN_VEXT_VF(vfnmsac_vf_d, 8, 8)
static uint16_t fmadd16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
{
@@ -3579,15 +3460,15 @@ static uint64_t fmadd64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
RVVCALL(OPFVV3, vfmadd_vv_h, OP_UUU_H, H2, H2, H2, fmadd16)
RVVCALL(OPFVV3, vfmadd_vv_w, OP_UUU_W, H4, H4, H4, fmadd32)
RVVCALL(OPFVV3, vfmadd_vv_d, OP_UUU_D, H8, H8, H8, fmadd64)
-GEN_VEXT_VV_ENV(vfmadd_vv_h, 2, 2, clearh)
-GEN_VEXT_VV_ENV(vfmadd_vv_w, 4, 4, clearl)
-GEN_VEXT_VV_ENV(vfmadd_vv_d, 8, 8, clearq)
+GEN_VEXT_VV_ENV(vfmadd_vv_h, 2, 2)
+GEN_VEXT_VV_ENV(vfmadd_vv_w, 4, 4)
+GEN_VEXT_VV_ENV(vfmadd_vv_d, 8, 8)
RVVCALL(OPFVF3, vfmadd_vf_h, OP_UUU_H, H2, H2, fmadd16)
RVVCALL(OPFVF3, vfmadd_vf_w, OP_UUU_W, H4, H4, fmadd32)
RVVCALL(OPFVF3, vfmadd_vf_d, OP_UUU_D, H8, H8, fmadd64)
-GEN_VEXT_VF(vfmadd_vf_h, 2, 2, clearh)
-GEN_VEXT_VF(vfmadd_vf_w, 4, 4, clearl)
-GEN_VEXT_VF(vfmadd_vf_d, 8, 8, clearq)
+GEN_VEXT_VF(vfmadd_vf_h, 2, 2)
+GEN_VEXT_VF(vfmadd_vf_w, 4, 4)
+GEN_VEXT_VF(vfmadd_vf_d, 8, 8)
static uint16_t fnmadd16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
{
@@ -3610,15 +3491,15 @@ static uint64_t fnmadd64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
RVVCALL(OPFVV3, vfnmadd_vv_h, OP_UUU_H, H2, H2, H2, fnmadd16)
RVVCALL(OPFVV3, vfnmadd_vv_w, OP_UUU_W, H4, H4, H4, fnmadd32)
RVVCALL(OPFVV3, vfnmadd_vv_d, OP_UUU_D, H8, H8, H8, fnmadd64)
-GEN_VEXT_VV_ENV(vfnmadd_vv_h, 2, 2, clearh)
-GEN_VEXT_VV_ENV(vfnmadd_vv_w, 4, 4, clearl)
-GEN_VEXT_VV_ENV(vfnmadd_vv_d, 8, 8, clearq)
+GEN_VEXT_VV_ENV(vfnmadd_vv_h, 2, 2)
+GEN_VEXT_VV_ENV(vfnmadd_vv_w, 4, 4)
+GEN_VEXT_VV_ENV(vfnmadd_vv_d, 8, 8)
RVVCALL(OPFVF3, vfnmadd_vf_h, OP_UUU_H, H2, H2, fnmadd16)
RVVCALL(OPFVF3, vfnmadd_vf_w, OP_UUU_W, H4, H4, fnmadd32)
RVVCALL(OPFVF3, vfnmadd_vf_d, OP_UUU_D, H8, H8, fnmadd64)
-GEN_VEXT_VF(vfnmadd_vf_h, 2, 2, clearh)
-GEN_VEXT_VF(vfnmadd_vf_w, 4, 4, clearl)
-GEN_VEXT_VF(vfnmadd_vf_d, 8, 8, clearq)
+GEN_VEXT_VF(vfnmadd_vf_h, 2, 2)
+GEN_VEXT_VF(vfnmadd_vf_w, 4, 4)
+GEN_VEXT_VF(vfnmadd_vf_d, 8, 8)
static uint16_t fmsub16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
{
@@ -3638,15 +3519,15 @@ static uint64_t fmsub64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
RVVCALL(OPFVV3, vfmsub_vv_h, OP_UUU_H, H2, H2, H2, fmsub16)
RVVCALL(OPFVV3, vfmsub_vv_w, OP_UUU_W, H4, H4, H4, fmsub32)
RVVCALL(OPFVV3, vfmsub_vv_d, OP_UUU_D, H8, H8, H8, fmsub64)
-GEN_VEXT_VV_ENV(vfmsub_vv_h, 2, 2, clearh)
-GEN_VEXT_VV_ENV(vfmsub_vv_w, 4, 4, clearl)
-GEN_VEXT_VV_ENV(vfmsub_vv_d, 8, 8, clearq)
+GEN_VEXT_VV_ENV(vfmsub_vv_h, 2, 2)
+GEN_VEXT_VV_ENV(vfmsub_vv_w, 4, 4)
+GEN_VEXT_VV_ENV(vfmsub_vv_d, 8, 8)
RVVCALL(OPFVF3, vfmsub_vf_h, OP_UUU_H, H2, H2, fmsub16)
RVVCALL(OPFVF3, vfmsub_vf_w, OP_UUU_W, H4, H4, fmsub32)
RVVCALL(OPFVF3, vfmsub_vf_d, OP_UUU_D, H8, H8, fmsub64)
-GEN_VEXT_VF(vfmsub_vf_h, 2, 2, clearh)
-GEN_VEXT_VF(vfmsub_vf_w, 4, 4, clearl)
-GEN_VEXT_VF(vfmsub_vf_d, 8, 8, clearq)
+GEN_VEXT_VF(vfmsub_vf_h, 2, 2)
+GEN_VEXT_VF(vfmsub_vf_w, 4, 4)
+GEN_VEXT_VF(vfmsub_vf_d, 8, 8)
static uint16_t fnmsub16(uint16_t a, uint16_t b, uint16_t d, float_status *s)
{
@@ -3666,15 +3547,15 @@ static uint64_t fnmsub64(uint64_t a, uint64_t b, uint64_t d, float_status *s)
RVVCALL(OPFVV3, vfnmsub_vv_h, OP_UUU_H, H2, H2, H2, fnmsub16)
RVVCALL(OPFVV3, vfnmsub_vv_w, OP_UUU_W, H4, H4, H4, fnmsub32)
RVVCALL(OPFVV3, vfnmsub_vv_d, OP_UUU_D, H8, H8, H8, fnmsub64)
-GEN_VEXT_VV_ENV(vfnmsub_vv_h, 2, 2, clearh)
-GEN_VEXT_VV_ENV(vfnmsub_vv_w, 4, 4, clearl)
-GEN_VEXT_VV_ENV(vfnmsub_vv_d, 8, 8, clearq)
+GEN_VEXT_VV_ENV(vfnmsub_vv_h, 2, 2)
+GEN_VEXT_VV_ENV(vfnmsub_vv_w, 4, 4)
+GEN_VEXT_VV_ENV(vfnmsub_vv_d, 8, 8)
RVVCALL(OPFVF3, vfnmsub_vf_h, OP_UUU_H, H2, H2, fnmsub16)
RVVCALL(OPFVF3, vfnmsub_vf_w, OP_UUU_W, H4, H4, fnmsub32)
RVVCALL(OPFVF3, vfnmsub_vf_d, OP_UUU_D, H8, H8, fnmsub64)
-GEN_VEXT_VF(vfnmsub_vf_h, 2, 2, clearh)
-GEN_VEXT_VF(vfnmsub_vf_w, 4, 4, clearl)
-GEN_VEXT_VF(vfnmsub_vf_d, 8, 8, clearq)
+GEN_VEXT_VF(vfnmsub_vf_h, 2, 2)
+GEN_VEXT_VF(vfnmsub_vf_w, 4, 4)
+GEN_VEXT_VF(vfnmsub_vf_d, 8, 8)
/* Vector Widening Floating-Point Fused Multiply-Add Instructions */
static uint32_t fwmacc16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
@@ -3691,12 +3572,12 @@ static uint64_t fwmacc32(uint32_t a, uint32_t b, uint64_t d, float_status *s)
RVVCALL(OPFVV3, vfwmacc_vv_h, WOP_UUU_H, H4, H2, H2, fwmacc16)
RVVCALL(OPFVV3, vfwmacc_vv_w, WOP_UUU_W, H8, H4, H4, fwmacc32)
-GEN_VEXT_VV_ENV(vfwmacc_vv_h, 2, 4, clearl)
-GEN_VEXT_VV_ENV(vfwmacc_vv_w, 4, 8, clearq)
+GEN_VEXT_VV_ENV(vfwmacc_vv_h, 2, 4)
+GEN_VEXT_VV_ENV(vfwmacc_vv_w, 4, 8)
RVVCALL(OPFVF3, vfwmacc_vf_h, WOP_UUU_H, H4, H2, fwmacc16)
RVVCALL(OPFVF3, vfwmacc_vf_w, WOP_UUU_W, H8, H4, fwmacc32)
-GEN_VEXT_VF(vfwmacc_vf_h, 2, 4, clearl)
-GEN_VEXT_VF(vfwmacc_vf_w, 4, 8, clearq)
+GEN_VEXT_VF(vfwmacc_vf_h, 2, 4)
+GEN_VEXT_VF(vfwmacc_vf_w, 4, 8)
static uint32_t fwnmacc16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
{
@@ -3714,12 +3595,12 @@ static uint64_t fwnmacc32(uint32_t a, uint32_t b, uint64_t d, float_status *s)
RVVCALL(OPFVV3, vfwnmacc_vv_h, WOP_UUU_H, H4, H2, H2, fwnmacc16)
RVVCALL(OPFVV3, vfwnmacc_vv_w, WOP_UUU_W, H8, H4, H4, fwnmacc32)
-GEN_VEXT_VV_ENV(vfwnmacc_vv_h, 2, 4, clearl)
-GEN_VEXT_VV_ENV(vfwnmacc_vv_w, 4, 8, clearq)
+GEN_VEXT_VV_ENV(vfwnmacc_vv_h, 2, 4)
+GEN_VEXT_VV_ENV(vfwnmacc_vv_w, 4, 8)
RVVCALL(OPFVF3, vfwnmacc_vf_h, WOP_UUU_H, H4, H2, fwnmacc16)
RVVCALL(OPFVF3, vfwnmacc_vf_w, WOP_UUU_W, H8, H4, fwnmacc32)
-GEN_VEXT_VF(vfwnmacc_vf_h, 2, 4, clearl)
-GEN_VEXT_VF(vfwnmacc_vf_w, 4, 8, clearq)
+GEN_VEXT_VF(vfwnmacc_vf_h, 2, 4)
+GEN_VEXT_VF(vfwnmacc_vf_w, 4, 8)
static uint32_t fwmsac16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
{
@@ -3737,12 +3618,12 @@ static uint64_t fwmsac32(uint32_t a, uint32_t b, uint64_t d, float_status *s)
RVVCALL(OPFVV3, vfwmsac_vv_h, WOP_UUU_H, H4, H2, H2, fwmsac16)
RVVCALL(OPFVV3, vfwmsac_vv_w, WOP_UUU_W, H8, H4, H4, fwmsac32)
-GEN_VEXT_VV_ENV(vfwmsac_vv_h, 2, 4, clearl)
-GEN_VEXT_VV_ENV(vfwmsac_vv_w, 4, 8, clearq)
+GEN_VEXT_VV_ENV(vfwmsac_vv_h, 2, 4)
+GEN_VEXT_VV_ENV(vfwmsac_vv_w, 4, 8)
RVVCALL(OPFVF3, vfwmsac_vf_h, WOP_UUU_H, H4, H2, fwmsac16)
RVVCALL(OPFVF3, vfwmsac_vf_w, WOP_UUU_W, H8, H4, fwmsac32)
-GEN_VEXT_VF(vfwmsac_vf_h, 2, 4, clearl)
-GEN_VEXT_VF(vfwmsac_vf_w, 4, 8, clearq)
+GEN_VEXT_VF(vfwmsac_vf_h, 2, 4)
+GEN_VEXT_VF(vfwmsac_vf_w, 4, 8)
static uint32_t fwnmsac16(uint16_t a, uint16_t b, uint32_t d, float_status *s)
{
@@ -3760,12 +3641,12 @@ static uint64_t fwnmsac32(uint32_t a, uint32_t b, uint64_t d, float_status *s)
RVVCALL(OPFVV3, vfwnmsac_vv_h, WOP_UUU_H, H4, H2, H2, fwnmsac16)
RVVCALL(OPFVV3, vfwnmsac_vv_w, WOP_UUU_W, H8, H4, H4, fwnmsac32)
-GEN_VEXT_VV_ENV(vfwnmsac_vv_h, 2, 4, clearl)
-GEN_VEXT_VV_ENV(vfwnmsac_vv_w, 4, 8, clearq)
+GEN_VEXT_VV_ENV(vfwnmsac_vv_h, 2, 4)
+GEN_VEXT_VV_ENV(vfwnmsac_vv_w, 4, 8)
RVVCALL(OPFVF3, vfwnmsac_vf_h, WOP_UUU_H, H4, H2, fwnmsac16)
RVVCALL(OPFVF3, vfwnmsac_vf_w, WOP_UUU_W, H8, H4, fwnmsac32)
-GEN_VEXT_VF(vfwnmsac_vf_h, 2, 4, clearl)
-GEN_VEXT_VF(vfwnmsac_vf_w, 4, 8, clearq)
+GEN_VEXT_VF(vfwnmsac_vf_h, 2, 4)
+GEN_VEXT_VF(vfwnmsac_vf_w, 4, 8)
/* Vector Floating-Point Square-Root Instruction */
/* (TD, T2, TX2) */
@@ -3781,11 +3662,10 @@ static void do_##NAME(void *vd, void *vs2, int i, \
*((TD *)vd + HD(i)) = OP(s2, &env->fp_status); \
}
-#define GEN_VEXT_V_ENV(NAME, ESZ, DSZ, CLEAR_FN) \
+#define GEN_VEXT_V_ENV(NAME, ESZ, DSZ) \
void HELPER(NAME)(void *vd, void *v0, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t vlmax = vext_maxsz(desc) / ESZ; \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
@@ -3799,42 +3679,41 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \
} \
do_##NAME(vd, vs2, i, env); \
} \
- CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \
}
RVVCALL(OPFVV1, vfsqrt_v_h, OP_UU_H, H2, H2, float16_sqrt)
RVVCALL(OPFVV1, vfsqrt_v_w, OP_UU_W, H4, H4, float32_sqrt)
RVVCALL(OPFVV1, vfsqrt_v_d, OP_UU_D, H8, H8, float64_sqrt)
-GEN_VEXT_V_ENV(vfsqrt_v_h, 2, 2, clearh)
-GEN_VEXT_V_ENV(vfsqrt_v_w, 4, 4, clearl)
-GEN_VEXT_V_ENV(vfsqrt_v_d, 8, 8, clearq)
+GEN_VEXT_V_ENV(vfsqrt_v_h, 2, 2)
+GEN_VEXT_V_ENV(vfsqrt_v_w, 4, 4)
+GEN_VEXT_V_ENV(vfsqrt_v_d, 8, 8)
/* Vector Floating-Point MIN/MAX Instructions */
RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minnum)
RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minnum)
RVVCALL(OPFVV2, vfmin_vv_d, OP_UUU_D, H8, H8, H8, float64_minnum)
-GEN_VEXT_VV_ENV(vfmin_vv_h, 2, 2, clearh)
-GEN_VEXT_VV_ENV(vfmin_vv_w, 4, 4, clearl)
-GEN_VEXT_VV_ENV(vfmin_vv_d, 8, 8, clearq)
+GEN_VEXT_VV_ENV(vfmin_vv_h, 2, 2)
+GEN_VEXT_VV_ENV(vfmin_vv_w, 4, 4)
+GEN_VEXT_VV_ENV(vfmin_vv_d, 8, 8)
RVVCALL(OPFVF2, vfmin_vf_h, OP_UUU_H, H2, H2, float16_minnum)
RVVCALL(OPFVF2, vfmin_vf_w, OP_UUU_W, H4, H4, float32_minnum)
RVVCALL(OPFVF2, vfmin_vf_d, OP_UUU_D, H8, H8, float64_minnum)
-GEN_VEXT_VF(vfmin_vf_h, 2, 2, clearh)
-GEN_VEXT_VF(vfmin_vf_w, 4, 4, clearl)
-GEN_VEXT_VF(vfmin_vf_d, 8, 8, clearq)
+GEN_VEXT_VF(vfmin_vf_h, 2, 2)
+GEN_VEXT_VF(vfmin_vf_w, 4, 4)
+GEN_VEXT_VF(vfmin_vf_d, 8, 8)
RVVCALL(OPFVV2, vfmax_vv_h, OP_UUU_H, H2, H2, H2, float16_maxnum)
RVVCALL(OPFVV2, vfmax_vv_w, OP_UUU_W, H4, H4, H4, float32_maxnum)
RVVCALL(OPFVV2, vfmax_vv_d, OP_UUU_D, H8, H8, H8, float64_maxnum)
-GEN_VEXT_VV_ENV(vfmax_vv_h, 2, 2, clearh)
-GEN_VEXT_VV_ENV(vfmax_vv_w, 4, 4, clearl)
-GEN_VEXT_VV_ENV(vfmax_vv_d, 8, 8, clearq)
+GEN_VEXT_VV_ENV(vfmax_vv_h, 2, 2)
+GEN_VEXT_VV_ENV(vfmax_vv_w, 4, 4)
+GEN_VEXT_VV_ENV(vfmax_vv_d, 8, 8)
RVVCALL(OPFVF2, vfmax_vf_h, OP_UUU_H, H2, H2, float16_maxnum)
RVVCALL(OPFVF2, vfmax_vf_w, OP_UUU_W, H4, H4, float32_maxnum)
RVVCALL(OPFVF2, vfmax_vf_d, OP_UUU_D, H8, H8, float64_maxnum)
-GEN_VEXT_VF(vfmax_vf_h, 2, 2, clearh)
-GEN_VEXT_VF(vfmax_vf_w, 4, 4, clearl)
-GEN_VEXT_VF(vfmax_vf_d, 8, 8, clearq)
+GEN_VEXT_VF(vfmax_vf_h, 2, 2)
+GEN_VEXT_VF(vfmax_vf_w, 4, 4)
+GEN_VEXT_VF(vfmax_vf_d, 8, 8)
/* Vector Floating-Point Sign-Injection Instructions */
static uint16_t fsgnj16(uint16_t a, uint16_t b, float_status *s)
@@ -3855,15 +3734,15 @@ static uint64_t fsgnj64(uint64_t a, uint64_t b, float_status *s)
RVVCALL(OPFVV2, vfsgnj_vv_h, OP_UUU_H, H2, H2, H2, fsgnj16)
RVVCALL(OPFVV2, vfsgnj_vv_w, OP_UUU_W, H4, H4, H4, fsgnj32)
RVVCALL(OPFVV2, vfsgnj_vv_d, OP_UUU_D, H8, H8, H8, fsgnj64)
-GEN_VEXT_VV_ENV(vfsgnj_vv_h, 2, 2, clearh)
-GEN_VEXT_VV_ENV(vfsgnj_vv_w, 4, 4, clearl)
-GEN_VEXT_VV_ENV(vfsgnj_vv_d, 8, 8, clearq)
+GEN_VEXT_VV_ENV(vfsgnj_vv_h, 2, 2)
+GEN_VEXT_VV_ENV(vfsgnj_vv_w, 4, 4)
+GEN_VEXT_VV_ENV(vfsgnj_vv_d, 8, 8)
RVVCALL(OPFVF2, vfsgnj_vf_h, OP_UUU_H, H2, H2, fsgnj16)
RVVCALL(OPFVF2, vfsgnj_vf_w, OP_UUU_W, H4, H4, fsgnj32)
RVVCALL(OPFVF2, vfsgnj_vf_d, OP_UUU_D, H8, H8, fsgnj64)
-GEN_VEXT_VF(vfsgnj_vf_h, 2, 2, clearh)
-GEN_VEXT_VF(vfsgnj_vf_w, 4, 4, clearl)
-GEN_VEXT_VF(vfsgnj_vf_d, 8, 8, clearq)
+GEN_VEXT_VF(vfsgnj_vf_h, 2, 2)
+GEN_VEXT_VF(vfsgnj_vf_w, 4, 4)
+GEN_VEXT_VF(vfsgnj_vf_d, 8, 8)
static uint16_t fsgnjn16(uint16_t a, uint16_t b, float_status *s)
{
@@ -3883,15 +3762,15 @@ static uint64_t fsgnjn64(uint64_t a, uint64_t b, float_status *s)
RVVCALL(OPFVV2, vfsgnjn_vv_h, OP_UUU_H, H2, H2, H2, fsgnjn16)
RVVCALL(OPFVV2, vfsgnjn_vv_w, OP_UUU_W, H4, H4, H4, fsgnjn32)
RVVCALL(OPFVV2, vfsgnjn_vv_d, OP_UUU_D, H8, H8, H8, fsgnjn64)
-GEN_VEXT_VV_ENV(vfsgnjn_vv_h, 2, 2, clearh)
-GEN_VEXT_VV_ENV(vfsgnjn_vv_w, 4, 4, clearl)
-GEN_VEXT_VV_ENV(vfsgnjn_vv_d, 8, 8, clearq)
+GEN_VEXT_VV_ENV(vfsgnjn_vv_h, 2, 2)
+GEN_VEXT_VV_ENV(vfsgnjn_vv_w, 4, 4)
+GEN_VEXT_VV_ENV(vfsgnjn_vv_d, 8, 8)
RVVCALL(OPFVF2, vfsgnjn_vf_h, OP_UUU_H, H2, H2, fsgnjn16)
RVVCALL(OPFVF2, vfsgnjn_vf_w, OP_UUU_W, H4, H4, fsgnjn32)
RVVCALL(OPFVF2, vfsgnjn_vf_d, OP_UUU_D, H8, H8, fsgnjn64)
-GEN_VEXT_VF(vfsgnjn_vf_h, 2, 2, clearh)
-GEN_VEXT_VF(vfsgnjn_vf_w, 4, 4, clearl)
-GEN_VEXT_VF(vfsgnjn_vf_d, 8, 8, clearq)
+GEN_VEXT_VF(vfsgnjn_vf_h, 2, 2)
+GEN_VEXT_VF(vfsgnjn_vf_w, 4, 4)
+GEN_VEXT_VF(vfsgnjn_vf_d, 8, 8)
static uint16_t fsgnjx16(uint16_t a, uint16_t b, float_status *s)
{
@@ -3911,15 +3790,15 @@ static uint64_t fsgnjx64(uint64_t a, uint64_t b, float_status *s)
RVVCALL(OPFVV2, vfsgnjx_vv_h, OP_UUU_H, H2, H2, H2, fsgnjx16)
RVVCALL(OPFVV2, vfsgnjx_vv_w, OP_UUU_W, H4, H4, H4, fsgnjx32)
RVVCALL(OPFVV2, vfsgnjx_vv_d, OP_UUU_D, H8, H8, H8, fsgnjx64)
-GEN_VEXT_VV_ENV(vfsgnjx_vv_h, 2, 2, clearh)
-GEN_VEXT_VV_ENV(vfsgnjx_vv_w, 4, 4, clearl)
-GEN_VEXT_VV_ENV(vfsgnjx_vv_d, 8, 8, clearq)
+GEN_VEXT_VV_ENV(vfsgnjx_vv_h, 2, 2)
+GEN_VEXT_VV_ENV(vfsgnjx_vv_w, 4, 4)
+GEN_VEXT_VV_ENV(vfsgnjx_vv_d, 8, 8)
RVVCALL(OPFVF2, vfsgnjx_vf_h, OP_UUU_H, H2, H2, fsgnjx16)
RVVCALL(OPFVF2, vfsgnjx_vf_w, OP_UUU_W, H4, H4, fsgnjx32)
RVVCALL(OPFVF2, vfsgnjx_vf_d, OP_UUU_D, H8, H8, fsgnjx64)
-GEN_VEXT_VF(vfsgnjx_vf_h, 2, 2, clearh)
-GEN_VEXT_VF(vfsgnjx_vf_w, 4, 4, clearl)
-GEN_VEXT_VF(vfsgnjx_vf_d, 8, 8, clearq)
+GEN_VEXT_VF(vfsgnjx_vf_h, 2, 2)
+GEN_VEXT_VF(vfsgnjx_vf_w, 4, 4)
+GEN_VEXT_VF(vfsgnjx_vf_d, 8, 8)
/* Vector Floating-Point Compare Instructions */
#define GEN_VEXT_CMP_VV_ENV(NAME, ETYPE, H, DO_OP) \
@@ -4076,11 +3955,10 @@ static void do_##NAME(void *vd, void *vs2, int i) \
*((TD *)vd + HD(i)) = OP(s2); \
}
-#define GEN_VEXT_V(NAME, ESZ, DSZ, CLEAR_FN) \
+#define GEN_VEXT_V(NAME, ESZ, DSZ) \
void HELPER(NAME)(void *vd, void *v0, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t vlmax = vext_maxsz(desc) / ESZ; \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
@@ -4091,7 +3969,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \
} \
do_##NAME(vd, vs2, i); \
} \
- CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \
}
target_ulong fclass_h(uint64_t frs1)
@@ -4154,19 +4031,17 @@ target_ulong fclass_d(uint64_t frs1)
RVVCALL(OPIVV1, vfclass_v_h, OP_UU_H, H2, H2, fclass_h)
RVVCALL(OPIVV1, vfclass_v_w, OP_UU_W, H4, H4, fclass_s)
RVVCALL(OPIVV1, vfclass_v_d, OP_UU_D, H8, H8, fclass_d)
-GEN_VEXT_V(vfclass_v_h, 2, 2, clearh)
-GEN_VEXT_V(vfclass_v_w, 4, 4, clearl)
-GEN_VEXT_V(vfclass_v_d, 8, 8, clearq)
+GEN_VEXT_V(vfclass_v_h, 2, 2)
+GEN_VEXT_V(vfclass_v_w, 4, 4)
+GEN_VEXT_V(vfclass_v_d, 8, 8)
/* Vector Floating-Point Merge Instruction */
-#define GEN_VFMERGE_VF(NAME, ETYPE, H, CLEAR_FN) \
+#define GEN_VFMERGE_VF(NAME, ETYPE, H) \
void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
- uint32_t esz = sizeof(ETYPE); \
- uint32_t vlmax = vext_maxsz(desc) / esz; \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
@@ -4174,45 +4049,44 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
*((ETYPE *)vd + H(i)) \
= (!vm && !vext_elem_mask(v0, i) ? s2 : s1); \
} \
- CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \
}
-GEN_VFMERGE_VF(vfmerge_vfm_h, int16_t, H2, clearh)
-GEN_VFMERGE_VF(vfmerge_vfm_w, int32_t, H4, clearl)
-GEN_VFMERGE_VF(vfmerge_vfm_d, int64_t, H8, clearq)
+GEN_VFMERGE_VF(vfmerge_vfm_h, int16_t, H2)
+GEN_VFMERGE_VF(vfmerge_vfm_w, int32_t, H4)
+GEN_VFMERGE_VF(vfmerge_vfm_d, int64_t, H8)
/* Single-Width Floating-Point/Integer Type-Convert Instructions */
/* vfcvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer. */
RVVCALL(OPFVV1, vfcvt_xu_f_v_h, OP_UU_H, H2, H2, float16_to_uint16)
RVVCALL(OPFVV1, vfcvt_xu_f_v_w, OP_UU_W, H4, H4, float32_to_uint32)
RVVCALL(OPFVV1, vfcvt_xu_f_v_d, OP_UU_D, H8, H8, float64_to_uint64)
-GEN_VEXT_V_ENV(vfcvt_xu_f_v_h, 2, 2, clearh)
-GEN_VEXT_V_ENV(vfcvt_xu_f_v_w, 4, 4, clearl)
-GEN_VEXT_V_ENV(vfcvt_xu_f_v_d, 8, 8, clearq)
+GEN_VEXT_V_ENV(vfcvt_xu_f_v_h, 2, 2)
+GEN_VEXT_V_ENV(vfcvt_xu_f_v_w, 4, 4)
+GEN_VEXT_V_ENV(vfcvt_xu_f_v_d, 8, 8)
/* vfcvt.x.f.v vd, vs2, vm # Convert float to signed integer. */
RVVCALL(OPFVV1, vfcvt_x_f_v_h, OP_UU_H, H2, H2, float16_to_int16)
RVVCALL(OPFVV1, vfcvt_x_f_v_w, OP_UU_W, H4, H4, float32_to_int32)
RVVCALL(OPFVV1, vfcvt_x_f_v_d, OP_UU_D, H8, H8, float64_to_int64)
-GEN_VEXT_V_ENV(vfcvt_x_f_v_h, 2, 2, clearh)
-GEN_VEXT_V_ENV(vfcvt_x_f_v_w, 4, 4, clearl)
-GEN_VEXT_V_ENV(vfcvt_x_f_v_d, 8, 8, clearq)
+GEN_VEXT_V_ENV(vfcvt_x_f_v_h, 2, 2)
+GEN_VEXT_V_ENV(vfcvt_x_f_v_w, 4, 4)
+GEN_VEXT_V_ENV(vfcvt_x_f_v_d, 8, 8)
/* vfcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to float. */
RVVCALL(OPFVV1, vfcvt_f_xu_v_h, OP_UU_H, H2, H2, uint16_to_float16)
RVVCALL(OPFVV1, vfcvt_f_xu_v_w, OP_UU_W, H4, H4, uint32_to_float32)
RVVCALL(OPFVV1, vfcvt_f_xu_v_d, OP_UU_D, H8, H8, uint64_to_float64)
-GEN_VEXT_V_ENV(vfcvt_f_xu_v_h, 2, 2, clearh)
-GEN_VEXT_V_ENV(vfcvt_f_xu_v_w, 4, 4, clearl)
-GEN_VEXT_V_ENV(vfcvt_f_xu_v_d, 8, 8, clearq)
+GEN_VEXT_V_ENV(vfcvt_f_xu_v_h, 2, 2)
+GEN_VEXT_V_ENV(vfcvt_f_xu_v_w, 4, 4)
+GEN_VEXT_V_ENV(vfcvt_f_xu_v_d, 8, 8)
/* vfcvt.f.x.v vd, vs2, vm # Convert integer to float. */
RVVCALL(OPFVV1, vfcvt_f_x_v_h, OP_UU_H, H2, H2, int16_to_float16)
RVVCALL(OPFVV1, vfcvt_f_x_v_w, OP_UU_W, H4, H4, int32_to_float32)
RVVCALL(OPFVV1, vfcvt_f_x_v_d, OP_UU_D, H8, H8, int64_to_float64)
-GEN_VEXT_V_ENV(vfcvt_f_x_v_h, 2, 2, clearh)
-GEN_VEXT_V_ENV(vfcvt_f_x_v_w, 4, 4, clearl)
-GEN_VEXT_V_ENV(vfcvt_f_x_v_d, 8, 8, clearq)
+GEN_VEXT_V_ENV(vfcvt_f_x_v_h, 2, 2)
+GEN_VEXT_V_ENV(vfcvt_f_x_v_w, 4, 4)
+GEN_VEXT_V_ENV(vfcvt_f_x_v_d, 8, 8)
/* Widening Floating-Point/Integer Type-Convert Instructions */
/* (TD, T2, TX2) */
@@ -4221,26 +4095,26 @@ GEN_VEXT_V_ENV(vfcvt_f_x_v_d, 8, 8, clearq)
/* vfwcvt.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer.*/
RVVCALL(OPFVV1, vfwcvt_xu_f_v_h, WOP_UU_H, H4, H2, float16_to_uint32)
RVVCALL(OPFVV1, vfwcvt_xu_f_v_w, WOP_UU_W, H8, H4, float32_to_uint64)
-GEN_VEXT_V_ENV(vfwcvt_xu_f_v_h, 2, 4, clearl)
-GEN_VEXT_V_ENV(vfwcvt_xu_f_v_w, 4, 8, clearq)
+GEN_VEXT_V_ENV(vfwcvt_xu_f_v_h, 2, 4)
+GEN_VEXT_V_ENV(vfwcvt_xu_f_v_w, 4, 8)
/* vfwcvt.x.f.v vd, vs2, vm # Convert float to double-width signed integer. */
RVVCALL(OPFVV1, vfwcvt_x_f_v_h, WOP_UU_H, H4, H2, float16_to_int32)
RVVCALL(OPFVV1, vfwcvt_x_f_v_w, WOP_UU_W, H8, H4, float32_to_int64)
-GEN_VEXT_V_ENV(vfwcvt_x_f_v_h, 2, 4, clearl)
-GEN_VEXT_V_ENV(vfwcvt_x_f_v_w, 4, 8, clearq)
+GEN_VEXT_V_ENV(vfwcvt_x_f_v_h, 2, 4)
+GEN_VEXT_V_ENV(vfwcvt_x_f_v_w, 4, 8)
/* vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to double-width float */
RVVCALL(OPFVV1, vfwcvt_f_xu_v_h, WOP_UU_H, H4, H2, uint16_to_float32)
RVVCALL(OPFVV1, vfwcvt_f_xu_v_w, WOP_UU_W, H8, H4, uint32_to_float64)
-GEN_VEXT_V_ENV(vfwcvt_f_xu_v_h, 2, 4, clearl)
-GEN_VEXT_V_ENV(vfwcvt_f_xu_v_w, 4, 8, clearq)
+GEN_VEXT_V_ENV(vfwcvt_f_xu_v_h, 2, 4)
+GEN_VEXT_V_ENV(vfwcvt_f_xu_v_w, 4, 8)
/* vfwcvt.f.x.v vd, vs2, vm # Convert integer to double-width float. */
RVVCALL(OPFVV1, vfwcvt_f_x_v_h, WOP_UU_H, H4, H2, int16_to_float32)
RVVCALL(OPFVV1, vfwcvt_f_x_v_w, WOP_UU_W, H8, H4, int32_to_float64)
-GEN_VEXT_V_ENV(vfwcvt_f_x_v_h, 2, 4, clearl)
-GEN_VEXT_V_ENV(vfwcvt_f_x_v_w, 4, 8, clearq)
+GEN_VEXT_V_ENV(vfwcvt_f_x_v_h, 2, 4)
+GEN_VEXT_V_ENV(vfwcvt_f_x_v_w, 4, 8)
/*
* vfwcvt.f.f.v vd, vs2, vm #
@@ -4253,8 +4127,8 @@ static uint32_t vfwcvtffv16(uint16_t a, float_status *s)
RVVCALL(OPFVV1, vfwcvt_f_f_v_h, WOP_UU_H, H4, H2, vfwcvtffv16)
RVVCALL(OPFVV1, vfwcvt_f_f_v_w, WOP_UU_W, H8, H4, float32_to_float64)
-GEN_VEXT_V_ENV(vfwcvt_f_f_v_h, 2, 4, clearl)
-GEN_VEXT_V_ENV(vfwcvt_f_f_v_w, 4, 8, clearq)
+GEN_VEXT_V_ENV(vfwcvt_f_f_v_h, 2, 4)
+GEN_VEXT_V_ENV(vfwcvt_f_f_v_w, 4, 8)
/* Narrowing Floating-Point/Integer Type-Convert Instructions */
/* (TD, T2, TX2) */
@@ -4263,26 +4137,26 @@ GEN_VEXT_V_ENV(vfwcvt_f_f_v_w, 4, 8, clearq)
/* vfncvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer. */
RVVCALL(OPFVV1, vfncvt_xu_f_v_h, NOP_UU_H, H2, H4, float32_to_uint16)
RVVCALL(OPFVV1, vfncvt_xu_f_v_w, NOP_UU_W, H4, H8, float64_to_uint32)
-GEN_VEXT_V_ENV(vfncvt_xu_f_v_h, 2, 2, clearh)
-GEN_VEXT_V_ENV(vfncvt_xu_f_v_w, 4, 4, clearl)
+GEN_VEXT_V_ENV(vfncvt_xu_f_v_h, 2, 2)
+GEN_VEXT_V_ENV(vfncvt_xu_f_v_w, 4, 4)
/* vfncvt.x.f.v vd, vs2, vm # Convert double-width float to signed integer. */
RVVCALL(OPFVV1, vfncvt_x_f_v_h, NOP_UU_H, H2, H4, float32_to_int16)
RVVCALL(OPFVV1, vfncvt_x_f_v_w, NOP_UU_W, H4, H8, float64_to_int32)
-GEN_VEXT_V_ENV(vfncvt_x_f_v_h, 2, 2, clearh)
-GEN_VEXT_V_ENV(vfncvt_x_f_v_w, 4, 4, clearl)
+GEN_VEXT_V_ENV(vfncvt_x_f_v_h, 2, 2)
+GEN_VEXT_V_ENV(vfncvt_x_f_v_w, 4, 4)
/* vfncvt.f.xu.v vd, vs2, vm # Convert double-width unsigned integer to float */
RVVCALL(OPFVV1, vfncvt_f_xu_v_h, NOP_UU_H, H2, H4, uint32_to_float16)
RVVCALL(OPFVV1, vfncvt_f_xu_v_w, NOP_UU_W, H4, H8, uint64_to_float32)
-GEN_VEXT_V_ENV(vfncvt_f_xu_v_h, 2, 2, clearh)
-GEN_VEXT_V_ENV(vfncvt_f_xu_v_w, 4, 4, clearl)
+GEN_VEXT_V_ENV(vfncvt_f_xu_v_h, 2, 2)
+GEN_VEXT_V_ENV(vfncvt_f_xu_v_w, 4, 4)
/* vfncvt.f.x.v vd, vs2, vm # Convert double-width integer to float. */
RVVCALL(OPFVV1, vfncvt_f_x_v_h, NOP_UU_H, H2, H4, int32_to_float16)
RVVCALL(OPFVV1, vfncvt_f_x_v_w, NOP_UU_W, H4, H8, int64_to_float32)
-GEN_VEXT_V_ENV(vfncvt_f_x_v_h, 2, 2, clearh)
-GEN_VEXT_V_ENV(vfncvt_f_x_v_w, 4, 4, clearl)
+GEN_VEXT_V_ENV(vfncvt_f_x_v_h, 2, 2)
+GEN_VEXT_V_ENV(vfncvt_f_x_v_w, 4, 4)
/* vfncvt.f.f.v vd, vs2, vm # Convert double float to single-width float. */
static uint16_t vfncvtffv16(uint32_t a, float_status *s)
@@ -4292,21 +4166,20 @@ static uint16_t vfncvtffv16(uint32_t a, float_status *s)
RVVCALL(OPFVV1, vfncvt_f_f_v_h, NOP_UU_H, H2, H4, vfncvtffv16)
RVVCALL(OPFVV1, vfncvt_f_f_v_w, NOP_UU_W, H4, H8, float64_to_float32)
-GEN_VEXT_V_ENV(vfncvt_f_f_v_h, 2, 2, clearh)
-GEN_VEXT_V_ENV(vfncvt_f_f_v_w, 4, 4, clearl)
+GEN_VEXT_V_ENV(vfncvt_f_f_v_h, 2, 2)
+GEN_VEXT_V_ENV(vfncvt_f_f_v_w, 4, 4)
/*
*** Vector Reduction Operations
*/
/* Vector Single-Width Integer Reduction Instructions */
-#define GEN_VEXT_RED(NAME, TD, TS2, HD, HS2, OP, CLEAR_FN)\
+#define GEN_VEXT_RED(NAME, TD, TS2, HD, HS2, OP) \
void HELPER(NAME)(void *vd, void *v0, void *vs1, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
- uint32_t tot = env_archcpu(env)->cfg.vlen / 8; \
TD s1 = *((TD *)vs1 + HD(0)); \
\
for (i = 0; i < vl; i++) { \
@@ -4317,70 +4190,69 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
s1 = OP(s1, (TD)s2); \
} \
*((TD *)vd + HD(0)) = s1; \
- CLEAR_FN(vd, 1, sizeof(TD), tot); \
}
/* vd[0] = sum(vs1[0], vs2[*]) */
-GEN_VEXT_RED(vredsum_vs_b, int8_t, int8_t, H1, H1, DO_ADD, clearb)
-GEN_VEXT_RED(vredsum_vs_h, int16_t, int16_t, H2, H2, DO_ADD, clearh)
-GEN_VEXT_RED(vredsum_vs_w, int32_t, int32_t, H4, H4, DO_ADD, clearl)
-GEN_VEXT_RED(vredsum_vs_d, int64_t, int64_t, H8, H8, DO_ADD, clearq)
+GEN_VEXT_RED(vredsum_vs_b, int8_t, int8_t, H1, H1, DO_ADD)
+GEN_VEXT_RED(vredsum_vs_h, int16_t, int16_t, H2, H2, DO_ADD)
+GEN_VEXT_RED(vredsum_vs_w, int32_t, int32_t, H4, H4, DO_ADD)
+GEN_VEXT_RED(vredsum_vs_d, int64_t, int64_t, H8, H8, DO_ADD)
/* vd[0] = maxu(vs1[0], vs2[*]) */
-GEN_VEXT_RED(vredmaxu_vs_b, uint8_t, uint8_t, H1, H1, DO_MAX, clearb)
-GEN_VEXT_RED(vredmaxu_vs_h, uint16_t, uint16_t, H2, H2, DO_MAX, clearh)
-GEN_VEXT_RED(vredmaxu_vs_w, uint32_t, uint32_t, H4, H4, DO_MAX, clearl)
-GEN_VEXT_RED(vredmaxu_vs_d, uint64_t, uint64_t, H8, H8, DO_MAX, clearq)
+GEN_VEXT_RED(vredmaxu_vs_b, uint8_t, uint8_t, H1, H1, DO_MAX)
+GEN_VEXT_RED(vredmaxu_vs_h, uint16_t, uint16_t, H2, H2, DO_MAX)
+GEN_VEXT_RED(vredmaxu_vs_w, uint32_t, uint32_t, H4, H4, DO_MAX)
+GEN_VEXT_RED(vredmaxu_vs_d, uint64_t, uint64_t, H8, H8, DO_MAX)
/* vd[0] = max(vs1[0], vs2[*]) */
-GEN_VEXT_RED(vredmax_vs_b, int8_t, int8_t, H1, H1, DO_MAX, clearb)
-GEN_VEXT_RED(vredmax_vs_h, int16_t, int16_t, H2, H2, DO_MAX, clearh)
-GEN_VEXT_RED(vredmax_vs_w, int32_t, int32_t, H4, H4, DO_MAX, clearl)
-GEN_VEXT_RED(vredmax_vs_d, int64_t, int64_t, H8, H8, DO_MAX, clearq)
+GEN_VEXT_RED(vredmax_vs_b, int8_t, int8_t, H1, H1, DO_MAX)
+GEN_VEXT_RED(vredmax_vs_h, int16_t, int16_t, H2, H2, DO_MAX)
+GEN_VEXT_RED(vredmax_vs_w, int32_t, int32_t, H4, H4, DO_MAX)
+GEN_VEXT_RED(vredmax_vs_d, int64_t, int64_t, H8, H8, DO_MAX)
/* vd[0] = minu(vs1[0], vs2[*]) */
-GEN_VEXT_RED(vredminu_vs_b, uint8_t, uint8_t, H1, H1, DO_MIN, clearb)
-GEN_VEXT_RED(vredminu_vs_h, uint16_t, uint16_t, H2, H2, DO_MIN, clearh)
-GEN_VEXT_RED(vredminu_vs_w, uint32_t, uint32_t, H4, H4, DO_MIN, clearl)
-GEN_VEXT_RED(vredminu_vs_d, uint64_t, uint64_t, H8, H8, DO_MIN, clearq)
+GEN_VEXT_RED(vredminu_vs_b, uint8_t, uint8_t, H1, H1, DO_MIN)
+GEN_VEXT_RED(vredminu_vs_h, uint16_t, uint16_t, H2, H2, DO_MIN)
+GEN_VEXT_RED(vredminu_vs_w, uint32_t, uint32_t, H4, H4, DO_MIN)
+GEN_VEXT_RED(vredminu_vs_d, uint64_t, uint64_t, H8, H8, DO_MIN)
/* vd[0] = min(vs1[0], vs2[*]) */
-GEN_VEXT_RED(vredmin_vs_b, int8_t, int8_t, H1, H1, DO_MIN, clearb)
-GEN_VEXT_RED(vredmin_vs_h, int16_t, int16_t, H2, H2, DO_MIN, clearh)
-GEN_VEXT_RED(vredmin_vs_w, int32_t, int32_t, H4, H4, DO_MIN, clearl)
-GEN_VEXT_RED(vredmin_vs_d, int64_t, int64_t, H8, H8, DO_MIN, clearq)
+GEN_VEXT_RED(vredmin_vs_b, int8_t, int8_t, H1, H1, DO_MIN)
+GEN_VEXT_RED(vredmin_vs_h, int16_t, int16_t, H2, H2, DO_MIN)
+GEN_VEXT_RED(vredmin_vs_w, int32_t, int32_t, H4, H4, DO_MIN)
+GEN_VEXT_RED(vredmin_vs_d, int64_t, int64_t, H8, H8, DO_MIN)
/* vd[0] = and(vs1[0], vs2[*]) */
-GEN_VEXT_RED(vredand_vs_b, int8_t, int8_t, H1, H1, DO_AND, clearb)
-GEN_VEXT_RED(vredand_vs_h, int16_t, int16_t, H2, H2, DO_AND, clearh)
-GEN_VEXT_RED(vredand_vs_w, int32_t, int32_t, H4, H4, DO_AND, clearl)
-GEN_VEXT_RED(vredand_vs_d, int64_t, int64_t, H8, H8, DO_AND, clearq)
+GEN_VEXT_RED(vredand_vs_b, int8_t, int8_t, H1, H1, DO_AND)
+GEN_VEXT_RED(vredand_vs_h, int16_t, int16_t, H2, H2, DO_AND)
+GEN_VEXT_RED(vredand_vs_w, int32_t, int32_t, H4, H4, DO_AND)
+GEN_VEXT_RED(vredand_vs_d, int64_t, int64_t, H8, H8, DO_AND)
/* vd[0] = or(vs1[0], vs2[*]) */
-GEN_VEXT_RED(vredor_vs_b, int8_t, int8_t, H1, H1, DO_OR, clearb)
-GEN_VEXT_RED(vredor_vs_h, int16_t, int16_t, H2, H2, DO_OR, clearh)
-GEN_VEXT_RED(vredor_vs_w, int32_t, int32_t, H4, H4, DO_OR, clearl)
-GEN_VEXT_RED(vredor_vs_d, int64_t, int64_t, H8, H8, DO_OR, clearq)
+GEN_VEXT_RED(vredor_vs_b, int8_t, int8_t, H1, H1, DO_OR)
+GEN_VEXT_RED(vredor_vs_h, int16_t, int16_t, H2, H2, DO_OR)
+GEN_VEXT_RED(vredor_vs_w, int32_t, int32_t, H4, H4, DO_OR)
+GEN_VEXT_RED(vredor_vs_d, int64_t, int64_t, H8, H8, DO_OR)
/* vd[0] = xor(vs1[0], vs2[*]) */
-GEN_VEXT_RED(vredxor_vs_b, int8_t, int8_t, H1, H1, DO_XOR, clearb)
-GEN_VEXT_RED(vredxor_vs_h, int16_t, int16_t, H2, H2, DO_XOR, clearh)
-GEN_VEXT_RED(vredxor_vs_w, int32_t, int32_t, H4, H4, DO_XOR, clearl)
-GEN_VEXT_RED(vredxor_vs_d, int64_t, int64_t, H8, H8, DO_XOR, clearq)
+GEN_VEXT_RED(vredxor_vs_b, int8_t, int8_t, H1, H1, DO_XOR)
+GEN_VEXT_RED(vredxor_vs_h, int16_t, int16_t, H2, H2, DO_XOR)
+GEN_VEXT_RED(vredxor_vs_w, int32_t, int32_t, H4, H4, DO_XOR)
+GEN_VEXT_RED(vredxor_vs_d, int64_t, int64_t, H8, H8, DO_XOR)
/* Vector Widening Integer Reduction Instructions */
/* signed sum reduction into double-width accumulator */
-GEN_VEXT_RED(vwredsum_vs_b, int16_t, int8_t, H2, H1, DO_ADD, clearh)
-GEN_VEXT_RED(vwredsum_vs_h, int32_t, int16_t, H4, H2, DO_ADD, clearl)
-GEN_VEXT_RED(vwredsum_vs_w, int64_t, int32_t, H8, H4, DO_ADD, clearq)
+GEN_VEXT_RED(vwredsum_vs_b, int16_t, int8_t, H2, H1, DO_ADD)
+GEN_VEXT_RED(vwredsum_vs_h, int32_t, int16_t, H4, H2, DO_ADD)
+GEN_VEXT_RED(vwredsum_vs_w, int64_t, int32_t, H8, H4, DO_ADD)
/* Unsigned sum reduction into double-width accumulator */
-GEN_VEXT_RED(vwredsumu_vs_b, uint16_t, uint8_t, H2, H1, DO_ADD, clearh)
-GEN_VEXT_RED(vwredsumu_vs_h, uint32_t, uint16_t, H4, H2, DO_ADD, clearl)
-GEN_VEXT_RED(vwredsumu_vs_w, uint64_t, uint32_t, H8, H4, DO_ADD, clearq)
+GEN_VEXT_RED(vwredsumu_vs_b, uint16_t, uint8_t, H2, H1, DO_ADD)
+GEN_VEXT_RED(vwredsumu_vs_h, uint32_t, uint16_t, H4, H2, DO_ADD)
+GEN_VEXT_RED(vwredsumu_vs_w, uint64_t, uint32_t, H8, H4, DO_ADD)
/* Vector Single-Width Floating-Point Reduction Instructions */
-#define GEN_VEXT_FRED(NAME, TD, TS2, HD, HS2, OP, CLEAR_FN)\
+#define GEN_VEXT_FRED(NAME, TD, TS2, HD, HS2, OP) \
void HELPER(NAME)(void *vd, void *v0, void *vs1, \
void *vs2, CPURISCVState *env, \
uint32_t desc) \
@@ -4388,7 +4260,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
- uint32_t tot = env_archcpu(env)->cfg.vlen / 8; \
TD s1 = *((TD *)vs1 + HD(0)); \
\
for (i = 0; i < vl; i++) { \
@@ -4399,23 +4270,22 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
s1 = OP(s1, (TD)s2, &env->fp_status); \
} \
*((TD *)vd + HD(0)) = s1; \
- CLEAR_FN(vd, 1, sizeof(TD), tot); \
}
/* Unordered sum */
-GEN_VEXT_FRED(vfredsum_vs_h, uint16_t, uint16_t, H2, H2, float16_add, clearh)
-GEN_VEXT_FRED(vfredsum_vs_w, uint32_t, uint32_t, H4, H4, float32_add, clearl)
-GEN_VEXT_FRED(vfredsum_vs_d, uint64_t, uint64_t, H8, H8, float64_add, clearq)
+GEN_VEXT_FRED(vfredsum_vs_h, uint16_t, uint16_t, H2, H2, float16_add)
+GEN_VEXT_FRED(vfredsum_vs_w, uint32_t, uint32_t, H4, H4, float32_add)
+GEN_VEXT_FRED(vfredsum_vs_d, uint64_t, uint64_t, H8, H8, float64_add)
/* Maximum value */
-GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2, float16_maxnum, clearh)
-GEN_VEXT_FRED(vfredmax_vs_w, uint32_t, uint32_t, H4, H4, float32_maxnum, clearl)
-GEN_VEXT_FRED(vfredmax_vs_d, uint64_t, uint64_t, H8, H8, float64_maxnum, clearq)
+GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2, float16_maxnum)
+GEN_VEXT_FRED(vfredmax_vs_w, uint32_t, uint32_t, H4, H4, float32_maxnum)
+GEN_VEXT_FRED(vfredmax_vs_d, uint64_t, uint64_t, H8, H8, float64_maxnum)
/* Minimum value */
-GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2, float16_minnum, clearh)
-GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4, float32_minnum, clearl)
-GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, float64_minnum, clearq)
+GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2, float16_minnum)
+GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4, float32_minnum)
+GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, float64_minnum)
/* Vector Widening Floating-Point Reduction Instructions */
/* Unordered reduce 2*SEW = 2*SEW + sum(promote(SEW)) */
@@ -4425,7 +4295,6 @@ void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1,
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
uint32_t i;
- uint32_t tot = env_archcpu(env)->cfg.vlen / 8;
uint32_t s1 = *((uint32_t *)vs1 + H4(0));
for (i = 0; i < vl; i++) {
@@ -4437,7 +4306,6 @@ void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1,
&env->fp_status);
}
*((uint32_t *)vd + H4(0)) = s1;
- clearl(vd, 1, sizeof(uint32_t), tot);
}
void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1,
@@ -4446,7 +4314,6 @@ void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1,
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
uint32_t i;
- uint32_t tot = env_archcpu(env)->cfg.vlen / 8;
uint64_t s1 = *((uint64_t *)vs1);
for (i = 0; i < vl; i++) {
@@ -4458,7 +4325,6 @@ void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1,
&env->fp_status);
}
*((uint64_t *)vd) = s1;
- clearq(vd, 1, sizeof(uint64_t), tot);
}
/*
@@ -4600,11 +4466,10 @@ void HELPER(vmsof_m)(void *vd, void *v0, void *vs2, CPURISCVState *env,
}
/* Vector Iota Instruction */
-#define GEN_VEXT_VIOTA_M(NAME, ETYPE, H, CLEAR_FN) \
+#define GEN_VEXT_VIOTA_M(NAME, ETYPE, H) \
void HELPER(NAME)(void *vd, void *v0, void *vs2, CPURISCVState *env, \
uint32_t desc) \
{ \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t sum = 0; \
@@ -4619,19 +4484,17 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, CPURISCVState *env, \
sum++; \
} \
} \
- CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
}
-GEN_VEXT_VIOTA_M(viota_m_b, uint8_t, H1, clearb)
-GEN_VEXT_VIOTA_M(viota_m_h, uint16_t, H2, clearh)
-GEN_VEXT_VIOTA_M(viota_m_w, uint32_t, H4, clearl)
-GEN_VEXT_VIOTA_M(viota_m_d, uint64_t, H8, clearq)
+GEN_VEXT_VIOTA_M(viota_m_b, uint8_t, H1)
+GEN_VEXT_VIOTA_M(viota_m_h, uint16_t, H2)
+GEN_VEXT_VIOTA_M(viota_m_w, uint32_t, H4)
+GEN_VEXT_VIOTA_M(viota_m_d, uint64_t, H8)
/* Vector Element Index Instruction */
-#define GEN_VEXT_VID_V(NAME, ETYPE, H, CLEAR_FN) \
+#define GEN_VEXT_VID_V(NAME, ETYPE, H) \
void HELPER(NAME)(void *vd, void *v0, CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
int i; \
@@ -4642,24 +4505,22 @@ void HELPER(NAME)(void *vd, void *v0, CPURISCVState *env, uint32_t desc) \
} \
*((ETYPE *)vd + H(i)) = i; \
} \
- CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
}
-GEN_VEXT_VID_V(vid_v_b, uint8_t, H1, clearb)
-GEN_VEXT_VID_V(vid_v_h, uint16_t, H2, clearh)
-GEN_VEXT_VID_V(vid_v_w, uint32_t, H4, clearl)
-GEN_VEXT_VID_V(vid_v_d, uint64_t, H8, clearq)
+GEN_VEXT_VID_V(vid_v_b, uint8_t, H1)
+GEN_VEXT_VID_V(vid_v_h, uint16_t, H2)
+GEN_VEXT_VID_V(vid_v_w, uint32_t, H4)
+GEN_VEXT_VID_V(vid_v_d, uint64_t, H8)
/*
*** Vector Permutation Instructions
*/
/* Vector Slide Instructions */
-#define GEN_VEXT_VSLIDEUP_VX(NAME, ETYPE, H, CLEAR_FN) \
+#define GEN_VEXT_VSLIDEUP_VX(NAME, ETYPE, H) \
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
target_ulong offset = s1, i; \
@@ -4670,16 +4531,15 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
} \
*((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - offset)); \
} \
- CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
}
/* vslideup.vx vd, vs2, rs1, vm # vd[i+rs1] = vs2[i] */
-GEN_VEXT_VSLIDEUP_VX(vslideup_vx_b, uint8_t, H1, clearb)
-GEN_VEXT_VSLIDEUP_VX(vslideup_vx_h, uint16_t, H2, clearh)
-GEN_VEXT_VSLIDEUP_VX(vslideup_vx_w, uint32_t, H4, clearl)
-GEN_VEXT_VSLIDEUP_VX(vslideup_vx_d, uint64_t, H8, clearq)
+GEN_VEXT_VSLIDEUP_VX(vslideup_vx_b, uint8_t, H1)
+GEN_VEXT_VSLIDEUP_VX(vslideup_vx_h, uint16_t, H2)
+GEN_VEXT_VSLIDEUP_VX(vslideup_vx_w, uint32_t, H4)
+GEN_VEXT_VSLIDEUP_VX(vslideup_vx_d, uint64_t, H8)
-#define GEN_VEXT_VSLIDEDOWN_VX(NAME, ETYPE, H, CLEAR_FN) \
+#define GEN_VEXT_VSLIDEDOWN_VX(NAME, ETYPE, H) \
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
@@ -4695,20 +4555,18 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
} \
*((ETYPE *)vd + H(i)) = j >= vlmax ? 0 : *((ETYPE *)vs2 + H(j)); \
} \
- CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
}
/* vslidedown.vx vd, vs2, rs1, vm # vd[i] = vs2[i+rs1] */
-GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_b, uint8_t, H1, clearb)
-GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_h, uint16_t, H2, clearh)
-GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_w, uint32_t, H4, clearl)
-GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_d, uint64_t, H8, clearq)
+GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_b, uint8_t, H1)
+GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_h, uint16_t, H2)
+GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_w, uint32_t, H4)
+GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_d, uint64_t, H8)
-#define GEN_VEXT_VSLIDE1UP_VX(NAME, ETYPE, H, CLEAR_FN) \
+#define GEN_VEXT_VSLIDE1UP_VX(NAME, ETYPE, H) \
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
@@ -4723,20 +4581,18 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
*((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - 1)); \
} \
} \
- CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
}
/* vslide1up.vx vd, vs2, rs1, vm # vd[0]=x[rs1], vd[i+1] = vs2[i] */
-GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_b, uint8_t, H1, clearb)
-GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_h, uint16_t, H2, clearh)
-GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_w, uint32_t, H4, clearl)
-GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, uint64_t, H8, clearq)
+GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_b, uint8_t, H1)
+GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_h, uint16_t, H2)
+GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_w, uint32_t, H4)
+GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, uint64_t, H8)
-#define GEN_VEXT_VSLIDE1DOWN_VX(NAME, ETYPE, H, CLEAR_FN) \
+#define GEN_VEXT_VSLIDE1DOWN_VX(NAME, ETYPE, H) \
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t i; \
@@ -4751,17 +4607,16 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
*((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i + 1)); \
} \
} \
- CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
}
/* vslide1down.vx vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=x[rs1] */
-GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_b, uint8_t, H1, clearb)
-GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_h, uint16_t, H2, clearh)
-GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_w, uint32_t, H4, clearl)
-GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, uint64_t, H8, clearq)
+GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_b, uint8_t, H1)
+GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_h, uint16_t, H2)
+GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_w, uint32_t, H4)
+GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, uint64_t, H8)
/* Vector Register Gather Instruction */
-#define GEN_VEXT_VRGATHER_VV(NAME, ETYPE, H, CLEAR_FN) \
+#define GEN_VEXT_VRGATHER_VV(NAME, ETYPE, H) \
void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
@@ -4781,16 +4636,15 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
*((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(index)); \
} \
} \
- CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
}
/* vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]]; */
-GEN_VEXT_VRGATHER_VV(vrgather_vv_b, uint8_t, H1, clearb)
-GEN_VEXT_VRGATHER_VV(vrgather_vv_h, uint16_t, H2, clearh)
-GEN_VEXT_VRGATHER_VV(vrgather_vv_w, uint32_t, H4, clearl)
-GEN_VEXT_VRGATHER_VV(vrgather_vv_d, uint64_t, H8, clearq)
+GEN_VEXT_VRGATHER_VV(vrgather_vv_b, uint8_t, H1)
+GEN_VEXT_VRGATHER_VV(vrgather_vv_h, uint16_t, H2)
+GEN_VEXT_VRGATHER_VV(vrgather_vv_w, uint32_t, H4)
+GEN_VEXT_VRGATHER_VV(vrgather_vv_d, uint64_t, H8)
-#define GEN_VEXT_VRGATHER_VX(NAME, ETYPE, H, CLEAR_FN) \
+#define GEN_VEXT_VRGATHER_VX(NAME, ETYPE, H) \
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
@@ -4809,21 +4663,19 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
*((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(index)); \
} \
} \
- CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
}
/* vd[i] = (x[rs1] >= VLMAX) ? 0 : vs2[rs1] */
-GEN_VEXT_VRGATHER_VX(vrgather_vx_b, uint8_t, H1, clearb)
-GEN_VEXT_VRGATHER_VX(vrgather_vx_h, uint16_t, H2, clearh)
-GEN_VEXT_VRGATHER_VX(vrgather_vx_w, uint32_t, H4, clearl)
-GEN_VEXT_VRGATHER_VX(vrgather_vx_d, uint64_t, H8, clearq)
+GEN_VEXT_VRGATHER_VX(vrgather_vx_b, uint8_t, H1)
+GEN_VEXT_VRGATHER_VX(vrgather_vx_h, uint16_t, H2)
+GEN_VEXT_VRGATHER_VX(vrgather_vx_w, uint32_t, H4)
+GEN_VEXT_VRGATHER_VX(vrgather_vx_d, uint64_t, H8)
/* Vector Compress Instruction */
-#define GEN_VEXT_VCOMPRESS_VM(NAME, ETYPE, H, CLEAR_FN) \
+#define GEN_VEXT_VCOMPRESS_VM(NAME, ETYPE, H) \
void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vl = env->vl; \
uint32_t num = 0, i; \
\
@@ -4834,11 +4686,10 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
*((ETYPE *)vd + H(num)) = *((ETYPE *)vs2 + H(i)); \
num++; \
} \
- CLEAR_FN(vd, num, num * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
}
/* Compress into vd elements of vs2 where vs1 is enabled */
-GEN_VEXT_VCOMPRESS_VM(vcompress_vm_b, uint8_t, H1, clearb)
-GEN_VEXT_VCOMPRESS_VM(vcompress_vm_h, uint16_t, H2, clearh)
-GEN_VEXT_VCOMPRESS_VM(vcompress_vm_w, uint32_t, H4, clearl)
-GEN_VEXT_VCOMPRESS_VM(vcompress_vm_d, uint64_t, H8, clearq)
+GEN_VEXT_VCOMPRESS_VM(vcompress_vm_b, uint8_t, H1)
+GEN_VEXT_VCOMPRESS_VM(vcompress_vm_h, uint16_t, H2)
+GEN_VEXT_VCOMPRESS_VM(vcompress_vm_w, uint32_t, H4)
+GEN_VEXT_VCOMPRESS_VM(vcompress_vm_d, uint64_t, H8)
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 14/75] target/riscv: rvv-1.0: update check functions
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (12 preceding siblings ...)
2021-02-26 3:17 ` [PATCH v7 13/75] target/riscv: rvv-1.0: add VMA and VTA frank.chang
@ 2021-02-26 3:17 ` frank.chang
2021-02-26 3:17 ` [PATCH v7 15/75] target/riscv: introduce more imm value modes in translator functions frank.chang
` (60 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:17 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Update check functions with RVV 1.0 rules.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 732 ++++++++++++++++--------
1 file changed, 499 insertions(+), 233 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 46e18a62b59..5967ba42b6d 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -19,11 +19,124 @@
#include "tcg/tcg-gvec-desc.h"
#include "internals.h"
+static inline bool is_overlapped(const int8_t astart, int8_t asize,
+ const int8_t bstart, int8_t bsize)
+{
+ const int8_t aend = astart + asize;
+ const int8_t bend = bstart + bsize;
+
+ return MAX(aend, bend) - MIN(astart, bstart) < asize + bsize;
+}
+
+static bool require_rvv(DisasContext *s)
+{
+ return s->mstatus_vs != 0;
+}
+
+static bool require_rvf(DisasContext *s)
+{
+ if (s->mstatus_fs == 0) {
+ return false;
+ }
+
+ switch (s->sew) {
+ case MO_16:
+ case MO_32:
+ return has_ext(s, RVF);
+ case MO_64:
+ return has_ext(s, RVD);
+ default:
+ return false;
+ }
+}
+
+static bool require_scale_rvf(DisasContext *s)
+{
+ if (s->mstatus_fs == 0) {
+ return false;
+ }
+
+ switch (s->sew) {
+ case MO_8:
+ case MO_16:
+ return has_ext(s, RVF);
+ case MO_32:
+ return has_ext(s, RVD);
+ default:
+ return false;
+ }
+}
+
+/* Destination vector register group cannot overlap source mask register. */
+static bool require_vm(int vm, int vd)
+{
+ return (vm != 0 || vd != 0);
+}
+
+static bool require_nf(int vd, int nf, int lmul)
+{
+ int size = nf << MAX(lmul, 0);
+ return size <= 8 && vd + size <= 32;
+}
+
+/*
+ * Vector register should aligned with the passed-in LMUL (EMUL).
+ * If LMUL < 0, i.e. fractional LMUL, any vector register is allowed.
+ */
+static bool require_align(const int8_t val, const int8_t lmul)
+{
+ return lmul <= 0 || extract32(val, 0, lmul) == 0;
+}
+
+/*
+ * A destination vector register group can overlap a source vector
+ * register group only if one of the following holds:
+ * 1. The destination EEW equals the source EEW.
+ * 2. The destination EEW is smaller than the source EEW and the overlap
+ * is in the lowest-numbered part of the source register group.
+ * 3. The destination EEW is greater than the source EEW, the source EMUL
+ * is at least 1, and the overlap is in the highest-numbered part of
+ * the destination register group.
+ * (Section 5.2)
+ *
+ * This function returns true if one of the following holds:
+ * * Destination vector register group does not overlap a source vector
+ * register group.
+ * * Rule 3 met.
+ * For rule 1, overlap is allowed so this function doesn't need to be called.
+ * For rule 2, (vd == vs). Caller has to check whether: (vd != vs) before
+ * calling this function.
+ */
+static bool require_noover(const int8_t dst, const int8_t dst_lmul,
+ const int8_t src, const int8_t src_lmul)
+{
+ int8_t dst_size = dst_lmul <= 0 ? 1 : 1 << dst_lmul;
+ int8_t src_size = src_lmul <= 0 ? 1 : 1 << src_lmul;
+
+ /* Destination EEW is greater than the source EEW, check rule 3. */
+ if (dst_size > src_size) {
+ if (dst < src &&
+ src_lmul >= 0 &&
+ is_overlapped(dst, dst_size, src, src_size) &&
+ !is_overlapped(dst, dst_size, src + src_size, src_size)) {
+ return true;
+ }
+ }
+
+ return !is_overlapped(dst, dst_size, src, src_size);
+}
+
+static bool require_noover_seg(const int8_t dst, const int8_t nf,
+ const int8_t src)
+{
+ return !is_overlapped(dst, nf, src, 1);
+}
+
static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
{
TCGv s1, s2, dst;
- if (!has_ext(ctx, RVV)) {
+ if (!require_rvv(ctx) || !has_ext(ctx, RVV)) {
return false;
}
@@ -56,7 +169,7 @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
{
TCGv s1, s2, dst;
- if (!has_ext(ctx, RVV)) {
+ if (!require_rvv(ctx) || !has_ext(ctx, RVV)) {
return false;
}
@@ -100,54 +213,246 @@ static bool vext_check_isa_ill(DisasContext *s)
return !s->vill;
}
+static bool vext_check_ss(DisasContext *s, int vd, int vs, int vm)
+{
+ return require_vm(vm, vd) &&
+ require_align(vd, s->lmul) &&
+ require_align(vs, s->lmul);
+}
+
/*
- * There are two rules check here.
+ * Check function for vector instruction with format:
+ * single-width result and single-width sources (SEW = SEW op SEW)
*
- * 1. Vector register numbers are multiples of LMUL. (Section 3.2)
+ * Rules to be checked here:
+ * 1. Destination vector register group for a masked vector
+ * instruction cannot overlap the source mask register (v0).
+ * (Section 5.3)
+ * 2. Destination vector register number is multiples of LMUL.
+ * (Section 3.3.2)
+ * 3. Source (vs2, vs1) vector register number are multiples of LMUL.
+ * (Section 3.3.2)
+ */
+static bool vext_check_sss(DisasContext *s, int vd, int vs1, int vs2, int vm)
+{
+ return vext_check_ss(s, vd, vs2, vm) &&
+ require_align(vs1, s->lmul);
+}
+
+static bool vext_check_ms(DisasContext *s, int vd, int vs)
+{
+ bool ret = require_align(vs, s->lmul);
+ if (vd != vs) {
+ ret &= require_noover(vd, 0, vs, s->lmul);
+ }
+ return ret;
+}
+
+/*
+ * Check function for maskable vector instruction with format:
+ * single-width result and single-width sources (SEW = SEW op SEW)
*
- * 2. For all widening instructions, the destination LMUL value must also be
- * a supported LMUL value. (Section 11.2)
+ * Rules to be checked here:
+ * 1. Source (vs2, vs1) vector register number are multiples of LMUL.
+ * (Section 3.3.2)
+ * 2. Destination vector register cannot overlap a source vector
+ * register (vs2, vs1) group.
+ * (Section 5.2)
+ * 3. The destination vector register group for a masked vector
+ * instruction cannot overlap the source mask register (v0),
+ * unless the destination vector register is being written
+ * with a mask value (e.g., comparisons) or the scalar result
+ * of a reduction. (Section 5.3)
*/
-static bool vext_check_reg(DisasContext *s, uint32_t reg, bool widen)
+static bool vext_check_mss(DisasContext *s, int vd, int vs1, int vs2)
{
- /*
- * The destination vector register group results are arranged as if both
- * SEW and LMUL were at twice their current settings. (Section 11.2).
- */
- int legal = widen ? 2 << s->lmul : 1 << s->lmul;
+ bool ret = vext_check_ms(s, vd, vs2) &&
+ require_align(vs1, s->lmul);
+ if (vd != vs1) {
+ ret &= require_noover(vd, 0, vs1, s->lmul);
+ }
+ return ret;
+}
- return !((s->lmul == 0x3 && widen) || (reg % legal));
+/*
+ * Common check function for vector widening instructions
+ * of double-width result (2*SEW).
+ *
+ * Rules to be checked here:
+ * 1. The largest vector register group used by an instruction
+ * can not be greater than 8 vector registers (Section 5.2):
+ * => LMUL < 8.
+ * => SEW < 64.
+ * 2. Destination vector register number is multiples of 2 * LMUL.
+ * (Section 3.3.2, 11.2)
+ * 3. Destination vector register group for a masked vector
+ * instruction cannot overlap the source mask register (v0).
+ * (Section 5.3)
+ */
+static bool vext_wide_check_common(DisasContext *s, int vd, int vm)
+{
+ return (s->lmul <= 2) &&
+ (s->sew < MO_64) &&
+ require_align(vd, s->lmul + 1) &&
+ require_vm(vm, vd);
}
/*
- * There are two rules check here.
+ * Common check function for vector narrowing instructions
+ * of single-width result (SEW) and double-width source (2*SEW).
*
- * 1. The destination vector register group for a masked vector instruction can
- * only overlap the source mask register (v0) when LMUL=1. (Section 5.3)
+ * Rules to be checked here:
+ * 1. The largest vector register group used by an instruction
+ * can not be greater than 8 vector registers (Section 5.2):
+ * => LMUL < 8.
+ * => SEW < 64.
+ * 2. Source vector register number is multiples of 2 * LMUL.
+ * (Section 3.3.2, 11.3)
+ * 3. Destination vector register number is multiples of LMUL.
+ * (Section 3.3.2, 11.3)
+ * 4. Destination vector register group for a masked vector
+ * instruction cannot overlap the source mask register (v0).
+ * (Section 5.3)
+ */
+static bool vext_narrow_check_common(DisasContext *s, int vd, int vs2,
+ int vm)
+{
+ return (s->lmul <= 2) &&
+ (s->sew < MO_64) &&
+ require_align(vs2, s->lmul + 1) &&
+ require_align(vd, s->lmul) &&
+ require_vm(vm, vd);
+}
+
+static bool vext_check_ds(DisasContext *s, int vd, int vs, int vm)
+{
+ return vext_wide_check_common(s, vd, vm) &&
+ require_align(vs, s->lmul) &&
+ require_noover(vd, s->lmul + 1, vs, s->lmul);
+}
+
+static bool vext_check_dd(DisasContext *s, int vd, int vs, int vm)
+{
+ return vext_wide_check_common(s, vd, vm) &&
+ require_align(vs, s->lmul + 1);
+}
+
+/*
+ * Check function for vector instruction with format:
+ * double-width result and single-width sources (2*SEW = SEW op SEW)
+ *
+ * Rules to be checked here:
+ * 1. All rules in defined in widen common rules are applied.
+ * 2. Source (vs2, vs1) vector register number are multiples of LMUL.
+ * (Section 3.3.2)
+ * 3. Destination vector register cannot overlap a source vector
+ * register (vs2, vs1) group.
+ * (Section 5.2)
+ */
+static bool vext_check_dss(DisasContext *s, int vd, int vs1, int vs2, int vm)
+{
+ return vext_check_ds(s, vd, vs2, vm) &&
+ require_align(vs1, s->lmul) &&
+ require_noover(vd, s->lmul + 1, vs1, s->lmul);
+}
+
+/*
+ * Check function for vector instruction with format:
+ * double-width result and double-width source1 and single-width
+ * source2 (2*SEW = 2*SEW op SEW)
+ *
+ * Rules to be checked here:
+ * 1. All rules in defined in widen common rules are applied.
+ * 2. Source 1 (vs2) vector register number is multiples of 2 * LMUL.
+ * (Section 3.3.2)
+ * 3. Source 2 (vs1) vector register number is multiples of LMUL.
+ * (Section 3.3.2)
+ * 4. Destination vector register cannot overlap a source vector
+ * register (vs1) group.
+ * (Section 5.2)
+ */
+static bool vext_check_dds(DisasContext *s, int vd, int vs1, int vs2, int vm)
+{
+ return vext_check_ds(s, vd, vs1, vm) &&
+ require_align(vs2, s->lmul + 1);
+}
+
+static bool vext_check_sd(DisasContext *s, int vd, int vs, int vm)
+{
+ bool ret = vext_narrow_check_common(s, vd, vs, vm);
+ if (vd != vs) {
+ ret &= require_noover(vd, s->lmul, vs, s->lmul + 1);
+ }
+ return ret;
+}
+
+/*
+ * Check function for vector instruction with format:
+ * single-width result and double-width source 1 and single-width
+ * source 2 (SEW = 2*SEW op SEW)
*
- * 2. In widen instructions and some other insturctions, like vslideup.vx,
- * there is no need to check whether LMUL=1.
+ * Rules to be checked here:
+ * 1. All rules in defined in narrow common rules are applied.
+ * 2. Destination vector register cannot overlap a source vector
+ * register (vs2) group.
+ * (Section 5.2)
+ * 3. Source 2 (vs1) vector register number is multiples of LMUL.
+ * (Section 3.3.2)
*/
-static bool vext_check_overlap_mask(DisasContext *s, uint32_t vd, bool vm,
- bool force)
+static bool vext_check_sds(DisasContext *s, int vd, int vs1, int vs2, int vm)
{
- return (vm != 0 || vd != 0) || (!force && (s->lmul == 0));
+ return vext_check_sd(s, vd, vs2, vm) &&
+ require_align(vs1, s->lmul);
}
-/* The LMUL setting must be such that LMUL * NFIELDS <= 8. (Section 7.8) */
-static bool vext_check_nf(DisasContext *s, uint32_t nf)
+/*
+ * Check function for vector reduction instructions.
+ *
+ * Rules to be checked here:
+ * 1. Source 1 (vs2) vector register number is multiples of LMUL.
+ * (Section 3.3.2)
+ */
+static bool vext_check_reduction(DisasContext *s, int vs2)
{
- return (1 << s->lmul) * nf <= 8;
+ return require_align(vs2, s->lmul) && (s->vstart == 0);
}
/*
- * The destination vector register group cannot overlap a source vector register
- * group of a different element width. (Section 11.2)
+ * Check function for vector slide instructions.
+ *
+ * Rules to be checked here:
+ * 1. Source 1 (vs2) vector register number is multiples of LMUL.
+ * (Section 3.3.2)
+ * 2. Destination vector register number is multiples of LMUL.
+ * (Section 3.3.2)
+ * 3. Destination vector register group for a masked vector
+ * instruction cannot overlap the source mask register (v0).
+ * (Section 5.3)
+ * 4. The destination vector register group for vslideup, vslide1up,
+ * vfslide1up, cannot overlap the source vector register (vs2) group.
+ * (Section 5.2, 17.3.1, 17.3.3)
*/
-static inline bool vext_check_overlap_group(int rd, int dlen, int rs, int slen)
+static bool vext_check_slide(DisasContext *s, int vd, int vs2,
+ int vm, bool is_over)
+{
+ bool ret = require_align(vs2, s->lmul) &&
+ require_align(vd, s->lmul) &&
+ require_vm(vm, vd);
+ if (is_over) {
+ ret &= (vd != vs2);
+ }
+ return ret;
+}
+
+/*
+ * In cpu_get_tb_cpu_state(), set VILL if RVV was not present.
+ * So RVV is also be checked in this function.
+ */
+static bool vext_check_isa_ill(DisasContext *s)
{
- return ((rd >= rs + slen) || (rs >= rd + dlen));
+ return !s->vill;
}
+
/* common translation macro */
#define GEN_VEXT_TRANS(NAME, SEQ, ARGTYPE, OP, CHECK) \
static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE *a)\
@@ -803,11 +1108,9 @@ GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check)
static bool opivv_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_reg(s, a->rs1, false));
+ return require_rvv(s) &&
+ vext_check_isa_ill(s) &&
+ vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm);
}
typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
@@ -898,10 +1201,9 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
static bool opivx_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false));
+ return require_rvv(s) &&
+ vext_check_isa_ill(s) &&
+ vext_check_ss(s, a->rd, a->rs2, a->vm);
}
typedef void GVecGen2sFn(unsigned, uint32_t, uint32_t, TCGv_i64,
@@ -1098,16 +1400,9 @@ GEN_OPIVI_GVEC_TRANS(vrsub_vi, 0, vrsub_vx, rsubi)
/* OPIVV with WIDEN */
static bool opivv_widen_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, true) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_reg(s, a->rs1, false) &&
- vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2,
- 1 << s->lmul) &&
- vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1,
- 1 << s->lmul) &&
- (s->lmul < 0x3) && (s->sew < 0x3));
+ return require_rvv(s) &&
+ vext_check_isa_ill(s) &&
+ vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
}
static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
@@ -1152,13 +1447,9 @@ GEN_OPIVV_WIDEN_TRANS(vwsub_vv, opivv_widen_check)
/* OPIVX with WIDEN */
static bool opivx_widen_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, true) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2,
- 1 << s->lmul) &&
- (s->lmul < 0x3) && (s->sew < 0x3));
+ return require_rvv(s) &&
+ vext_check_isa_ill(s) &&
+ vext_check_ds(s, a->rd, a->rs2, a->vm);
}
static bool do_opivx_widen(DisasContext *s, arg_rmrr *a,
@@ -1189,14 +1480,9 @@ GEN_OPIVX_WIDEN_TRANS(vwsub_vx)
/* WIDEN OPIVV with WIDEN */
static bool opiwv_widen_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, true) &&
- vext_check_reg(s, a->rs2, true) &&
- vext_check_reg(s, a->rs1, false) &&
- vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1,
- 1 << s->lmul) &&
- (s->lmul < 0x3) && (s->sew < 0x3));
+ return require_rvv(s) &&
+ vext_check_isa_ill(s) &&
+ vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
}
static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
@@ -1239,11 +1525,9 @@ GEN_OPIWV_WIDEN_TRANS(vwsub_wv)
/* WIDEN OPIVX with WIDEN */
static bool opiwx_widen_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, true) &&
- vext_check_reg(s, a->rs2, true) &&
- (s->lmul < 0x3) && (s->sew < 0x3));
+ return require_rvv(s) &&
+ vext_check_isa_ill(s) &&
+ vext_check_dd(s, a->rd, a->rs2, a->vm);
}
static bool do_opiwx_widen(DisasContext *s, arg_rmrr *a,
@@ -1304,11 +1588,10 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
*/
static bool opivv_vadc_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_reg(s, a->rs1, false) &&
- ((a->rd != 0) || (s->lmul == 0)));
+ return require_rvv(s) &&
+ vext_check_isa_ill(s) &&
+ (a->rd != 0) &&
+ vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm);
}
GEN_OPIVV_TRANS(vadc_vvm, opivv_vadc_check)
@@ -1320,11 +1603,9 @@ GEN_OPIVV_TRANS(vsbc_vvm, opivv_vadc_check)
*/
static bool opivv_vmadc_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_reg(s, a->rs1, false) &&
- vext_check_overlap_group(a->rd, 1, a->rs1, 1 << s->lmul) &&
- vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul));
+ return require_rvv(s) &&
+ vext_check_isa_ill(s) &&
+ vext_check_mss(s, a->rd, a->rs1, a->rs2);
}
GEN_OPIVV_TRANS(vmadc_vvm, opivv_vmadc_check)
@@ -1332,10 +1613,10 @@ GEN_OPIVV_TRANS(vmsbc_vvm, opivv_vmadc_check)
static bool opivx_vadc_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- ((a->rd != 0) || (s->lmul == 0)));
+ return require_rvv(s) &&
+ vext_check_isa_ill(s) &&
+ (a->rd != 0) &&
+ vext_check_ss(s, a->rd, a->rs2, a->vm);
}
/* OPIVX without GVEC IR */
@@ -1358,9 +1639,9 @@ GEN_OPIVX_TRANS(vsbc_vxm, opivx_vadc_check)
static bool opivx_vmadc_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul));
+ return require_rvv(s) &&
+ vext_check_isa_ill(s) &&
+ vext_check_ms(s, a->rd, a->rs2);
}
GEN_OPIVX_TRANS(vmadc_vxm, opivx_vmadc_check)
@@ -1451,14 +1732,9 @@ GEN_OPIVI_GVEC_TRANS(vsra_vi, 1, vsra_vx, sari)
/* Vector Narrowing Integer Right Shift Instructions */
static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, true) &&
- vext_check_reg(s, a->rs1, false) &&
- vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2,
- 2 << s->lmul) &&
- (s->lmul < 0x3) && (s->sew < 0x3));
+ return require_rvv(s) &&
+ vext_check_isa_ill(s) &&
+ vext_check_sds(s, a->rd, a->rs1, a->rs2, a->vm);
}
/* OPIVV with NARROW */
@@ -1492,13 +1768,9 @@ GEN_OPIVV_NARROW_TRANS(vnsrl_vv)
static bool opivx_narrow_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, true) &&
- vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2,
- 2 << s->lmul) &&
- (s->lmul < 0x3) && (s->sew < 0x3));
+ return require_rvv(s) &&
+ vext_check_isa_ill(s) &&
+ vext_check_sd(s, a->rd, a->rs2, a->vm);
}
/* OPIVX with NARROW */
@@ -1546,13 +1818,11 @@ GEN_OPIVI_NARROW_TRANS(vnsrl_vi, 1, vnsrl_vx)
*/
static bool opivv_cmp_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_reg(s, a->rs1, false) &&
- ((vext_check_overlap_group(a->rd, 1, a->rs1, 1 << s->lmul) &&
- vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul)) ||
- (s->lmul == 0)));
+ return require_rvv(s) &&
+ vext_check_isa_ill(s) &&
+ vext_check_mss(s, a->rd, a->rs1, a->rs2);
}
+
GEN_OPIVV_TRANS(vmseq_vv, opivv_cmp_check)
GEN_OPIVV_TRANS(vmsne_vv, opivv_cmp_check)
GEN_OPIVV_TRANS(vmsltu_vv, opivv_cmp_check)
@@ -1562,10 +1832,9 @@ GEN_OPIVV_TRANS(vmsle_vv, opivv_cmp_check)
static bool opivx_cmp_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rs2, false) &&
- (vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul) ||
- (s->lmul == 0)));
+ return require_rvv(s) &&
+ vext_check_isa_ill(s) &&
+ vext_check_ms(s, a->rd, a->rs2);
}
GEN_OPIVX_TRANS(vmseq_vx, opivx_cmp_check)
@@ -1644,10 +1913,10 @@ GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx)
/* Vector Integer Merge and Move Instructions */
static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
{
- if (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs1, false)) {
-
+ if (require_rvv(s) &&
+ vext_check_isa_ill(s) &&
+ /* vmv.v.v has rs2 = 0 and vm = 1 */
+ vext_check_sss(s, a->rd, a->rs1, 0, 1)) {
if (s->vl_eq_vlmax) {
tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd),
vreg_ofs(s, a->rs1),
@@ -1674,9 +1943,10 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
typedef void gen_helper_vmv_vx(TCGv_ptr, TCGv_i64, TCGv_env, TCGv_i32);
static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
{
- if (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false)) {
-
+ if (require_rvv(s) &&
+ vext_check_isa_ill(s) &&
+ /* vmv.v.x has rs2 = 0 and vm = 1 */
+ vext_check_ss(s, a->rd, 0, 1)) {
TCGv s1;
TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
@@ -1717,9 +1987,10 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
{
- if (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false)) {
-
+ if (require_rvv(s) &&
+ vext_check_isa_ill(s) &&
+ /* vmv.v.i has rs2 = 0 and vm = 1 */
+ vext_check_ss(s, a->rd, 0, 1)) {
int64_t simm = sextract64(a->rs1, 0, 5);
if (s->vl_eq_vlmax) {
tcg_gen_gvec_dup_imm(s->sew, vreg_ofs(s, a->rd),
@@ -1821,12 +2092,10 @@ GEN_OPIVI_NARROW_TRANS(vnclip_vi, 1, vnclip_vx)
*/
static bool opfvv_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_reg(s, a->rs1, false) &&
- (s->sew != 0));
+ return require_rvv(s) &&
+ require_rvf(s) &&
+ vext_check_isa_ill(s) &&
+ vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm);
}
/* OPFVV without GVEC IR */
@@ -1891,17 +2160,16 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
return true;
}
-static bool opfvf_check(DisasContext *s, arg_rmrr *a)
-{
/*
* If the current SEW does not correspond to a supported IEEE floating-point
* type, an illegal instruction exception is raised
*/
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- (s->sew != 0));
+static bool opfvf_check(DisasContext *s, arg_rmrr *a)
+{
+ return require_rvv(s) &&
+ require_rvf(s) &&
+ vext_check_isa_ill(s) &&
+ vext_check_ss(s, a->rd, a->rs2, a->vm);
}
/* OPFVF without GVEC IR */
@@ -1931,16 +2199,10 @@ GEN_OPFVF_TRANS(vfrsub_vf, opfvf_check)
/* Vector Widening Floating-Point Add/Subtract Instructions */
static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, true) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_reg(s, a->rs1, false) &&
- vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2,
- 1 << s->lmul) &&
- vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1,
- 1 << s->lmul) &&
- (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
+ return require_rvv(s) &&
+ require_rvf(s) &&
+ vext_check_isa_ill(s) &&
+ vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
}
/* OPFVV with WIDEN */
@@ -1974,13 +2236,10 @@ GEN_OPFVV_WIDEN_TRANS(vfwsub_vv, opfvv_widen_check)
static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, true) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2,
- 1 << s->lmul) &&
- (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
+ return require_rvv(s) &&
+ require_rvf(s) &&
+ vext_check_isa_ill(s) &&
+ vext_check_ds(s, a->rd, a->rs2, a->vm);
}
/* OPFVF with WIDEN */
@@ -2006,14 +2265,10 @@ GEN_OPFVF_WIDEN_TRANS(vfwsub_vf)
static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, true) &&
- vext_check_reg(s, a->rs2, true) &&
- vext_check_reg(s, a->rs1, false) &&
- vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs1,
- 1 << s->lmul) &&
- (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
+ return require_rvv(s) &&
+ require_rvf(s) &&
+ vext_check_isa_ill(s) &&
+ vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
}
/* WIDEN OPFVV with WIDEN */
@@ -2047,11 +2302,10 @@ GEN_OPFWV_WIDEN_TRANS(vfwsub_wv)
static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, true) &&
- vext_check_reg(s, a->rs2, true) &&
- (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
+ return require_rvv(s) &&
+ require_rvf(s) &&
+ vext_check_isa_ill(s) &&
+ vext_check_dd(s, a->rd, a->rs2, a->vm);
}
/* WIDEN OPFVF with WIDEN */
@@ -2122,11 +2376,11 @@ GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf)
*/
static bool opfv_check(DisasContext *s, arg_rmr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- (s->sew != 0));
+ return require_rvv(s) &&
+ require_rvf(s) &&
+ vext_check_isa_ill(s) &&
+ /* OPFV instructions ignore vs1 check */
+ vext_check_ss(s, a->rd, a->rs2, a->vm);
}
#define GEN_OPFV_TRANS(NAME, CHECK) \
@@ -2174,13 +2428,10 @@ GEN_OPFVF_TRANS(vfsgnjx_vf, opfvf_check)
/* Vector Floating-Point Compare Instructions */
static bool opfvv_cmp_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_reg(s, a->rs1, false) &&
- (s->sew != 0) &&
- ((vext_check_overlap_group(a->rd, 1, a->rs1, 1 << s->lmul) &&
- vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul)) ||
- (s->lmul == 0)));
+ return require_rvv(s) &&
+ require_rvf(s) &&
+ vext_check_isa_ill(s) &&
+ vext_check_mss(s, a->rd, a->rs1, a->rs2);
}
GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check)
@@ -2191,11 +2442,10 @@ GEN_OPFVV_TRANS(vmford_vv, opfvv_cmp_check)
static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rs2, false) &&
- (s->sew != 0) &&
- (vext_check_overlap_group(a->rd, 1, a->rs2, 1 << s->lmul) ||
- (s->lmul == 0)));
+ return require_rvv(s) &&
+ require_rvf(s) &&
+ vext_check_isa_ill(s) &&
+ vext_check_ms(s, a->rd, a->rs2);
}
GEN_OPFVF_TRANS(vmfeq_vf, opfvf_cmp_check)
@@ -2214,10 +2464,10 @@ GEN_OPFVF_TRANS(vfmerge_vfm, opfvf_check)
static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
{
- if (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false) &&
- (s->sew != 0)) {
-
+ if (require_rvv(s) &&
+ require_rvf(s) &&
+ vext_check_isa_ill(s) &&
+ require_align(a->rd, s->lmul)) {
if (s->vl_eq_vlmax) {
tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
MAXSZ(s), MAXSZ(s), cpu_fpr[a->rs1]);
@@ -2263,13 +2513,11 @@ GEN_OPFV_TRANS(vfcvt_f_x_v, opfv_check)
*/
static bool opfv_widen_check(DisasContext *s, arg_rmr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, true) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_overlap_group(a->rd, 2 << s->lmul, a->rs2,
- 1 << s->lmul) &&
- (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
+ return require_rvv(s) &&
+ require_scale_rvf(s) &&
+ (s->sew != MO_8) &&
+ vext_check_isa_ill(s) &&
+ vext_check_ds(s, a->rd, a->rs2, a->vm);
}
#define GEN_OPFV_WIDEN_TRANS(NAME) \
@@ -2311,13 +2559,12 @@ GEN_OPFV_WIDEN_TRANS(vfwcvt_f_f_v)
*/
static bool opfv_narrow_check(DisasContext *s, arg_rmr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, true) &&
- vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2,
- 2 << s->lmul) &&
- (s->lmul < 0x3) && (s->sew < 0x3) && (s->sew != 0));
+ return require_rvv(s) &&
+ require_rvf(s) &&
+ (s->sew != MO_64) &&
+ vext_check_isa_ill(s) &&
+ /* OPFV narrowing instructions ignore vs1 check */
+ vext_check_sd(s, a->rd, a->rs2, a->vm);
}
#define GEN_OPFV_NARROW_TRANS(NAME) \
@@ -2357,7 +2604,9 @@ GEN_OPFV_NARROW_TRANS(vfncvt_f_f_v)
/* Vector Single-Width Integer Reduction Instructions */
static bool reduction_check(DisasContext *s, arg_rmrr *a)
{
- return vext_check_isa_ill(s) && vext_check_reg(s, a->rs2, false);
+ return require_rvv(s) &&
+ vext_check_isa_ill(s) &&
+ vext_check_reduction(s, a->rs2);
}
GEN_OPIVV_TRANS(vredsum_vs, reduction_check)
@@ -2370,8 +2619,13 @@ GEN_OPIVV_TRANS(vredor_vs, reduction_check)
GEN_OPIVV_TRANS(vredxor_vs, reduction_check)
/* Vector Widening Integer Reduction Instructions */
-GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_check)
-GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_check)
+static bool reduction_widen_check(DisasContext *s, arg_rmrr *a)
+{
+ return reduction_check(s, a) && (s->sew < MO_64);
+}
+
+GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_widen_check)
+GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_widen_check)
/* Vector Single-Width Floating-Point Reduction Instructions */
GEN_OPFVV_TRANS(vfredsum_vs, reduction_check)
@@ -2419,7 +2673,8 @@ GEN_MM_TRANS(vmxnor_mm)
/* Vector mask population count vmpopc */
static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
{
- if (vext_check_isa_ill(s)) {
+ if (require_rvv(s) &&
+ vext_check_isa_ill(s)) {
TCGv_ptr src2, mask;
TCGv dst;
TCGv_i32 desc;
@@ -2450,7 +2705,8 @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
/* vmfirst find-first-set mask bit */
static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a)
{
- if (vext_check_isa_ill(s)) {
+ if (require_rvv(s) &&
+ vext_check_isa_ill(s)) {
TCGv_ptr src2, mask;
TCGv dst;
TCGv_i32 desc;
@@ -2509,10 +2765,11 @@ GEN_M_TRANS(vmsof_m)
/* Vector Iota Instruction */
static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
{
- if (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2, 1) &&
- (a->vm != 0 || a->rd != 0)) {
+ if (require_rvv(s) &&
+ vext_check_isa_ill(s) &&
+ require_noover(a->rd, s->lmul, a->rs2, 0) &&
+ require_vm(a->vm, a->rd) &&
+ require_align(a->rd, s->lmul)) {
uint32_t data = 0;
TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
@@ -2536,9 +2793,10 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
/* Vector Element Index Instruction */
static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
{
- if (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false)) {
+ if (require_rvv(s) &&
+ vext_check_isa_ill(s) &&
+ require_align(a->rd, s->lmul) &&
+ require_vm(a->vm, a->rd)) {
uint32_t data = 0;
TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
@@ -2788,41 +3046,48 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
/* Vector Slide Instructions */
static bool slideup_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- (a->rd != a->rs2));
+ return require_rvv(s) &&
+ vext_check_isa_ill(s) &&
+ vext_check_slide(s, a->rd, a->rs2, a->vm, true);
}
GEN_OPIVX_TRANS(vslideup_vx, slideup_check)
GEN_OPIVX_TRANS(vslide1up_vx, slideup_check)
GEN_OPIVI_TRANS(vslideup_vi, 1, vslideup_vx, slideup_check)
-GEN_OPIVX_TRANS(vslidedown_vx, opivx_check)
-GEN_OPIVX_TRANS(vslide1down_vx, opivx_check)
-GEN_OPIVI_TRANS(vslidedown_vi, 1, vslidedown_vx, opivx_check)
+static bool slidedown_check(DisasContext *s, arg_rmrr *a)
+{
+ return require_rvv(s) &&
+ vext_check_isa_ill(s) &&
+ vext_check_slide(s, a->rd, a->rs2, a->vm, false);
+}
+
+GEN_OPIVX_TRANS(vslidedown_vx, slidedown_check)
+GEN_OPIVX_TRANS(vslide1down_vx, slidedown_check)
+GEN_OPIVI_TRANS(vslidedown_vi, 1, vslidedown_vx, slidedown_check)
/* Vector Register Gather Instruction */
static bool vrgather_vv_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs1, false) &&
- vext_check_reg(s, a->rs2, false) &&
- (a->rd != a->rs2) && (a->rd != a->rs1));
+ return require_rvv(s) &&
+ vext_check_isa_ill(s) &&
+ require_align(a->rd, s->lmul) &&
+ require_align(a->rs1, s->lmul) &&
+ require_align(a->rs2, s->lmul) &&
+ (a->rd != a->rs2 && a->rd != a->rs1) &&
+ require_vm(a->vm, a->rd);
}
GEN_OPIVV_TRANS(vrgather_vv, vrgather_vv_check)
static bool vrgather_vx_check(DisasContext *s, arg_rmrr *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, true) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- (a->rd != a->rs2));
+ return require_rvv(s) &&
+ vext_check_isa_ill(s) &&
+ require_align(a->rd, s->lmul) &&
+ require_align(a->rs2, s->lmul) &&
+ (a->rd != a->rs2) &&
+ require_vm(a->vm, a->rd);
}
/* vrgather.vx vd, vs2, rs1, vm # vd[i] = (x[rs1] >= VLMAX) ? 0 : vs2[rs1] */
@@ -2886,11 +3151,12 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a)
/* Vector Compress Instruction */
static bool vcompress_vm_check(DisasContext *s, arg_r *a)
{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs1, 1) &&
- (a->rd != a->rs2));
+ return require_rvv(s) &&
+ vext_check_isa_ill(s) &&
+ require_align(a->rd, s->lmul) &&
+ require_align(a->rs2, s->lmul) &&
+ (a->rd != a->rs2) &&
+ require_noover(a->rd, s->lmul, a->rs1, 0);
}
static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 15/75] target/riscv: introduce more imm value modes in translator functions
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (13 preceding siblings ...)
2021-02-26 3:17 ` [PATCH v7 14/75] target/riscv: rvv-1.0: update check functions frank.chang
@ 2021-02-26 3:17 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 16/75] target/riscv: rvv:1.0: add translation-time nan-box helper function frank.chang
` (59 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:17 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Immediate value in translator function is extended not only
zero-extended and sign-extended but with more modes to be applicable
with multiple formats of vector instructions.
* IMM_ZX: Zero-extended
* IMM_SX: Sign-extended
* IMM_TRUNC_SEW: Truncate to log(SEW) bit
* IMM_TRUNC_2SEW: Truncate to log(2*SEW) bit
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 115 ++++++++++++++----------
1 file changed, 66 insertions(+), 49 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 5967ba42b6d..18a1c409fcf 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1307,8 +1307,32 @@ static void tcg_gen_gvec_rsubs(unsigned vece, uint32_t dofs, uint32_t aofs,
GEN_OPIVX_GVEC_TRANS(vrsub_vx, rsubs)
+typedef enum {
+ IMM_ZX, /* Zero-extended */
+ IMM_SX, /* Sign-extended */
+ IMM_TRUNC_SEW, /* Truncate to log(SEW) bits */
+ IMM_TRUNC_2SEW, /* Truncate to log(2*SEW) bits */
+} imm_mode_t;
+
+static int64_t extract_imm(DisasContext *s, uint32_t imm, imm_mode_t imm_mode)
+{
+ switch (imm_mode) {
+ case IMM_ZX:
+ return extract64(imm, 0, 5);
+ case IMM_SX:
+ return sextract64(imm, 0, 5);
+ case IMM_TRUNC_SEW:
+ return extract64(imm, 0, s->sew + 3);
+ case IMM_TRUNC_2SEW:
+ return extract64(imm, 0, s->sew + 4);
+ default:
+ g_assert_not_reached();
+ }
+}
+
static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
- gen_helper_opivx *fn, DisasContext *s, int zx)
+ gen_helper_opivx *fn, DisasContext *s,
+ imm_mode_t imm_mode)
{
TCGv_ptr dest, src2, mask;
TCGv src1;
@@ -1321,11 +1345,8 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
dest = tcg_temp_new_ptr();
mask = tcg_temp_new_ptr();
src2 = tcg_temp_new_ptr();
- if (zx) {
- src1 = tcg_const_tl(imm);
- } else {
- src1 = tcg_const_tl(sextract64(imm, 0, 5));
- }
+ src1 = tcg_const_tl(extract_imm(s, imm, imm_mode));
+
data = FIELD_DP32(data, VDATA, VM, vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
@@ -1351,28 +1372,23 @@ typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t,
static inline bool
do_opivi_gvec(DisasContext *s, arg_rmrr *a, GVecGen2iFn *gvec_fn,
- gen_helper_opivx *fn, int zx)
+ gen_helper_opivx *fn, imm_mode_t imm_mode)
{
if (!opivx_check(s, a)) {
return false;
}
if (a->vm && s->vl_eq_vlmax) {
- if (zx) {
- gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
- extract64(a->rs1, 0, 5), MAXSZ(s), MAXSZ(s));
- } else {
- gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
- sextract64(a->rs1, 0, 5), MAXSZ(s), MAXSZ(s));
- }
+ gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
+ extract_imm(s, a->rs1, imm_mode), MAXSZ(s), MAXSZ(s));
mark_vs_dirty(s);
return true;
}
- return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, zx);
+ return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, imm_mode);
}
/* OPIVI with GVEC IR */
-#define GEN_OPIVI_GVEC_TRANS(NAME, ZX, OPIVX, SUF) \
+#define GEN_OPIVI_GVEC_TRANS(NAME, IMM_MODE, OPIVX, SUF) \
static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
{ \
static gen_helper_opivx * const fns[4] = { \
@@ -1380,10 +1396,10 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_helper_##OPIVX##_w, gen_helper_##OPIVX##_d, \
}; \
return do_opivi_gvec(s, a, tcg_gen_gvec_##SUF, \
- fns[s->sew], ZX); \
+ fns[s->sew], IMM_MODE); \
}
-GEN_OPIVI_GVEC_TRANS(vadd_vi, 0, vadd_vx, addi)
+GEN_OPIVI_GVEC_TRANS(vadd_vi, IMM_SX, vadd_vx, addi)
static void tcg_gen_gvec_rsubi(unsigned vece, uint32_t dofs, uint32_t aofs,
int64_t c, uint32_t oprsz, uint32_t maxsz)
@@ -1393,7 +1409,7 @@ static void tcg_gen_gvec_rsubi(unsigned vece, uint32_t dofs, uint32_t aofs,
tcg_temp_free_i64(tmp);
}
-GEN_OPIVI_GVEC_TRANS(vrsub_vi, 0, vrsub_vx, rsubi)
+GEN_OPIVI_GVEC_TRANS(vrsub_vi, IMM_SX, vrsub_vx, rsubi)
/* Vector Widening Integer Add/Subtract */
@@ -1648,7 +1664,7 @@ GEN_OPIVX_TRANS(vmadc_vxm, opivx_vmadc_check)
GEN_OPIVX_TRANS(vmsbc_vxm, opivx_vmadc_check)
/* OPIVI without GVEC IR */
-#define GEN_OPIVI_TRANS(NAME, ZX, OPIVX, CHECK) \
+#define GEN_OPIVI_TRANS(NAME, IMM_MODE, OPIVX, CHECK) \
static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
{ \
if (CHECK(s, a)) { \
@@ -1657,13 +1673,13 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_helper_##OPIVX##_w, gen_helper_##OPIVX##_d, \
}; \
return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, \
- fns[s->sew], s, ZX); \
+ fns[s->sew], s, IMM_MODE); \
} \
return false; \
}
-GEN_OPIVI_TRANS(vadc_vim, 0, vadc_vxm, opivx_vadc_check)
-GEN_OPIVI_TRANS(vmadc_vim, 0, vmadc_vxm, opivx_vmadc_check)
+GEN_OPIVI_TRANS(vadc_vim, IMM_SX, vadc_vxm, opivx_vadc_check)
+GEN_OPIVI_TRANS(vmadc_vim, IMM_SX, vmadc_vxm, opivx_vmadc_check)
/* Vector Bitwise Logical Instructions */
GEN_OPIVV_GVEC_TRANS(vand_vv, and)
@@ -1672,9 +1688,9 @@ GEN_OPIVV_GVEC_TRANS(vxor_vv, xor)
GEN_OPIVX_GVEC_TRANS(vand_vx, ands)
GEN_OPIVX_GVEC_TRANS(vor_vx, ors)
GEN_OPIVX_GVEC_TRANS(vxor_vx, xors)
-GEN_OPIVI_GVEC_TRANS(vand_vi, 0, vand_vx, andi)
-GEN_OPIVI_GVEC_TRANS(vor_vi, 0, vor_vx, ori)
-GEN_OPIVI_GVEC_TRANS(vxor_vi, 0, vxor_vx, xori)
+GEN_OPIVI_GVEC_TRANS(vand_vi, IMM_SX, vand_vx, andi)
+GEN_OPIVI_GVEC_TRANS(vor_vi, IMM_SX, vor_vx, ori)
+GEN_OPIVI_GVEC_TRANS(vxor_vi, IMM_SX, vxor_vx, xori)
/* Vector Single-Width Bit Shift Instructions */
GEN_OPIVV_GVEC_TRANS(vsll_vv, shlv)
@@ -1725,9 +1741,9 @@ GEN_OPIVX_GVEC_SHIFT_TRANS(vsll_vx, shls)
GEN_OPIVX_GVEC_SHIFT_TRANS(vsrl_vx, shrs)
GEN_OPIVX_GVEC_SHIFT_TRANS(vsra_vx, sars)
-GEN_OPIVI_GVEC_TRANS(vsll_vi, 1, vsll_vx, shli)
-GEN_OPIVI_GVEC_TRANS(vsrl_vi, 1, vsrl_vx, shri)
-GEN_OPIVI_GVEC_TRANS(vsra_vi, 1, vsra_vx, sari)
+GEN_OPIVI_GVEC_TRANS(vsll_vi, IMM_ZX, vsll_vx, shli)
+GEN_OPIVI_GVEC_TRANS(vsrl_vi, IMM_ZX, vsrl_vx, shri)
+GEN_OPIVI_GVEC_TRANS(vsra_vi, IMM_ZX, vsra_vx, sari)
/* Vector Narrowing Integer Right Shift Instructions */
static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a)
@@ -1792,7 +1808,7 @@ GEN_OPIVX_NARROW_TRANS(vnsra_vx)
GEN_OPIVX_NARROW_TRANS(vnsrl_vx)
/* OPIVI with NARROW */
-#define GEN_OPIVI_NARROW_TRANS(NAME, ZX, OPIVX) \
+#define GEN_OPIVI_NARROW_TRANS(NAME, IMM_MODE, OPIVX) \
static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
{ \
if (opivx_narrow_check(s, a)) { \
@@ -1802,13 +1818,13 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_helper_##OPIVX##_w, \
}; \
return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, \
- fns[s->sew], s, ZX); \
+ fns[s->sew], s, IMM_MODE); \
} \
return false; \
}
-GEN_OPIVI_NARROW_TRANS(vnsra_vi, 1, vnsra_vx)
-GEN_OPIVI_NARROW_TRANS(vnsrl_vi, 1, vnsrl_vx)
+GEN_OPIVI_NARROW_TRANS(vnsra_vi, IMM_ZX, vnsra_vx)
+GEN_OPIVI_NARROW_TRANS(vnsrl_vi, IMM_ZX, vnsrl_vx)
/* Vector Integer Comparison Instructions */
/*
@@ -1846,12 +1862,12 @@ GEN_OPIVX_TRANS(vmsle_vx, opivx_cmp_check)
GEN_OPIVX_TRANS(vmsgtu_vx, opivx_cmp_check)
GEN_OPIVX_TRANS(vmsgt_vx, opivx_cmp_check)
-GEN_OPIVI_TRANS(vmseq_vi, 0, vmseq_vx, opivx_cmp_check)
-GEN_OPIVI_TRANS(vmsne_vi, 0, vmsne_vx, opivx_cmp_check)
-GEN_OPIVI_TRANS(vmsleu_vi, 1, vmsleu_vx, opivx_cmp_check)
-GEN_OPIVI_TRANS(vmsle_vi, 0, vmsle_vx, opivx_cmp_check)
-GEN_OPIVI_TRANS(vmsgtu_vi, 1, vmsgtu_vx, opivx_cmp_check)
-GEN_OPIVI_TRANS(vmsgt_vi, 0, vmsgt_vx, opivx_cmp_check)
+GEN_OPIVI_TRANS(vmseq_vi, IMM_SX, vmseq_vx, opivx_cmp_check)
+GEN_OPIVI_TRANS(vmsne_vi, IMM_SX, vmsne_vx, opivx_cmp_check)
+GEN_OPIVI_TRANS(vmsleu_vi, IMM_ZX, vmsleu_vx, opivx_cmp_check)
+GEN_OPIVI_TRANS(vmsle_vi, IMM_SX, vmsle_vx, opivx_cmp_check)
+GEN_OPIVI_TRANS(vmsgtu_vi, IMM_ZX, vmsgtu_vx, opivx_cmp_check)
+GEN_OPIVI_TRANS(vmsgt_vi, IMM_SX, vmsgt_vx, opivx_cmp_check)
/* Vector Integer Min/Max Instructions */
GEN_OPIVV_GVEC_TRANS(vminu_vv, umin)
@@ -2027,7 +2043,7 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
GEN_OPIVV_TRANS(vmerge_vvm, opivv_vadc_check)
GEN_OPIVX_TRANS(vmerge_vxm, opivx_vadc_check)
-GEN_OPIVI_TRANS(vmerge_vim, 0, vmerge_vxm, opivx_vadc_check)
+GEN_OPIVI_TRANS(vmerge_vim, IMM_SX, vmerge_vxm, opivx_vadc_check)
/*
*** Vector Fixed-Point Arithmetic Instructions
@@ -2042,8 +2058,8 @@ GEN_OPIVX_TRANS(vsaddu_vx, opivx_check)
GEN_OPIVX_TRANS(vsadd_vx, opivx_check)
GEN_OPIVX_TRANS(vssubu_vx, opivx_check)
GEN_OPIVX_TRANS(vssub_vx, opivx_check)
-GEN_OPIVI_TRANS(vsaddu_vi, 1, vsaddu_vx, opivx_check)
-GEN_OPIVI_TRANS(vsadd_vi, 0, vsadd_vx, opivx_check)
+GEN_OPIVI_TRANS(vsaddu_vi, IMM_ZX, vsaddu_vx, opivx_check)
+GEN_OPIVI_TRANS(vsadd_vi, IMM_SX, vsadd_vx, opivx_check)
/* Vector Single-Width Averaging Add and Subtract */
GEN_OPIVV_TRANS(vaadd_vv, opivv_check)
@@ -2070,16 +2086,16 @@ GEN_OPIVV_TRANS(vssrl_vv, opivv_check)
GEN_OPIVV_TRANS(vssra_vv, opivv_check)
GEN_OPIVX_TRANS(vssrl_vx, opivx_check)
GEN_OPIVX_TRANS(vssra_vx, opivx_check)
-GEN_OPIVI_TRANS(vssrl_vi, 1, vssrl_vx, opivx_check)
-GEN_OPIVI_TRANS(vssra_vi, 0, vssra_vx, opivx_check)
+GEN_OPIVI_TRANS(vssrl_vi, IMM_ZX, vssrl_vx, opivx_check)
+GEN_OPIVI_TRANS(vssra_vi, IMM_SX, vssra_vx, opivx_check)
/* Vector Narrowing Fixed-Point Clip Instructions */
GEN_OPIVV_NARROW_TRANS(vnclipu_vv)
GEN_OPIVV_NARROW_TRANS(vnclip_vv)
GEN_OPIVX_NARROW_TRANS(vnclipu_vx)
GEN_OPIVX_NARROW_TRANS(vnclip_vx)
-GEN_OPIVI_NARROW_TRANS(vnclipu_vi, 1, vnclipu_vx)
-GEN_OPIVI_NARROW_TRANS(vnclip_vi, 1, vnclip_vx)
+GEN_OPIVI_NARROW_TRANS(vnclipu_vi, IMM_ZX, vnclipu_vx)
+GEN_OPIVI_NARROW_TRANS(vnclip_vi, IMM_ZX, vnclip_vx)
/*
*** Vector Float Point Arithmetic Instructions
@@ -3053,7 +3069,7 @@ static bool slideup_check(DisasContext *s, arg_rmrr *a)
GEN_OPIVX_TRANS(vslideup_vx, slideup_check)
GEN_OPIVX_TRANS(vslide1up_vx, slideup_check)
-GEN_OPIVI_TRANS(vslideup_vi, 1, vslideup_vx, slideup_check)
+GEN_OPIVI_TRANS(vslideup_vi, IMM_ZX, vslideup_vx, slideup_check)
static bool slidedown_check(DisasContext *s, arg_rmrr *a)
{
@@ -3064,7 +3080,7 @@ static bool slidedown_check(DisasContext *s, arg_rmrr *a)
GEN_OPIVX_TRANS(vslidedown_vx, slidedown_check)
GEN_OPIVX_TRANS(vslide1down_vx, slidedown_check)
-GEN_OPIVI_TRANS(vslidedown_vi, 1, vslidedown_vx, slidedown_check)
+GEN_OPIVI_TRANS(vslidedown_vi, IMM_ZX, vslidedown_vx, slidedown_check)
/* Vector Register Gather Instruction */
static bool vrgather_vv_check(DisasContext *s, arg_rmrr *a)
@@ -3143,7 +3159,8 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a)
gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h,
gen_helper_vrgather_vx_w, gen_helper_vrgather_vx_d
};
- return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s, 1);
+ return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew],
+ s, IMM_ZX);
}
return true;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 16/75] target/riscv: rvv:1.0: add translation-time nan-box helper function
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (14 preceding siblings ...)
2021-02-26 3:17 ` [PATCH v7 15/75] target/riscv: introduce more imm value modes in translator functions frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 17/75] target/riscv: rvv-1.0: configure instructions frank.chang
` (58 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
* Add fp16 nan-box check generator function, if a 16-bit input is not
properly nanboxed, then the input is replaced with the default qnan.
* Add do_nanbox() helper function to utilize gen_check_nanbox_X() to
generate the NaN-boxed floating-point values based on SEW setting.
* Apply nanbox helper in opfvf_trans().
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 35 ++++++++++++++++++++++++-
target/riscv/translate.c | 10 +++++++
2 files changed, 44 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 18a1c409fcf..ccfa93cf2f8 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2100,6 +2100,33 @@ GEN_OPIVI_NARROW_TRANS(vnclip_vi, IMM_ZX, vnclip_vx)
/*
*** Vector Float Point Arithmetic Instructions
*/
+
+/*
+ * As RVF-only cpus always have values NaN-boxed to 64-bits,
+ * RVF and RVD can be treated equally.
+ * We don't have to deal with the cases of: SEW > FLEN.
+ *
+ * If SEW < FLEN, check whether input fp register is a valid
+ * NaN-boxed value, in which case the least-significant SEW bits
+ * of the f regsiter are used, else the canonical NaN value is used.
+ */
+static void do_nanbox(DisasContext *s, TCGv_i64 out, TCGv_i64 in)
+{
+ switch (s->sew) {
+ case 1:
+ gen_check_nanbox_h(out, in);
+ break;
+ case 2:
+ gen_check_nanbox_s(out, in);
+ break;
+ case 3:
+ tcg_gen_mov_i64(out, in);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
/* Vector Single-Width Floating-Point Add/Subtract Instructions */
/*
@@ -2152,6 +2179,7 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
{
TCGv_ptr dest, src2, mask;
TCGv_i32 desc;
+ TCGv_i64 t1;
TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
@@ -2165,12 +2193,17 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
- fn(dest, mask, cpu_fpr[rs1], src2, cpu_env, desc);
+ /* NaN-box f[rs1] */
+ t1 = tcg_temp_new_i64();
+ do_nanbox(s, t1, cpu_fpr[rs1]);
+
+ fn(dest, mask, t1, src2, cpu_env, desc);
tcg_temp_free_ptr(dest);
tcg_temp_free_ptr(mask);
tcg_temp_free_ptr(src2);
tcg_temp_free_i32(desc);
+ tcg_temp_free_i64(t1);
mark_vs_dirty(s);
gen_set_label(over);
return true;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 75ed94c802b..d9a794d71e8 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -123,6 +123,16 @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
*
* Here, the result is always nan-boxed, even the canonical nan.
*/
+static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in)
+{
+ TCGv_i64 t_max = tcg_const_i64(0xffffffffffff0000ull);
+ TCGv_i64 t_nan = tcg_const_i64(0xffffffffffff7e00ull);
+
+ tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
+ tcg_temp_free_i64(t_max);
+ tcg_temp_free_i64(t_nan);
+}
+
static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in)
{
TCGv_i64 t_max = tcg_const_i64(0xffffffff00000000ull);
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 17/75] target/riscv: rvv-1.0: configure instructions
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (15 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 16/75] target/riscv: rvv:1.0: add translation-time nan-box helper function frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 18/75] target/riscv: rvv-1.0: stride load and store instructions frank.chang
` (57 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 53 +++++++++----------------
target/riscv/vector_helper.c | 14 ++++++-
2 files changed, 31 insertions(+), 36 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index ccfa93cf2f8..a3732e76e09 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -132,28 +132,29 @@ static bool require_noover_seg(const int8_t dst, const int8_t nf,
return !is_overlapped(dst, nf, src, 1);
}
-static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
+static bool do_vsetvl(DisasContext *ctx, int rd, int rs1, TCGv s2)
{
- TCGv s1, s2, dst;
+ TCGv s1, dst;
if (!require_rvv(ctx) || !has_ext(ctx, RVV)) {
return false;
}
- s2 = tcg_temp_new();
dst = tcg_temp_new();
- /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
- if (a->rs1 == 0) {
+ if (rd == 0 && rs1 == 0) {
+ s1 = tcg_temp_new();
+ tcg_gen_mov_tl(s1, cpu_vl);
+ } else if (rs1 == 0) {
/* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
s1 = tcg_const_tl(RV_VLEN_MAX);
} else {
s1 = tcg_temp_new();
- gen_get_gpr(s1, a->rs1);
+ gen_get_gpr(s1, rs1);
}
- gen_get_gpr(s2, a->rs2);
+
gen_helper_vsetvl(dst, cpu_env, s1, s2);
- gen_set_gpr(a->rd, dst);
+ gen_set_gpr(rd, dst);
mark_vs_dirty(ctx);
tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
lookup_and_goto_ptr(ctx);
@@ -165,35 +166,17 @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
return true;
}
-static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
+static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
{
- TCGv s1, s2, dst;
-
- if (!require_rvv(ctx) || !has_ext(ctx, RVV)) {
- return false;
- }
-
- s2 = tcg_const_tl(a->zimm);
- dst = tcg_temp_new();
-
- /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
- if (a->rs1 == 0) {
- /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
- s1 = tcg_const_tl(RV_VLEN_MAX);
- } else {
- s1 = tcg_temp_new();
- gen_get_gpr(s1, a->rs1);
- }
- gen_helper_vsetvl(dst, cpu_env, s1, s2);
- gen_set_gpr(a->rd, dst);
- mark_vs_dirty(ctx);
- gen_goto_tb(ctx, 0, ctx->pc_succ_insn);
- ctx->base.is_jmp = DISAS_NORETURN;
+ TCGv s2 = tcg_temp_new();
+ gen_get_gpr(s2, a->rs2);
+ return do_vsetvl(ctx, a->rd, a->rs1, s2);
+}
- tcg_temp_free(s1);
- tcg_temp_free(s2);
- tcg_temp_free(dst);
- return true;
+static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
+{
+ TCGv s2 = tcg_const_tl(a->zimm);
+ return do_vsetvl(ctx, a->rd, a->rs1, s2);
}
/* vector register offset from env */
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 89aa7cbf73f..61917d34ffe 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -31,12 +31,24 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
{
int vlmax, vl;
RISCVCPU *cpu = env_archcpu(env);
+ uint64_t lmul = FIELD_EX64(s2, VTYPE, VLMUL);
uint16_t sew = 8 << FIELD_EX64(s2, VTYPE, VSEW);
uint8_t ediv = FIELD_EX64(s2, VTYPE, VEDIV);
bool vill = FIELD_EX64(s2, VTYPE, VILL);
target_ulong reserved = FIELD_EX64(s2, VTYPE, RESERVED);
- if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0)) {
+ if (lmul & 4) {
+ /* Fractional LMUL. */
+ if (lmul == 4 ||
+ cpu->cfg.elen >> (8 - lmul) < sew) {
+ vill = true;
+ }
+ }
+
+ if ((sew > cpu->cfg.elen)
+ || vill
+ || (ediv != 0)
+ || (reserved != 0)) {
/* only set vill bit. */
env->vtype = FIELD_DP64(0, VTYPE, VILL, 1);
env->vl = 0;
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 18/75] target/riscv: rvv-1.0: stride load and store instructions
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (16 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 17/75] target/riscv: rvv-1.0: configure instructions frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 19/75] target/riscv: rvv-1.0: index " frank.chang
` (56 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/helper.h | 129 +++-----------
target/riscv/insn32.decode | 43 +++--
target/riscv/insn_trans/trans_rvv.c.inc | 227 +++++++++++-------------
target/riscv/vector_helper.c | 190 ++++++--------------
4 files changed, 194 insertions(+), 395 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index e3f3f41e891..ab865f4919f 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -79,111 +79,30 @@ DEF_HELPER_2(hyp_hlvx_wu, tl, env, tl)
/* Vector functions */
DEF_HELPER_3(vsetvl, tl, env, tl, tl)
-DEF_HELPER_5(vlb_v_b, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlb_v_b_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlb_v_h, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlb_v_h_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlb_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlb_v_w_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlb_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlb_v_d_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlh_v_h, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlh_v_h_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlh_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlh_v_w_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlh_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlh_v_d_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlw_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlw_v_w_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlw_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlw_v_d_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vle_v_b, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vle_v_b_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vle_v_h, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vle_v_h_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vle_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vle_v_w_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vle_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vle_v_d_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbu_v_b, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbu_v_b_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbu_v_h, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbu_v_h_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbu_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbu_v_w_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbu_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbu_v_d_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlhu_v_h, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlhu_v_h_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlhu_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlhu_v_w_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlhu_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlhu_v_d_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlwu_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlwu_v_w_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlwu_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlwu_v_d_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsb_v_b, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsb_v_b_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsb_v_h, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsb_v_h_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsb_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsb_v_w_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsb_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsb_v_d_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsh_v_h, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsh_v_h_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsh_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsh_v_w_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsh_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsh_v_d_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsw_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsw_v_w_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsw_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vsw_v_d_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vse_v_b, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vse_v_b_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vse_v_h, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vse_v_h_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vse_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vse_v_w_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vse_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vse_v_d_mask, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_6(vlsb_v_b, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlsb_v_h, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlsb_v_w, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlsb_v_d, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlsh_v_h, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlsh_v_w, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlsh_v_d, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlsw_v_w, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlsw_v_d, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlse_v_b, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlse_v_h, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlse_v_w, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlse_v_d, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlsbu_v_b, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlsbu_v_h, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlsbu_v_w, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlsbu_v_d, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlshu_v_h, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlshu_v_w, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlshu_v_d, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlswu_v_w, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlswu_v_d, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vssb_v_b, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vssb_v_h, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vssb_v_w, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vssb_v_d, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vssh_v_h, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vssh_v_w, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vssh_v_d, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vssw_v_w, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vssw_v_d, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vsse_v_b, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vsse_v_h, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vsse_v_w, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vsse_v_d, void, ptr, ptr, tl, tl, env, i32)
+DEF_HELPER_5(vle8_v, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vle16_v, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vle32_v, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vle64_v, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vle8_v_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vle16_v_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vle32_v_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vle64_v_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vse8_v, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vse16_v, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vse32_v, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vse64_v, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vse8_v_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vse16_v_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vse32_v_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vse64_v_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_6(vlse8_v, void, ptr, ptr, tl, tl, env, i32)
+DEF_HELPER_6(vlse16_v, void, ptr, ptr, tl, tl, env, i32)
+DEF_HELPER_6(vlse32_v, void, ptr, ptr, tl, tl, env, i32)
+DEF_HELPER_6(vlse64_v, void, ptr, ptr, tl, tl, env, i32)
+DEF_HELPER_6(vsse8_v, void, ptr, ptr, tl, tl, env, i32)
+DEF_HELPER_6(vsse16_v, void, ptr, ptr, tl, tl, env, i32)
+DEF_HELPER_6(vsse32_v, void, ptr, ptr, tl, tl, env, i32)
+DEF_HELPER_6(vsse64_v, void, ptr, ptr, tl, tl, env, i32)
DEF_HELPER_6(vlxb_v_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vlxb_v_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vlxb_v_w, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 84080dd18ca..63811c0bd19 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -240,13 +240,26 @@ hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma
# *** RV32V Extension ***
# *** Vector loads and stores are encoded within LOADFP/STORE-FP ***
-vlb_v ... 100 . 00000 ..... 000 ..... 0000111 @r2_nfvm
-vlh_v ... 100 . 00000 ..... 101 ..... 0000111 @r2_nfvm
-vlw_v ... 100 . 00000 ..... 110 ..... 0000111 @r2_nfvm
-vle_v ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm
-vlbu_v ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm
-vlhu_v ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm
-vlwu_v ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm
+# Vector unit-stride load/store insns.
+vle8_v ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm
+vle16_v ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm
+vle32_v ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm
+vle64_v ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm
+vse8_v ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm
+vse16_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm
+vse32_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm
+vse64_v ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm
+
+# Vector strided insns.
+vlse8_v ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm
+vlse16_v ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm
+vlse32_v ... 010 . ..... ..... 110 ..... 0000111 @r_nfvm
+vlse64_v ... 010 . ..... ..... 111 ..... 0000111 @r_nfvm
+vsse8_v ... 010 . ..... ..... 000 ..... 0100111 @r_nfvm
+vsse16_v ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm
+vsse32_v ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm
+vsse64_v ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm
+
vlbff_v ... 100 . 10000 ..... 000 ..... 0000111 @r2_nfvm
vlhff_v ... 100 . 10000 ..... 101 ..... 0000111 @r2_nfvm
vlwff_v ... 100 . 10000 ..... 110 ..... 0000111 @r2_nfvm
@@ -254,22 +267,6 @@ vleff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm
vlbuff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm
vlhuff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm
vlwuff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
-vsb_v ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm
-vsh_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm
-vsw_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm
-vse_v ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm
-
-vlsb_v ... 110 . ..... ..... 000 ..... 0000111 @r_nfvm
-vlsh_v ... 110 . ..... ..... 101 ..... 0000111 @r_nfvm
-vlsw_v ... 110 . ..... ..... 110 ..... 0000111 @r_nfvm
-vlse_v ... 010 . ..... ..... 111 ..... 0000111 @r_nfvm
-vlsbu_v ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm
-vlshu_v ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm
-vlswu_v ... 010 . ..... ..... 110 ..... 0000111 @r_nfvm
-vssb_v ... 010 . ..... ..... 000 ..... 0100111 @r_nfvm
-vssh_v ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm
-vssw_v ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm
-vsse_v ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm
vlxb_v ... 111 . ..... ..... 000 ..... 0000111 @r_nfvm
vlxh_v ... 111 . ..... ..... 101 ..... 0000111 @r_nfvm
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index a3732e76e09..ec65ee65adb 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -188,9 +188,42 @@ static uint32_t vreg_ofs(DisasContext *s, int reg)
/* check functions */
/*
- * In cpu_get_tb_cpu_state(), set VILL if RVV was not present.
- * So RVV is also be checked in this function.
+ * Vector unit-stride, strided, unit-stride segment, strided segment
+ * store check function.
+ *
+ * Rules to be checked here:
+ * 1. EMUL must within the range: 1/8 <= EMUL <= 8. (Section 7.3)
+ * 2. Destination vector register number is multiples of EMUL.
+ * (Section 3.3.2, 7.3)
+ * 3. The EMUL setting must be such that EMUL * NFIELDS ≤ 8. (Section 7.8)
+ * 4. Vector register numbers accessed by the segment load or store
+ * cannot increment past 31. (Section 7.8)
+ */
+static bool vext_check_store(DisasContext *s, int vd, int nf, uint8_t eew)
+{
+ int8_t emul = eew - s->sew + s->lmul;
+ return (emul >= -3 && emul <= 3) &&
+ require_align(vd, emul) &&
+ require_nf(vd, nf, emul);
+}
+
+/*
+ * Vector unit-stride, strided, unit-stride segment, strided segment
+ * load check function.
+ *
+ * Rules to be checked here:
+ * 1. All rules applies to store instructions are applies
+ * to load instructions.
+ * 2. Destination vector register group for a masked vector
+ * instruction cannot overlap the source mask register (v0).
+ * (Section 5.3)
*/
+static bool vext_check_load(DisasContext *s, int vd, int nf, int vm,
+ uint8_t eew)
+{
+ return vext_check_store(s, vd, nf, eew) && require_vm(vm, vd);
+}
+
static bool vext_check_isa_ill(DisasContext *s)
{
return !s->vill;
@@ -437,13 +470,13 @@ static bool vext_check_isa_ill(DisasContext *s)
}
/* common translation macro */
-#define GEN_VEXT_TRANS(NAME, SEQ, ARGTYPE, OP, CHECK) \
-static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE *a)\
-{ \
- if (CHECK(s, a)) { \
- return OP(s, a, SEQ); \
- } \
- return false; \
+#define GEN_VEXT_TRANS(NAME, EEW, ARGTYPE, OP, CHECK) \
+static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE * a) \
+{ \
+ if (CHECK(s, a, EEW)) { \
+ return OP(s, a, EEW); \
+ } \
+ return false; \
}
/*
@@ -493,44 +526,20 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
return true;
}
-static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
+static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew)
{
uint32_t data = 0;
gen_helper_ldst_us *fn;
- static gen_helper_ldst_us * const fns[2][7][4] = {
+ static gen_helper_ldst_us * const fns[2][4] = {
/* masked unit stride load */
- { { gen_helper_vlb_v_b_mask, gen_helper_vlb_v_h_mask,
- gen_helper_vlb_v_w_mask, gen_helper_vlb_v_d_mask },
- { NULL, gen_helper_vlh_v_h_mask,
- gen_helper_vlh_v_w_mask, gen_helper_vlh_v_d_mask },
- { NULL, NULL,
- gen_helper_vlw_v_w_mask, gen_helper_vlw_v_d_mask },
- { gen_helper_vle_v_b_mask, gen_helper_vle_v_h_mask,
- gen_helper_vle_v_w_mask, gen_helper_vle_v_d_mask },
- { gen_helper_vlbu_v_b_mask, gen_helper_vlbu_v_h_mask,
- gen_helper_vlbu_v_w_mask, gen_helper_vlbu_v_d_mask },
- { NULL, gen_helper_vlhu_v_h_mask,
- gen_helper_vlhu_v_w_mask, gen_helper_vlhu_v_d_mask },
- { NULL, NULL,
- gen_helper_vlwu_v_w_mask, gen_helper_vlwu_v_d_mask } },
+ { gen_helper_vle8_v_mask, gen_helper_vle16_v_mask,
+ gen_helper_vle32_v_mask, gen_helper_vle64_v_mask },
/* unmasked unit stride load */
- { { gen_helper_vlb_v_b, gen_helper_vlb_v_h,
- gen_helper_vlb_v_w, gen_helper_vlb_v_d },
- { NULL, gen_helper_vlh_v_h,
- gen_helper_vlh_v_w, gen_helper_vlh_v_d },
- { NULL, NULL,
- gen_helper_vlw_v_w, gen_helper_vlw_v_d },
- { gen_helper_vle_v_b, gen_helper_vle_v_h,
- gen_helper_vle_v_w, gen_helper_vle_v_d },
- { gen_helper_vlbu_v_b, gen_helper_vlbu_v_h,
- gen_helper_vlbu_v_w, gen_helper_vlbu_v_d },
- { NULL, gen_helper_vlhu_v_h,
- gen_helper_vlhu_v_w, gen_helper_vlhu_v_d },
- { NULL, NULL,
- gen_helper_vlwu_v_w, gen_helper_vlwu_v_d } }
+ { gen_helper_vle8_v, gen_helper_vle16_v,
+ gen_helper_vle32_v, gen_helper_vle64_v }
};
- fn = fns[a->vm][seq][s->sew];
+ fn = fns[a->vm][eew];
if (fn == NULL) {
return false;
}
@@ -541,48 +550,32 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
return ldst_us_trans(a->rd, a->rs1, data, fn, s, false);
}
-static bool ld_us_check(DisasContext *s, arg_r2nfvm* a)
+static bool ld_us_check(DisasContext *s, arg_r2nfvm* a, uint8_t eew)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_nf(s, a->nf));
+ return require_rvv(s) &&
+ vext_check_isa_ill(s) &&
+ vext_check_load(s, a->rd, a->nf, a->vm, eew);
}
-GEN_VEXT_TRANS(vlb_v, 0, r2nfvm, ld_us_op, ld_us_check)
-GEN_VEXT_TRANS(vlh_v, 1, r2nfvm, ld_us_op, ld_us_check)
-GEN_VEXT_TRANS(vlw_v, 2, r2nfvm, ld_us_op, ld_us_check)
-GEN_VEXT_TRANS(vle_v, 3, r2nfvm, ld_us_op, ld_us_check)
-GEN_VEXT_TRANS(vlbu_v, 4, r2nfvm, ld_us_op, ld_us_check)
-GEN_VEXT_TRANS(vlhu_v, 5, r2nfvm, ld_us_op, ld_us_check)
-GEN_VEXT_TRANS(vlwu_v, 6, r2nfvm, ld_us_op, ld_us_check)
+GEN_VEXT_TRANS(vle8_v, MO_8, r2nfvm, ld_us_op, ld_us_check)
+GEN_VEXT_TRANS(vle16_v, MO_16, r2nfvm, ld_us_op, ld_us_check)
+GEN_VEXT_TRANS(vle32_v, MO_32, r2nfvm, ld_us_op, ld_us_check)
+GEN_VEXT_TRANS(vle64_v, MO_64, r2nfvm, ld_us_op, ld_us_check)
-static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
+static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew)
{
uint32_t data = 0;
gen_helper_ldst_us *fn;
- static gen_helper_ldst_us * const fns[2][4][4] = {
- /* masked unit stride load and store */
- { { gen_helper_vsb_v_b_mask, gen_helper_vsb_v_h_mask,
- gen_helper_vsb_v_w_mask, gen_helper_vsb_v_d_mask },
- { NULL, gen_helper_vsh_v_h_mask,
- gen_helper_vsh_v_w_mask, gen_helper_vsh_v_d_mask },
- { NULL, NULL,
- gen_helper_vsw_v_w_mask, gen_helper_vsw_v_d_mask },
- { gen_helper_vse_v_b_mask, gen_helper_vse_v_h_mask,
- gen_helper_vse_v_w_mask, gen_helper_vse_v_d_mask } },
+ static gen_helper_ldst_us * const fns[2][4] = {
+ /* masked unit stride store */
+ { gen_helper_vse8_v_mask, gen_helper_vse16_v_mask,
+ gen_helper_vse32_v_mask, gen_helper_vse64_v_mask },
/* unmasked unit stride store */
- { { gen_helper_vsb_v_b, gen_helper_vsb_v_h,
- gen_helper_vsb_v_w, gen_helper_vsb_v_d },
- { NULL, gen_helper_vsh_v_h,
- gen_helper_vsh_v_w, gen_helper_vsh_v_d },
- { NULL, NULL,
- gen_helper_vsw_v_w, gen_helper_vsw_v_d },
- { gen_helper_vse_v_b, gen_helper_vse_v_h,
- gen_helper_vse_v_w, gen_helper_vse_v_d } }
+ { gen_helper_vse8_v, gen_helper_vse16_v,
+ gen_helper_vse32_v, gen_helper_vse64_v }
};
- fn = fns[a->vm][seq][s->sew];
+ fn = fns[a->vm][eew];
if (fn == NULL) {
return false;
}
@@ -593,17 +586,17 @@ static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
return ldst_us_trans(a->rd, a->rs1, data, fn, s, true);
}
-static bool st_us_check(DisasContext *s, arg_r2nfvm* a)
+static bool st_us_check(DisasContext *s, arg_r2nfvm* a, uint8_t eew)
{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_nf(s, a->nf));
+ return require_rvv(s) &&
+ vext_check_isa_ill(s) &&
+ vext_check_store(s, a->rd, a->nf, eew);
}
-GEN_VEXT_TRANS(vsb_v, 0, r2nfvm, st_us_op, st_us_check)
-GEN_VEXT_TRANS(vsh_v, 1, r2nfvm, st_us_op, st_us_check)
-GEN_VEXT_TRANS(vsw_v, 2, r2nfvm, st_us_op, st_us_check)
-GEN_VEXT_TRANS(vse_v, 3, r2nfvm, st_us_op, st_us_check)
+GEN_VEXT_TRANS(vse8_v, MO_8, r2nfvm, st_us_op, st_us_check)
+GEN_VEXT_TRANS(vse16_v, MO_16, r2nfvm, st_us_op, st_us_check)
+GEN_VEXT_TRANS(vse32_v, MO_32, r2nfvm, st_us_op, st_us_check)
+GEN_VEXT_TRANS(vse64_v, MO_64, r2nfvm, st_us_op, st_us_check)
/*
*** stride load and store
@@ -647,28 +640,16 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
return true;
}
-static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
+static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
{
uint32_t data = 0;
gen_helper_ldst_stride *fn;
- static gen_helper_ldst_stride * const fns[7][4] = {
- { gen_helper_vlsb_v_b, gen_helper_vlsb_v_h,
- gen_helper_vlsb_v_w, gen_helper_vlsb_v_d },
- { NULL, gen_helper_vlsh_v_h,
- gen_helper_vlsh_v_w, gen_helper_vlsh_v_d },
- { NULL, NULL,
- gen_helper_vlsw_v_w, gen_helper_vlsw_v_d },
- { gen_helper_vlse_v_b, gen_helper_vlse_v_h,
- gen_helper_vlse_v_w, gen_helper_vlse_v_d },
- { gen_helper_vlsbu_v_b, gen_helper_vlsbu_v_h,
- gen_helper_vlsbu_v_w, gen_helper_vlsbu_v_d },
- { NULL, gen_helper_vlshu_v_h,
- gen_helper_vlshu_v_w, gen_helper_vlshu_v_d },
- { NULL, NULL,
- gen_helper_vlswu_v_w, gen_helper_vlswu_v_d },
+ static gen_helper_ldst_stride * const fns[4] = {
+ gen_helper_vlse8_v, gen_helper_vlse16_v,
+ gen_helper_vlse32_v, gen_helper_vlse64_v
};
- fn = fns[seq][s->sew];
+ fn = fns[eew];
if (fn == NULL) {
return false;
}
@@ -679,42 +660,32 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
}
-static bool ld_stride_check(DisasContext *s, arg_rnfvm* a)
+static bool ld_stride_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_nf(s, a->nf));
+ return require_rvv(s) &&
+ vext_check_isa_ill(s) &&
+ vext_check_load(s, a->rd, a->nf, a->vm, eew);
}
-GEN_VEXT_TRANS(vlsb_v, 0, rnfvm, ld_stride_op, ld_stride_check)
-GEN_VEXT_TRANS(vlsh_v, 1, rnfvm, ld_stride_op, ld_stride_check)
-GEN_VEXT_TRANS(vlsw_v, 2, rnfvm, ld_stride_op, ld_stride_check)
-GEN_VEXT_TRANS(vlse_v, 3, rnfvm, ld_stride_op, ld_stride_check)
-GEN_VEXT_TRANS(vlsbu_v, 4, rnfvm, ld_stride_op, ld_stride_check)
-GEN_VEXT_TRANS(vlshu_v, 5, rnfvm, ld_stride_op, ld_stride_check)
-GEN_VEXT_TRANS(vlswu_v, 6, rnfvm, ld_stride_op, ld_stride_check)
+GEN_VEXT_TRANS(vlse8_v, MO_8, rnfvm, ld_stride_op, ld_stride_check)
+GEN_VEXT_TRANS(vlse16_v, MO_16, rnfvm, ld_stride_op, ld_stride_check)
+GEN_VEXT_TRANS(vlse32_v, MO_32, rnfvm, ld_stride_op, ld_stride_check)
+GEN_VEXT_TRANS(vlse64_v, MO_64, rnfvm, ld_stride_op, ld_stride_check)
-static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
+static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
{
uint32_t data = 0;
gen_helper_ldst_stride *fn;
- static gen_helper_ldst_stride * const fns[4][4] = {
+ static gen_helper_ldst_stride * const fns[4] = {
/* masked stride store */
- { gen_helper_vssb_v_b, gen_helper_vssb_v_h,
- gen_helper_vssb_v_w, gen_helper_vssb_v_d },
- { NULL, gen_helper_vssh_v_h,
- gen_helper_vssh_v_w, gen_helper_vssh_v_d },
- { NULL, NULL,
- gen_helper_vssw_v_w, gen_helper_vssw_v_d },
- { gen_helper_vsse_v_b, gen_helper_vsse_v_h,
- gen_helper_vsse_v_w, gen_helper_vsse_v_d }
+ gen_helper_vsse8_v, gen_helper_vsse16_v,
+ gen_helper_vsse32_v, gen_helper_vsse64_v
};
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
- fn = fns[seq][s->sew];
+ fn = fns[eew];
if (fn == NULL) {
return false;
}
@@ -722,17 +693,17 @@ static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, true);
}
-static bool st_stride_check(DisasContext *s, arg_rnfvm* a)
+static bool st_stride_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_nf(s, a->nf));
+ return require_rvv(s) &&
+ vext_check_isa_ill(s) &&
+ vext_check_store(s, a->rd, a->nf, eew);
}
-GEN_VEXT_TRANS(vssb_v, 0, rnfvm, st_stride_op, st_stride_check)
-GEN_VEXT_TRANS(vssh_v, 1, rnfvm, st_stride_op, st_stride_check)
-GEN_VEXT_TRANS(vssw_v, 2, rnfvm, st_stride_op, st_stride_check)
-GEN_VEXT_TRANS(vsse_v, 3, rnfvm, st_stride_op, st_stride_check)
+GEN_VEXT_TRANS(vsse8_v, MO_8, rnfvm, st_stride_op, st_stride_check)
+GEN_VEXT_TRANS(vsse16_v, MO_16, rnfvm, st_stride_op, st_stride_check)
+GEN_VEXT_TRANS(vsse32_v, MO_32, rnfvm, st_stride_op, st_stride_check)
+GEN_VEXT_TRANS(vsse64_v, MO_64, rnfvm, st_stride_op, st_stride_check)
/*
*** index load and store
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 61917d34ffe..7ce6d0fb50f 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -183,38 +183,18 @@ static inline int vext_elem_mask(void *v0, int index)
typedef void vext_ldst_elem_fn(CPURISCVState *env, target_ulong addr,
uint32_t idx, void *vd, uintptr_t retaddr);
-#define GEN_VEXT_LD_ELEM(NAME, MTYPE, ETYPE, H, LDSUF) \
+#define GEN_VEXT_LD_ELEM(NAME, ETYPE, H, LDSUF) \
static void NAME(CPURISCVState *env, abi_ptr addr, \
uint32_t idx, void *vd, uintptr_t retaddr)\
{ \
- MTYPE data; \
ETYPE *cur = ((ETYPE *)vd + H(idx)); \
- data = cpu_##LDSUF##_data_ra(env, addr, retaddr); \
- *cur = data; \
+ *cur = cpu_##LDSUF##_data_ra(env, addr, retaddr); \
} \
-GEN_VEXT_LD_ELEM(ldb_b, int8_t, int8_t, H1, ldsb)
-GEN_VEXT_LD_ELEM(ldb_h, int8_t, int16_t, H2, ldsb)
-GEN_VEXT_LD_ELEM(ldb_w, int8_t, int32_t, H4, ldsb)
-GEN_VEXT_LD_ELEM(ldb_d, int8_t, int64_t, H8, ldsb)
-GEN_VEXT_LD_ELEM(ldh_h, int16_t, int16_t, H2, ldsw)
-GEN_VEXT_LD_ELEM(ldh_w, int16_t, int32_t, H4, ldsw)
-GEN_VEXT_LD_ELEM(ldh_d, int16_t, int64_t, H8, ldsw)
-GEN_VEXT_LD_ELEM(ldw_w, int32_t, int32_t, H4, ldl)
-GEN_VEXT_LD_ELEM(ldw_d, int32_t, int64_t, H8, ldl)
-GEN_VEXT_LD_ELEM(lde_b, int8_t, int8_t, H1, ldsb)
-GEN_VEXT_LD_ELEM(lde_h, int16_t, int16_t, H2, ldsw)
-GEN_VEXT_LD_ELEM(lde_w, int32_t, int32_t, H4, ldl)
-GEN_VEXT_LD_ELEM(lde_d, int64_t, int64_t, H8, ldq)
-GEN_VEXT_LD_ELEM(ldbu_b, uint8_t, uint8_t, H1, ldub)
-GEN_VEXT_LD_ELEM(ldbu_h, uint8_t, uint16_t, H2, ldub)
-GEN_VEXT_LD_ELEM(ldbu_w, uint8_t, uint32_t, H4, ldub)
-GEN_VEXT_LD_ELEM(ldbu_d, uint8_t, uint64_t, H8, ldub)
-GEN_VEXT_LD_ELEM(ldhu_h, uint16_t, uint16_t, H2, lduw)
-GEN_VEXT_LD_ELEM(ldhu_w, uint16_t, uint32_t, H4, lduw)
-GEN_VEXT_LD_ELEM(ldhu_d, uint16_t, uint64_t, H8, lduw)
-GEN_VEXT_LD_ELEM(ldwu_w, uint32_t, uint32_t, H4, ldl)
-GEN_VEXT_LD_ELEM(ldwu_d, uint32_t, uint64_t, H8, ldl)
+GEN_VEXT_LD_ELEM(lde_b, int8_t, H1, ldsb)
+GEN_VEXT_LD_ELEM(lde_h, int16_t, H2, ldsw)
+GEN_VEXT_LD_ELEM(lde_w, int32_t, H4, ldl)
+GEN_VEXT_LD_ELEM(lde_d, int64_t, H8, ldq)
#define GEN_VEXT_ST_ELEM(NAME, ETYPE, H, STSUF) \
static void NAME(CPURISCVState *env, abi_ptr addr, \
@@ -224,15 +204,6 @@ static void NAME(CPURISCVState *env, abi_ptr addr, \
cpu_##STSUF##_data_ra(env, addr, data, retaddr); \
}
-GEN_VEXT_ST_ELEM(stb_b, int8_t, H1, stb)
-GEN_VEXT_ST_ELEM(stb_h, int16_t, H2, stb)
-GEN_VEXT_ST_ELEM(stb_w, int32_t, H4, stb)
-GEN_VEXT_ST_ELEM(stb_d, int64_t, H8, stb)
-GEN_VEXT_ST_ELEM(sth_h, int16_t, H2, stw)
-GEN_VEXT_ST_ELEM(sth_w, int32_t, H4, stw)
-GEN_VEXT_ST_ELEM(sth_d, int64_t, H8, stw)
-GEN_VEXT_ST_ELEM(stw_w, int32_t, H4, stl)
-GEN_VEXT_ST_ELEM(stw_d, int64_t, H8, stl)
GEN_VEXT_ST_ELEM(ste_b, int8_t, H1, stb)
GEN_VEXT_ST_ELEM(ste_h, int16_t, H2, stw)
GEN_VEXT_ST_ELEM(ste_w, int32_t, H4, stl)
@@ -246,8 +217,7 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
target_ulong stride, CPURISCVState *env,
uint32_t desc, uint32_t vm,
vext_ldst_elem_fn *ldst_elem,
- uint32_t esz, uint32_t msz, uintptr_t ra,
- MMUAccessType access_type)
+ uint32_t esz, uintptr_t ra, MMUAccessType access_type)
{
uint32_t i, k;
uint32_t nf = vext_nf(desc);
@@ -258,7 +228,7 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
- probe_pages(env, base + stride * i, nf * msz, ra, access_type);
+ probe_pages(env, base + stride * i, nf * esz, ra, access_type);
}
/* do real access */
for (i = 0; i < env->vl; i++) {
@@ -267,71 +237,42 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
continue;
}
while (k < nf) {
- target_ulong addr = base + stride * i + k * msz;
+ target_ulong addr = base + stride * i + k * esz;
ldst_elem(env, addr, i + k * vlmax, vd, ra);
k++;
}
}
}
-#define GEN_VEXT_LD_STRIDE(NAME, MTYPE, ETYPE, LOAD_FN) \
+#define GEN_VEXT_LD_STRIDE(NAME, ETYPE, LOAD_FN) \
void HELPER(NAME)(void *vd, void * v0, target_ulong base, \
target_ulong stride, CPURISCVState *env, \
uint32_t desc) \
{ \
uint32_t vm = vext_vm(desc); \
vext_ldst_stride(vd, v0, base, stride, env, desc, vm, LOAD_FN, \
- sizeof(ETYPE), sizeof(MTYPE), \
- GETPC(), MMU_DATA_LOAD); \
-}
-
-GEN_VEXT_LD_STRIDE(vlsb_v_b, int8_t, int8_t, ldb_b)
-GEN_VEXT_LD_STRIDE(vlsb_v_h, int8_t, int16_t, ldb_h)
-GEN_VEXT_LD_STRIDE(vlsb_v_w, int8_t, int32_t, ldb_w)
-GEN_VEXT_LD_STRIDE(vlsb_v_d, int8_t, int64_t, ldb_d)
-GEN_VEXT_LD_STRIDE(vlsh_v_h, int16_t, int16_t, ldh_h)
-GEN_VEXT_LD_STRIDE(vlsh_v_w, int16_t, int32_t, ldh_w)
-GEN_VEXT_LD_STRIDE(vlsh_v_d, int16_t, int64_t, ldh_d)
-GEN_VEXT_LD_STRIDE(vlsw_v_w, int32_t, int32_t, ldw_w)
-GEN_VEXT_LD_STRIDE(vlsw_v_d, int32_t, int64_t, ldw_d)
-GEN_VEXT_LD_STRIDE(vlse_v_b, int8_t, int8_t, lde_b)
-GEN_VEXT_LD_STRIDE(vlse_v_h, int16_t, int16_t, lde_h)
-GEN_VEXT_LD_STRIDE(vlse_v_w, int32_t, int32_t, lde_w)
-GEN_VEXT_LD_STRIDE(vlse_v_d, int64_t, int64_t, lde_d)
-GEN_VEXT_LD_STRIDE(vlsbu_v_b, uint8_t, uint8_t, ldbu_b)
-GEN_VEXT_LD_STRIDE(vlsbu_v_h, uint8_t, uint16_t, ldbu_h)
-GEN_VEXT_LD_STRIDE(vlsbu_v_w, uint8_t, uint32_t, ldbu_w)
-GEN_VEXT_LD_STRIDE(vlsbu_v_d, uint8_t, uint64_t, ldbu_d)
-GEN_VEXT_LD_STRIDE(vlshu_v_h, uint16_t, uint16_t, ldhu_h)
-GEN_VEXT_LD_STRIDE(vlshu_v_w, uint16_t, uint32_t, ldhu_w)
-GEN_VEXT_LD_STRIDE(vlshu_v_d, uint16_t, uint64_t, ldhu_d)
-GEN_VEXT_LD_STRIDE(vlswu_v_w, uint32_t, uint32_t, ldwu_w)
-GEN_VEXT_LD_STRIDE(vlswu_v_d, uint32_t, uint64_t, ldwu_d)
-
-#define GEN_VEXT_ST_STRIDE(NAME, MTYPE, ETYPE, STORE_FN) \
+ sizeof(ETYPE), GETPC(), MMU_DATA_LOAD); \
+}
+
+GEN_VEXT_LD_STRIDE(vlse8_v, int8_t, lde_b)
+GEN_VEXT_LD_STRIDE(vlse16_v, int16_t, lde_h)
+GEN_VEXT_LD_STRIDE(vlse32_v, int32_t, lde_w)
+GEN_VEXT_LD_STRIDE(vlse64_v, int64_t, lde_d)
+
+#define GEN_VEXT_ST_STRIDE(NAME, ETYPE, STORE_FN) \
void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
target_ulong stride, CPURISCVState *env, \
uint32_t desc) \
{ \
uint32_t vm = vext_vm(desc); \
vext_ldst_stride(vd, v0, base, stride, env, desc, vm, STORE_FN, \
- sizeof(ETYPE), sizeof(MTYPE), \
- GETPC(), MMU_DATA_STORE); \
-}
-
-GEN_VEXT_ST_STRIDE(vssb_v_b, int8_t, int8_t, stb_b)
-GEN_VEXT_ST_STRIDE(vssb_v_h, int8_t, int16_t, stb_h)
-GEN_VEXT_ST_STRIDE(vssb_v_w, int8_t, int32_t, stb_w)
-GEN_VEXT_ST_STRIDE(vssb_v_d, int8_t, int64_t, stb_d)
-GEN_VEXT_ST_STRIDE(vssh_v_h, int16_t, int16_t, sth_h)
-GEN_VEXT_ST_STRIDE(vssh_v_w, int16_t, int32_t, sth_w)
-GEN_VEXT_ST_STRIDE(vssh_v_d, int16_t, int64_t, sth_d)
-GEN_VEXT_ST_STRIDE(vssw_v_w, int32_t, int32_t, stw_w)
-GEN_VEXT_ST_STRIDE(vssw_v_d, int32_t, int64_t, stw_d)
-GEN_VEXT_ST_STRIDE(vsse_v_b, int8_t, int8_t, ste_b)
-GEN_VEXT_ST_STRIDE(vsse_v_h, int16_t, int16_t, ste_h)
-GEN_VEXT_ST_STRIDE(vsse_v_w, int32_t, int32_t, ste_w)
-GEN_VEXT_ST_STRIDE(vsse_v_d, int64_t, int64_t, ste_d)
+ sizeof(ETYPE), GETPC(), MMU_DATA_STORE); \
+}
+
+GEN_VEXT_ST_STRIDE(vsse8_v, int8_t, ste_b)
+GEN_VEXT_ST_STRIDE(vsse16_v, int16_t, ste_h)
+GEN_VEXT_ST_STRIDE(vsse32_v, int32_t, ste_w)
+GEN_VEXT_ST_STRIDE(vsse64_v, int64_t, ste_d)
/*
*** unit-stride: access elements stored contiguously in memory
@@ -340,20 +281,20 @@ GEN_VEXT_ST_STRIDE(vsse_v_d, int64_t, int64_t, ste_d)
/* unmasked unit-stride load and store operation*/
static void
vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
- vext_ldst_elem_fn *ldst_elem, uint32_t esz, uint32_t msz,
- uintptr_t ra, MMUAccessType access_type)
+ vext_ldst_elem_fn *ldst_elem,
+ uint32_t esz, uintptr_t ra, MMUAccessType access_type)
{
uint32_t i, k;
uint32_t nf = vext_nf(desc);
uint32_t vlmax = vext_maxsz(desc) / esz;
/* probe every access */
- probe_pages(env, base, env->vl * nf * msz, ra, access_type);
+ probe_pages(env, base, env->vl * nf * esz, ra, access_type);
/* load bytes from guest memory */
for (i = 0; i < env->vl; i++) {
k = 0;
while (k < nf) {
- target_ulong addr = base + (i * nf + k) * msz;
+ target_ulong addr = base + (i * nf + k) * esz;
ldst_elem(env, addr, i + k * vlmax, vd, ra);
k++;
}
@@ -365,76 +306,47 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
* stride = NF * sizeof (MTYPE)
*/
-#define GEN_VEXT_LD_US(NAME, MTYPE, ETYPE, LOAD_FN) \
+#define GEN_VEXT_LD_US(NAME, ETYPE, LOAD_FN) \
void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t stride = vext_nf(desc) * sizeof(MTYPE); \
+ uint32_t stride = vext_nf(desc) * sizeof(ETYPE); \
vext_ldst_stride(vd, v0, base, stride, env, desc, false, LOAD_FN, \
- sizeof(ETYPE), sizeof(MTYPE), \
- GETPC(), MMU_DATA_LOAD); \
+ sizeof(ETYPE), GETPC(), MMU_DATA_LOAD); \
} \
\
void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
CPURISCVState *env, uint32_t desc) \
{ \
vext_ldst_us(vd, base, env, desc, LOAD_FN, \
- sizeof(ETYPE), sizeof(MTYPE), GETPC(), MMU_DATA_LOAD); \
-}
-
-GEN_VEXT_LD_US(vlb_v_b, int8_t, int8_t, ldb_b)
-GEN_VEXT_LD_US(vlb_v_h, int8_t, int16_t, ldb_h)
-GEN_VEXT_LD_US(vlb_v_w, int8_t, int32_t, ldb_w)
-GEN_VEXT_LD_US(vlb_v_d, int8_t, int64_t, ldb_d)
-GEN_VEXT_LD_US(vlh_v_h, int16_t, int16_t, ldh_h)
-GEN_VEXT_LD_US(vlh_v_w, int16_t, int32_t, ldh_w)
-GEN_VEXT_LD_US(vlh_v_d, int16_t, int64_t, ldh_d)
-GEN_VEXT_LD_US(vlw_v_w, int32_t, int32_t, ldw_w)
-GEN_VEXT_LD_US(vlw_v_d, int32_t, int64_t, ldw_d)
-GEN_VEXT_LD_US(vle_v_b, int8_t, int8_t, lde_b)
-GEN_VEXT_LD_US(vle_v_h, int16_t, int16_t, lde_h)
-GEN_VEXT_LD_US(vle_v_w, int32_t, int32_t, lde_w)
-GEN_VEXT_LD_US(vle_v_d, int64_t, int64_t, lde_d)
-GEN_VEXT_LD_US(vlbu_v_b, uint8_t, uint8_t, ldbu_b)
-GEN_VEXT_LD_US(vlbu_v_h, uint8_t, uint16_t, ldbu_h)
-GEN_VEXT_LD_US(vlbu_v_w, uint8_t, uint32_t, ldbu_w)
-GEN_VEXT_LD_US(vlbu_v_d, uint8_t, uint64_t, ldbu_d)
-GEN_VEXT_LD_US(vlhu_v_h, uint16_t, uint16_t, ldhu_h)
-GEN_VEXT_LD_US(vlhu_v_w, uint16_t, uint32_t, ldhu_w)
-GEN_VEXT_LD_US(vlhu_v_d, uint16_t, uint64_t, ldhu_d)
-GEN_VEXT_LD_US(vlwu_v_w, uint32_t, uint32_t, ldwu_w)
-GEN_VEXT_LD_US(vlwu_v_d, uint32_t, uint64_t, ldwu_d)
-
-#define GEN_VEXT_ST_US(NAME, MTYPE, ETYPE, STORE_FN) \
+ sizeof(ETYPE), GETPC(), MMU_DATA_LOAD); \
+}
+
+GEN_VEXT_LD_US(vle8_v, int8_t, lde_b)
+GEN_VEXT_LD_US(vle16_v, int16_t, lde_h)
+GEN_VEXT_LD_US(vle32_v, int32_t, lde_w)
+GEN_VEXT_LD_US(vle64_v, int64_t, lde_d)
+
+#define GEN_VEXT_ST_US(NAME, ETYPE, STORE_FN) \
void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t stride = vext_nf(desc) * sizeof(MTYPE); \
+ uint32_t stride = vext_nf(desc) * sizeof(ETYPE); \
vext_ldst_stride(vd, v0, base, stride, env, desc, false, STORE_FN, \
- sizeof(ETYPE), sizeof(MTYPE), \
- GETPC(), MMU_DATA_STORE); \
+ sizeof(ETYPE), GETPC(), MMU_DATA_STORE); \
} \
\
void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
CPURISCVState *env, uint32_t desc) \
{ \
vext_ldst_us(vd, base, env, desc, STORE_FN, \
- sizeof(ETYPE), sizeof(MTYPE), GETPC(), MMU_DATA_STORE);\
-}
-
-GEN_VEXT_ST_US(vsb_v_b, int8_t, int8_t , stb_b)
-GEN_VEXT_ST_US(vsb_v_h, int8_t, int16_t, stb_h)
-GEN_VEXT_ST_US(vsb_v_w, int8_t, int32_t, stb_w)
-GEN_VEXT_ST_US(vsb_v_d, int8_t, int64_t, stb_d)
-GEN_VEXT_ST_US(vsh_v_h, int16_t, int16_t, sth_h)
-GEN_VEXT_ST_US(vsh_v_w, int16_t, int32_t, sth_w)
-GEN_VEXT_ST_US(vsh_v_d, int16_t, int64_t, sth_d)
-GEN_VEXT_ST_US(vsw_v_w, int32_t, int32_t, stw_w)
-GEN_VEXT_ST_US(vsw_v_d, int32_t, int64_t, stw_d)
-GEN_VEXT_ST_US(vse_v_b, int8_t, int8_t , ste_b)
-GEN_VEXT_ST_US(vse_v_h, int16_t, int16_t, ste_h)
-GEN_VEXT_ST_US(vse_v_w, int32_t, int32_t, ste_w)
-GEN_VEXT_ST_US(vse_v_d, int64_t, int64_t, ste_d)
+ sizeof(ETYPE), GETPC(), MMU_DATA_STORE); \
+}
+
+GEN_VEXT_ST_US(vse8_v, int8_t, ste_b)
+GEN_VEXT_ST_US(vse16_v, int16_t, ste_h)
+GEN_VEXT_ST_US(vse32_v, int32_t, ste_w)
+GEN_VEXT_ST_US(vse64_v, int64_t, ste_d)
/*
*** index: access vector element from indexed memory
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 19/75] target/riscv: rvv-1.0: index load and store instructions
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (17 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 18/75] target/riscv: rvv-1.0: stride load and store instructions frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 20/75] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns frank.chang
` (55 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/helper.h | 67 ++++----
target/riscv/insn32.decode | 21 ++-
target/riscv/insn_trans/trans_rvv.c.inc | 209 ++++++++++++++++--------
target/riscv/vector_helper.c | 89 +++++-----
4 files changed, 222 insertions(+), 164 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index ab865f4919f..98c0c6e29b6 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -103,41 +103,38 @@ DEF_HELPER_6(vsse8_v, void, ptr, ptr, tl, tl, env, i32)
DEF_HELPER_6(vsse16_v, void, ptr, ptr, tl, tl, env, i32)
DEF_HELPER_6(vsse32_v, void, ptr, ptr, tl, tl, env, i32)
DEF_HELPER_6(vsse64_v, void, ptr, ptr, tl, tl, env, i32)
-DEF_HELPER_6(vlxb_v_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxb_v_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxb_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxb_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxh_v_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxh_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxh_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxw_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxw_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxe_v_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxe_v_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxe_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxe_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxbu_v_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxbu_v_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxbu_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxbu_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxhu_v_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxhu_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxhu_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxwu_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vlxwu_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxb_v_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxb_v_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxb_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxb_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxh_v_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxh_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxh_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxw_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxw_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxe_v_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxe_v_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxe_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vsxe_v_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei8_8_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei8_16_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei8_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei16_8_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei16_16_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei16_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei16_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei32_8_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei32_16_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei32_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei32_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei64_8_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei64_16_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei64_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vlxei64_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei8_8_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei8_16_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei8_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei16_8_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei16_16_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei16_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei16_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei32_8_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei32_16_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei32_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei32_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei64_8_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei64_16_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei64_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vsxei64_64_v, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_5(vlbff_v_b, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vlbff_v_h, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vlbff_v_w, void, ptr, ptr, tl, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 63811c0bd19..c0058c6c756 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -268,18 +268,17 @@ vlbuff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm
vlhuff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm
vlwuff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
-vlxb_v ... 111 . ..... ..... 000 ..... 0000111 @r_nfvm
-vlxh_v ... 111 . ..... ..... 101 ..... 0000111 @r_nfvm
-vlxw_v ... 111 . ..... ..... 110 ..... 0000111 @r_nfvm
-vlxe_v ... 011 . ..... ..... 111 ..... 0000111 @r_nfvm
-vlxbu_v ... 011 . ..... ..... 000 ..... 0000111 @r_nfvm
-vlxhu_v ... 011 . ..... ..... 101 ..... 0000111 @r_nfvm
-vlxwu_v ... 011 . ..... ..... 110 ..... 0000111 @r_nfvm
+# Vector ordered-indexed and unordered-indexed load insns.
+vlxei8_v ... 0-1 . ..... ..... 000 ..... 0000111 @r_nfvm
+vlxei16_v ... 0-1 . ..... ..... 101 ..... 0000111 @r_nfvm
+vlxei32_v ... 0-1 . ..... ..... 110 ..... 0000111 @r_nfvm
+vlxei64_v ... 0-1 . ..... ..... 111 ..... 0000111 @r_nfvm
+
# Vector ordered-indexed and unordered-indexed store insns.
-vsxb_v ... -11 . ..... ..... 000 ..... 0100111 @r_nfvm
-vsxh_v ... -11 . ..... ..... 101 ..... 0100111 @r_nfvm
-vsxw_v ... -11 . ..... ..... 110 ..... 0100111 @r_nfvm
-vsxe_v ... -11 . ..... ..... 111 ..... 0100111 @r_nfvm
+vsxei8_v ... 0-1 . ..... ..... 000 ..... 0100111 @r_nfvm
+vsxei16_v ... 0-1 . ..... ..... 101 ..... 0100111 @r_nfvm
+vsxei32_v ... 0-1 . ..... ..... 110 ..... 0100111 @r_nfvm
+vsxei64_v ... 0-1 . ..... ..... 111 ..... 0100111 @r_nfvm
#*** Vector AMO operations are encoded under the standard AMO major opcode ***
vamoswapw_v 00001 . . ..... ..... 110 ..... 0101111 @r_wdvm
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index ec65ee65adb..320d710695f 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -126,12 +126,6 @@ static bool require_noover(const int8_t dst, const int8_t dst_lmul,
return !is_overlapped(dst, dst_size, src, src_size);
}
-static bool require_noover_seg(const int8_t dst, const int8_t nf,
- const int8_t src)
-{
- return !is_overlapped(dst, nf, src, 1);
-}
-
static bool do_vsetvl(DisasContext *ctx, int rd, int rs1, TCGv s2)
{
TCGv s1, dst;
@@ -224,9 +218,76 @@ static bool vext_check_load(DisasContext *s, int vd, int nf, int vm,
return vext_check_store(s, vd, nf, eew) && require_vm(vm, vd);
}
-static bool vext_check_isa_ill(DisasContext *s)
+/*
+ * Vector indexed, indexed segment store check function.
+ *
+ * Rules to be checked here:
+ * 1. EMUL must within the range: 1/8 <= EMUL <= 8. (Section 7.3)
+ * 2. Index vector register number is multiples of EMUL.
+ * (Section 3.3.2, 7.3)
+ * 3. Destination vector register number is multiples of LMUL.
+ * (Section 3.3.2, 7.3)
+ * 4. The EMUL setting must be such that EMUL * NFIELDS ≤ 8. (Section 7.8)
+ * 5. Vector register numbers accessed by the segment load or store
+ * cannot increment past 31. (Section 7.8)
+ */
+static bool vext_check_st_index(DisasContext *s, int vd, int vs2, int nf,
+ uint8_t eew)
{
- return !s->vill;
+ int8_t emul = eew - s->sew + s->lmul;
+ return (emul >= -3 && emul <= 3) &&
+ require_align(vs2, emul) &&
+ require_align(vd, s->lmul) &&
+ require_nf(vd, nf, s->lmul);
+}
+
+/*
+ * Vector indexed, indexed segment load check function.
+ *
+ * Rules to be checked here:
+ * 1. All rules applies to store instructions are applies
+ * to load instructions.
+ * 2. Destination vector register group for a masked vector
+ * instruction cannot overlap the source mask register (v0).
+ * (Section 5.3)
+ * 3. Destination vector register cannot overlap a source vector
+ * register (vs2) group.
+ * (Section 5.2)
+ * 4. Destination vector register groups cannot overlap
+ * the source vector register (vs2) group for
+ * indexed segment load instructions. (Section 7.8.3)
+ */
+static bool vext_check_ld_index(DisasContext *s, int vd, int vs2,
+ int nf, int vm, uint8_t eew)
+{
+ int8_t seg_vd;
+ int8_t emul = eew - s->sew + s->lmul;
+ bool ret = vext_check_st_index(s, vd, vs2, nf, eew) &&
+ require_vm(vm, vd);
+
+ /* Each segment register group has to follow overlap rules. */
+ for (int i = 0; i < nf; ++i) {
+ seg_vd = vd + (1 << MAX(s->lmul, 0)) * i;
+
+ if (eew > s->sew) {
+ if (seg_vd != vs2) {
+ ret &= require_noover(seg_vd, s->lmul, vs2, emul);
+ }
+ } else if (eew < s->sew) {
+ ret &= require_noover(seg_vd, s->lmul, vs2, emul);
+ }
+
+ /*
+ * Destination vector register groups cannot overlap
+ * the source vector register (vs2) group for
+ * indexed segment load instructions.
+ */
+ if (nf > 1) {
+ ret &= !is_overlapped(seg_vd, 1 << MAX(s->lmul, 0),
+ vs2, 1 << MAX(emul, 0));
+ }
+ }
+ return ret;
}
static bool vext_check_ss(DisasContext *s, int vd, int vs, int vm)
@@ -747,31 +808,38 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
return true;
}
-static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
+static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
{
uint32_t data = 0;
gen_helper_ldst_index *fn;
- static gen_helper_ldst_index * const fns[7][4] = {
- { gen_helper_vlxb_v_b, gen_helper_vlxb_v_h,
- gen_helper_vlxb_v_w, gen_helper_vlxb_v_d },
- { NULL, gen_helper_vlxh_v_h,
- gen_helper_vlxh_v_w, gen_helper_vlxh_v_d },
- { NULL, NULL,
- gen_helper_vlxw_v_w, gen_helper_vlxw_v_d },
- { gen_helper_vlxe_v_b, gen_helper_vlxe_v_h,
- gen_helper_vlxe_v_w, gen_helper_vlxe_v_d },
- { gen_helper_vlxbu_v_b, gen_helper_vlxbu_v_h,
- gen_helper_vlxbu_v_w, gen_helper_vlxbu_v_d },
- { NULL, gen_helper_vlxhu_v_h,
- gen_helper_vlxhu_v_w, gen_helper_vlxhu_v_d },
- { NULL, NULL,
- gen_helper_vlxwu_v_w, gen_helper_vlxwu_v_d },
+ static gen_helper_ldst_index * const fns[4][4] = {
+ /*
+ * offset vector register group EEW = 8,
+ * data vector register group EEW = SEW
+ */
+ { gen_helper_vlxei8_8_v, gen_helper_vlxei8_16_v,
+ gen_helper_vlxei8_32_v, gen_helper_vlxei8_64_v },
+ /*
+ * offset vector register group EEW = 16,
+ * data vector register group EEW = SEW
+ */
+ { gen_helper_vlxei16_8_v, gen_helper_vlxei16_16_v,
+ gen_helper_vlxei16_32_v, gen_helper_vlxei16_64_v },
+ /*
+ * offset vector register group EEW = 32,
+ * data vector register group EEW = SEW
+ */
+ { gen_helper_vlxei32_8_v, gen_helper_vlxei32_16_v,
+ gen_helper_vlxei32_32_v, gen_helper_vlxei32_64_v },
+ /*
+ * offset vector register group EEW = 64,
+ * data vector register group EEW = SEW
+ */
+ { gen_helper_vlxei64_8_v, gen_helper_vlxei64_16_v,
+ gen_helper_vlxei64_32_v, gen_helper_vlxei64_64_v }
};
- fn = fns[seq][s->sew];
- if (fn == NULL) {
- return false;
- }
+ fn = fns[eew][s->sew];
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
@@ -779,50 +847,50 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
}
-/*
- * For vector indexed segment loads, the destination vector register
- * groups cannot overlap the source vector register group (specified by
- * `vs2`), else an illegal instruction exception is raised.
- */
-static bool ld_index_check(DisasContext *s, arg_rnfvm* a)
+static bool ld_index_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
{
- return (vext_check_isa_ill(s) &&
- vext_check_overlap_mask(s, a->rd, a->vm, false) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_nf(s, a->nf) &&
- ((a->nf == 1) ||
- vext_check_overlap_group(a->rd, a->nf << s->lmul,
- a->rs2, 1 << s->lmul)));
+ return require_rvv(s) &&
+ vext_check_isa_ill(s) &&
+ vext_check_ld_index(s, a->rd, a->rs2, a->nf, a->vm, eew);
}
-GEN_VEXT_TRANS(vlxb_v, 0, rnfvm, ld_index_op, ld_index_check)
-GEN_VEXT_TRANS(vlxh_v, 1, rnfvm, ld_index_op, ld_index_check)
-GEN_VEXT_TRANS(vlxw_v, 2, rnfvm, ld_index_op, ld_index_check)
-GEN_VEXT_TRANS(vlxe_v, 3, rnfvm, ld_index_op, ld_index_check)
-GEN_VEXT_TRANS(vlxbu_v, 4, rnfvm, ld_index_op, ld_index_check)
-GEN_VEXT_TRANS(vlxhu_v, 5, rnfvm, ld_index_op, ld_index_check)
-GEN_VEXT_TRANS(vlxwu_v, 6, rnfvm, ld_index_op, ld_index_check)
+GEN_VEXT_TRANS(vlxei8_v, MO_8, rnfvm, ld_index_op, ld_index_check)
+GEN_VEXT_TRANS(vlxei16_v, MO_16, rnfvm, ld_index_op, ld_index_check)
+GEN_VEXT_TRANS(vlxei32_v, MO_32, rnfvm, ld_index_op, ld_index_check)
+GEN_VEXT_TRANS(vlxei64_v, MO_64, rnfvm, ld_index_op, ld_index_check)
-static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
+static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
{
uint32_t data = 0;
gen_helper_ldst_index *fn;
static gen_helper_ldst_index * const fns[4][4] = {
- { gen_helper_vsxb_v_b, gen_helper_vsxb_v_h,
- gen_helper_vsxb_v_w, gen_helper_vsxb_v_d },
- { NULL, gen_helper_vsxh_v_h,
- gen_helper_vsxh_v_w, gen_helper_vsxh_v_d },
- { NULL, NULL,
- gen_helper_vsxw_v_w, gen_helper_vsxw_v_d },
- { gen_helper_vsxe_v_b, gen_helper_vsxe_v_h,
- gen_helper_vsxe_v_w, gen_helper_vsxe_v_d }
+ /*
+ * offset vector register group EEW = 8,
+ * data vector register group EEW = SEW
+ */
+ { gen_helper_vsxei8_8_v, gen_helper_vsxei8_16_v,
+ gen_helper_vsxei8_32_v, gen_helper_vsxei8_64_v },
+ /*
+ * offset vector register group EEW = 16,
+ * data vector register group EEW = SEW
+ */
+ { gen_helper_vsxei16_8_v, gen_helper_vsxei16_16_v,
+ gen_helper_vsxei16_32_v, gen_helper_vsxei16_64_v },
+ /*
+ * offset vector register group EEW = 32,
+ * data vector register group EEW = SEW
+ */
+ { gen_helper_vsxei32_8_v, gen_helper_vsxei32_16_v,
+ gen_helper_vsxei32_32_v, gen_helper_vsxei32_64_v },
+ /*
+ * offset vector register group EEW = 64,
+ * data vector register group EEW = SEW
+ */
+ { gen_helper_vsxei64_8_v, gen_helper_vsxei64_16_v,
+ gen_helper_vsxei64_32_v, gen_helper_vsxei64_64_v }
};
- fn = fns[seq][s->sew];
- if (fn == NULL) {
- return false;
- }
+ fn = fns[eew][s->sew];
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
@@ -830,18 +898,17 @@ static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, true);
}
-static bool st_index_check(DisasContext *s, arg_rnfvm* a)
+static bool st_index_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
{
- return (vext_check_isa_ill(s) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- vext_check_nf(s, a->nf));
+ return require_rvv(s) &&
+ vext_check_isa_ill(s) &&
+ vext_check_st_index(s, a->rd, a->rs2, a->nf, eew);
}
-GEN_VEXT_TRANS(vsxb_v, 0, rnfvm, st_index_op, st_index_check)
-GEN_VEXT_TRANS(vsxh_v, 1, rnfvm, st_index_op, st_index_check)
-GEN_VEXT_TRANS(vsxw_v, 2, rnfvm, st_index_op, st_index_check)
-GEN_VEXT_TRANS(vsxe_v, 3, rnfvm, st_index_op, st_index_check)
+GEN_VEXT_TRANS(vsxei8_v, MO_8, rnfvm, st_index_op, st_index_check)
+GEN_VEXT_TRANS(vsxei16_v, MO_16, rnfvm, st_index_op, st_index_check)
+GEN_VEXT_TRANS(vsxei32_v, MO_32, rnfvm, st_index_op, st_index_check)
+GEN_VEXT_TRANS(vsxei64_v, MO_64, rnfvm, st_index_op, st_index_check)
/*
*** unit stride fault-only-first load
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 7ce6d0fb50f..368259f75a0 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -371,8 +371,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
void *vs2, CPURISCVState *env, uint32_t desc,
vext_get_index_addr get_index_addr,
vext_ldst_elem_fn *ldst_elem,
- uint32_t esz, uint32_t msz, uintptr_t ra,
- MMUAccessType access_type)
+ uint32_t esz, uintptr_t ra, MMUAccessType access_type)
{
uint32_t i, k;
uint32_t nf = vext_nf(desc);
@@ -384,7 +383,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
- probe_pages(env, get_index_addr(base, i, vs2), nf * msz, ra,
+ probe_pages(env, get_index_addr(base, i, vs2), nf * esz, ra,
access_type);
}
/* load bytes from guest memory */
@@ -394,67 +393,63 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
continue;
}
while (k < nf) {
- abi_ptr addr = get_index_addr(base, i, vs2) + k * msz;
+ abi_ptr addr = get_index_addr(base, i, vs2) + k * esz;
ldst_elem(env, addr, i + k * vlmax, vd, ra);
k++;
}
}
}
-#define GEN_VEXT_LD_INDEX(NAME, MTYPE, ETYPE, INDEX_FN, LOAD_FN) \
+#define GEN_VEXT_LD_INDEX(NAME, ETYPE, INDEX_FN, LOAD_FN) \
void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \
- LOAD_FN, sizeof(ETYPE), sizeof(MTYPE), \
- GETPC(), MMU_DATA_LOAD); \
-}
-
-GEN_VEXT_LD_INDEX(vlxb_v_b, int8_t, int8_t, idx_b, ldb_b)
-GEN_VEXT_LD_INDEX(vlxb_v_h, int8_t, int16_t, idx_h, ldb_h)
-GEN_VEXT_LD_INDEX(vlxb_v_w, int8_t, int32_t, idx_w, ldb_w)
-GEN_VEXT_LD_INDEX(vlxb_v_d, int8_t, int64_t, idx_d, ldb_d)
-GEN_VEXT_LD_INDEX(vlxh_v_h, int16_t, int16_t, idx_h, ldh_h)
-GEN_VEXT_LD_INDEX(vlxh_v_w, int16_t, int32_t, idx_w, ldh_w)
-GEN_VEXT_LD_INDEX(vlxh_v_d, int16_t, int64_t, idx_d, ldh_d)
-GEN_VEXT_LD_INDEX(vlxw_v_w, int32_t, int32_t, idx_w, ldw_w)
-GEN_VEXT_LD_INDEX(vlxw_v_d, int32_t, int64_t, idx_d, ldw_d)
-GEN_VEXT_LD_INDEX(vlxe_v_b, int8_t, int8_t, idx_b, lde_b)
-GEN_VEXT_LD_INDEX(vlxe_v_h, int16_t, int16_t, idx_h, lde_h)
-GEN_VEXT_LD_INDEX(vlxe_v_w, int32_t, int32_t, idx_w, lde_w)
-GEN_VEXT_LD_INDEX(vlxe_v_d, int64_t, int64_t, idx_d, lde_d)
-GEN_VEXT_LD_INDEX(vlxbu_v_b, uint8_t, uint8_t, idx_b, ldbu_b)
-GEN_VEXT_LD_INDEX(vlxbu_v_h, uint8_t, uint16_t, idx_h, ldbu_h)
-GEN_VEXT_LD_INDEX(vlxbu_v_w, uint8_t, uint32_t, idx_w, ldbu_w)
-GEN_VEXT_LD_INDEX(vlxbu_v_d, uint8_t, uint64_t, idx_d, ldbu_d)
-GEN_VEXT_LD_INDEX(vlxhu_v_h, uint16_t, uint16_t, idx_h, ldhu_h)
-GEN_VEXT_LD_INDEX(vlxhu_v_w, uint16_t, uint32_t, idx_w, ldhu_w)
-GEN_VEXT_LD_INDEX(vlxhu_v_d, uint16_t, uint64_t, idx_d, ldhu_d)
-GEN_VEXT_LD_INDEX(vlxwu_v_w, uint32_t, uint32_t, idx_w, ldwu_w)
-GEN_VEXT_LD_INDEX(vlxwu_v_d, uint32_t, uint64_t, idx_d, ldwu_d)
-
-#define GEN_VEXT_ST_INDEX(NAME, MTYPE, ETYPE, INDEX_FN, STORE_FN)\
+ LOAD_FN, sizeof(ETYPE), GETPC(), MMU_DATA_LOAD); \
+}
+
+GEN_VEXT_LD_INDEX(vlxei8_8_v, int8_t, idx_b, lde_b)
+GEN_VEXT_LD_INDEX(vlxei8_16_v, int16_t, idx_b, lde_h)
+GEN_VEXT_LD_INDEX(vlxei8_32_v, int32_t, idx_b, lde_w)
+GEN_VEXT_LD_INDEX(vlxei8_64_v, int64_t, idx_b, lde_d)
+GEN_VEXT_LD_INDEX(vlxei16_8_v, int8_t, idx_h, lde_b)
+GEN_VEXT_LD_INDEX(vlxei16_16_v, int16_t, idx_h, lde_h)
+GEN_VEXT_LD_INDEX(vlxei16_32_v, int32_t, idx_h, lde_w)
+GEN_VEXT_LD_INDEX(vlxei16_64_v, int64_t, idx_h, lde_d)
+GEN_VEXT_LD_INDEX(vlxei32_8_v, int8_t, idx_w, lde_b)
+GEN_VEXT_LD_INDEX(vlxei32_16_v, int16_t, idx_w, lde_h)
+GEN_VEXT_LD_INDEX(vlxei32_32_v, int32_t, idx_w, lde_w)
+GEN_VEXT_LD_INDEX(vlxei32_64_v, int64_t, idx_w, lde_d)
+GEN_VEXT_LD_INDEX(vlxei64_8_v, int8_t, idx_d, lde_b)
+GEN_VEXT_LD_INDEX(vlxei64_16_v, int16_t, idx_d, lde_h)
+GEN_VEXT_LD_INDEX(vlxei64_32_v, int32_t, idx_d, lde_w)
+GEN_VEXT_LD_INDEX(vlxei64_64_v, int64_t, idx_d, lde_d)
+
+#define GEN_VEXT_ST_INDEX(NAME, ETYPE, INDEX_FN, STORE_FN) \
void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \
- STORE_FN, sizeof(ETYPE), sizeof(MTYPE), \
+ STORE_FN, sizeof(ETYPE), \
GETPC(), MMU_DATA_STORE); \
}
-GEN_VEXT_ST_INDEX(vsxb_v_b, int8_t, int8_t, idx_b, stb_b)
-GEN_VEXT_ST_INDEX(vsxb_v_h, int8_t, int16_t, idx_h, stb_h)
-GEN_VEXT_ST_INDEX(vsxb_v_w, int8_t, int32_t, idx_w, stb_w)
-GEN_VEXT_ST_INDEX(vsxb_v_d, int8_t, int64_t, idx_d, stb_d)
-GEN_VEXT_ST_INDEX(vsxh_v_h, int16_t, int16_t, idx_h, sth_h)
-GEN_VEXT_ST_INDEX(vsxh_v_w, int16_t, int32_t, idx_w, sth_w)
-GEN_VEXT_ST_INDEX(vsxh_v_d, int16_t, int64_t, idx_d, sth_d)
-GEN_VEXT_ST_INDEX(vsxw_v_w, int32_t, int32_t, idx_w, stw_w)
-GEN_VEXT_ST_INDEX(vsxw_v_d, int32_t, int64_t, idx_d, stw_d)
-GEN_VEXT_ST_INDEX(vsxe_v_b, int8_t, int8_t, idx_b, ste_b)
-GEN_VEXT_ST_INDEX(vsxe_v_h, int16_t, int16_t, idx_h, ste_h)
-GEN_VEXT_ST_INDEX(vsxe_v_w, int32_t, int32_t, idx_w, ste_w)
-GEN_VEXT_ST_INDEX(vsxe_v_d, int64_t, int64_t, idx_d, ste_d)
+GEN_VEXT_ST_INDEX(vsxei8_8_v, int8_t, idx_b, ste_b)
+GEN_VEXT_ST_INDEX(vsxei8_16_v, int16_t, idx_b, ste_h)
+GEN_VEXT_ST_INDEX(vsxei8_32_v, int32_t, idx_b, ste_w)
+GEN_VEXT_ST_INDEX(vsxei8_64_v, int64_t, idx_b, ste_d)
+GEN_VEXT_ST_INDEX(vsxei16_8_v, int8_t, idx_h, ste_b)
+GEN_VEXT_ST_INDEX(vsxei16_16_v, int16_t, idx_h, ste_h)
+GEN_VEXT_ST_INDEX(vsxei16_32_v, int32_t, idx_h, ste_w)
+GEN_VEXT_ST_INDEX(vsxei16_64_v, int64_t, idx_h, ste_d)
+GEN_VEXT_ST_INDEX(vsxei32_8_v, int8_t, idx_w, ste_b)
+GEN_VEXT_ST_INDEX(vsxei32_16_v, int16_t, idx_w, ste_h)
+GEN_VEXT_ST_INDEX(vsxei32_32_v, int32_t, idx_w, ste_w)
+GEN_VEXT_ST_INDEX(vsxei32_64_v, int64_t, idx_w, ste_d)
+GEN_VEXT_ST_INDEX(vsxei64_8_v, int8_t, idx_d, ste_b)
+GEN_VEXT_ST_INDEX(vsxei64_16_v, int16_t, idx_d, ste_h)
+GEN_VEXT_ST_INDEX(vsxei64_32_v, int32_t, idx_d, ste_w)
+GEN_VEXT_ST_INDEX(vsxei64_64_v, int64_t, idx_d, ste_d)
/*
*** unit-stride fault-only-fisrt load instructions
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 20/75] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (18 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 19/75] target/riscv: rvv-1.0: index " frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 21/75] target/riscv: rvv-1.0: fault-only-first unit stride load frank.chang
` (54 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Alistair Francis, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
Replace ETYPE from signed int to unsigned int to prevent index overflow
issue, which would lead to wrong index address.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/vector_helper.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 368259f75a0..9349a36b41b 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -361,10 +361,10 @@ static target_ulong NAME(target_ulong base, \
return (base + *((ETYPE *)vs2 + H(idx))); \
}
-GEN_VEXT_GET_INDEX_ADDR(idx_b, int8_t, H1)
-GEN_VEXT_GET_INDEX_ADDR(idx_h, int16_t, H2)
-GEN_VEXT_GET_INDEX_ADDR(idx_w, int32_t, H4)
-GEN_VEXT_GET_INDEX_ADDR(idx_d, int64_t, H8)
+GEN_VEXT_GET_INDEX_ADDR(idx_b, uint8_t, H1)
+GEN_VEXT_GET_INDEX_ADDR(idx_h, uint16_t, H2)
+GEN_VEXT_GET_INDEX_ADDR(idx_w, uint32_t, H4)
+GEN_VEXT_GET_INDEX_ADDR(idx_d, uint64_t, H8)
static inline void
vext_ldst_index(void *vd, void *v0, target_ulong base,
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 21/75] target/riscv: rvv-1.0: fault-only-first unit stride load
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (19 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 20/75] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 22/75] target/riscv: rvv-1.0: amo operations frank.chang
` (53 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/helper.h | 27 +++---------
target/riscv/insn32.decode | 14 +++----
target/riscv/insn_trans/trans_rvv.c.inc | 33 ++++-----------
target/riscv/vector_helper.c | 56 +++++++++----------------
4 files changed, 39 insertions(+), 91 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 98c0c6e29b6..5eb2404a75a 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -135,28 +135,11 @@ DEF_HELPER_6(vsxei64_8_v, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vsxei64_16_v, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vsxei64_32_v, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vsxei64_64_v, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_5(vlbff_v_b, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbff_v_h, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbff_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbff_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlhff_v_h, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlhff_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlhff_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlwff_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlwff_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vleff_v_b, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vleff_v_h, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vleff_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vleff_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbuff_v_b, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbuff_v_h, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbuff_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlbuff_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlhuff_v_h, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlhuff_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlhuff_v_d, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlwuff_v_w, void, ptr, ptr, tl, env, i32)
-DEF_HELPER_5(vlwuff_v_d, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vle8ff_v, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vle16ff_v, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vle32ff_v, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vle64ff_v, void, ptr, ptr, tl, env, i32)
+
#ifdef TARGET_RISCV64
DEF_HELPER_6(vamoswapw_v_d, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vamoswapd_v_d, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index c0058c6c756..9e4fe72560b 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -260,14 +260,6 @@ vsse16_v ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm
vsse32_v ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm
vsse64_v ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm
-vlbff_v ... 100 . 10000 ..... 000 ..... 0000111 @r2_nfvm
-vlhff_v ... 100 . 10000 ..... 101 ..... 0000111 @r2_nfvm
-vlwff_v ... 100 . 10000 ..... 110 ..... 0000111 @r2_nfvm
-vleff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm
-vlbuff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm
-vlhuff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm
-vlwuff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
-
# Vector ordered-indexed and unordered-indexed load insns.
vlxei8_v ... 0-1 . ..... ..... 000 ..... 0000111 @r_nfvm
vlxei16_v ... 0-1 . ..... ..... 101 ..... 0000111 @r_nfvm
@@ -280,6 +272,12 @@ vsxei16_v ... 0-1 . ..... ..... 101 ..... 0100111 @r_nfvm
vsxei32_v ... 0-1 . ..... ..... 110 ..... 0100111 @r_nfvm
vsxei64_v ... 0-1 . ..... ..... 111 ..... 0100111 @r_nfvm
+# Vector unit-stride fault-only-first load insns.
+vle8ff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm
+vle16ff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm
+vle32ff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
+vle64ff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm
+
#*** Vector AMO operations are encoded under the standard AMO major opcode ***
vamoswapw_v 00001 . . ..... ..... 110 ..... 0101111 @r_wdvm
vamoaddw_v 00000 . . ..... ..... 110 ..... 0101111 @r_wdvm
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 320d710695f..20161b1ebe3 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -943,28 +943,16 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
return true;
}
-static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
+static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew)
{
uint32_t data = 0;
gen_helper_ldst_us *fn;
- static gen_helper_ldst_us * const fns[7][4] = {
- { gen_helper_vlbff_v_b, gen_helper_vlbff_v_h,
- gen_helper_vlbff_v_w, gen_helper_vlbff_v_d },
- { NULL, gen_helper_vlhff_v_h,
- gen_helper_vlhff_v_w, gen_helper_vlhff_v_d },
- { NULL, NULL,
- gen_helper_vlwff_v_w, gen_helper_vlwff_v_d },
- { gen_helper_vleff_v_b, gen_helper_vleff_v_h,
- gen_helper_vleff_v_w, gen_helper_vleff_v_d },
- { gen_helper_vlbuff_v_b, gen_helper_vlbuff_v_h,
- gen_helper_vlbuff_v_w, gen_helper_vlbuff_v_d },
- { NULL, gen_helper_vlhuff_v_h,
- gen_helper_vlhuff_v_w, gen_helper_vlhuff_v_d },
- { NULL, NULL,
- gen_helper_vlwuff_v_w, gen_helper_vlwuff_v_d }
+ static gen_helper_ldst_us * const fns[4] = {
+ gen_helper_vle8ff_v, gen_helper_vle16ff_v,
+ gen_helper_vle32ff_v, gen_helper_vle64ff_v
};
- fn = fns[seq][s->sew];
+ fn = fns[eew];
if (fn == NULL) {
return false;
}
@@ -975,13 +963,10 @@ static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
return ldff_trans(a->rd, a->rs1, data, fn, s);
}
-GEN_VEXT_TRANS(vlbff_v, 0, r2nfvm, ldff_op, ld_us_check)
-GEN_VEXT_TRANS(vlhff_v, 1, r2nfvm, ldff_op, ld_us_check)
-GEN_VEXT_TRANS(vlwff_v, 2, r2nfvm, ldff_op, ld_us_check)
-GEN_VEXT_TRANS(vleff_v, 3, r2nfvm, ldff_op, ld_us_check)
-GEN_VEXT_TRANS(vlbuff_v, 4, r2nfvm, ldff_op, ld_us_check)
-GEN_VEXT_TRANS(vlhuff_v, 5, r2nfvm, ldff_op, ld_us_check)
-GEN_VEXT_TRANS(vlwuff_v, 6, r2nfvm, ldff_op, ld_us_check)
+GEN_VEXT_TRANS(vle8ff_v, MO_8, r2nfvm, ldff_op, ld_us_check)
+GEN_VEXT_TRANS(vle16ff_v, MO_16, r2nfvm, ldff_op, ld_us_check)
+GEN_VEXT_TRANS(vle32ff_v, MO_32, r2nfvm, ldff_op, ld_us_check)
+GEN_VEXT_TRANS(vle64ff_v, MO_64, r2nfvm, ldff_op, ld_us_check)
/*
*** vector atomic operation
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 9349a36b41b..fd398af8550 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -458,7 +458,7 @@ static inline void
vext_ldff(void *vd, void *v0, target_ulong base,
CPURISCVState *env, uint32_t desc,
vext_ldst_elem_fn *ldst_elem,
- uint32_t esz, uint32_t msz, uintptr_t ra)
+ uint32_t esz, uintptr_t ra)
{
void *host;
uint32_t i, k, vl = 0;
@@ -472,24 +472,24 @@ vext_ldff(void *vd, void *v0, target_ulong base,
if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
- addr = base + nf * i * msz;
+ addr = base + nf * i * esz;
if (i == 0) {
- probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD);
+ probe_pages(env, addr, nf * esz, ra, MMU_DATA_LOAD);
} else {
/* if it triggers an exception, no need to check watchpoint */
- remain = nf * msz;
+ remain = nf * esz;
while (remain > 0) {
offset = -(addr | TARGET_PAGE_MASK);
host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD,
cpu_mmu_index(env, false));
if (host) {
#ifdef CONFIG_USER_ONLY
- if (page_check_range(addr, nf * msz, PAGE_READ) < 0) {
+ if (page_check_range(addr, nf * esz, PAGE_READ) < 0) {
vl = i;
goto ProbeSuccess;
}
#else
- probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD);
+ probe_pages(env, addr, nf * esz, ra, MMU_DATA_LOAD);
#endif
} else {
vl = i;
@@ -514,43 +514,25 @@ ProbeSuccess:
continue;
}
while (k < nf) {
- target_ulong addr = base + (i * nf + k) * msz;
+ target_ulong addr = base + (i * nf + k) * esz;
ldst_elem(env, addr, i + k * vlmax, vd, ra);
k++;
}
}
}
-#define GEN_VEXT_LDFF(NAME, MTYPE, ETYPE, LOAD_FN) \
-void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
- CPURISCVState *env, uint32_t desc) \
-{ \
- vext_ldff(vd, v0, base, env, desc, LOAD_FN, \
- sizeof(ETYPE), sizeof(MTYPE), GETPC()); \
-}
-
-GEN_VEXT_LDFF(vlbff_v_b, int8_t, int8_t, ldb_b)
-GEN_VEXT_LDFF(vlbff_v_h, int8_t, int16_t, ldb_h)
-GEN_VEXT_LDFF(vlbff_v_w, int8_t, int32_t, ldb_w)
-GEN_VEXT_LDFF(vlbff_v_d, int8_t, int64_t, ldb_d)
-GEN_VEXT_LDFF(vlhff_v_h, int16_t, int16_t, ldh_h)
-GEN_VEXT_LDFF(vlhff_v_w, int16_t, int32_t, ldh_w)
-GEN_VEXT_LDFF(vlhff_v_d, int16_t, int64_t, ldh_d)
-GEN_VEXT_LDFF(vlwff_v_w, int32_t, int32_t, ldw_w)
-GEN_VEXT_LDFF(vlwff_v_d, int32_t, int64_t, ldw_d)
-GEN_VEXT_LDFF(vleff_v_b, int8_t, int8_t, lde_b)
-GEN_VEXT_LDFF(vleff_v_h, int16_t, int16_t, lde_h)
-GEN_VEXT_LDFF(vleff_v_w, int32_t, int32_t, lde_w)
-GEN_VEXT_LDFF(vleff_v_d, int64_t, int64_t, lde_d)
-GEN_VEXT_LDFF(vlbuff_v_b, uint8_t, uint8_t, ldbu_b)
-GEN_VEXT_LDFF(vlbuff_v_h, uint8_t, uint16_t, ldbu_h)
-GEN_VEXT_LDFF(vlbuff_v_w, uint8_t, uint32_t, ldbu_w)
-GEN_VEXT_LDFF(vlbuff_v_d, uint8_t, uint64_t, ldbu_d)
-GEN_VEXT_LDFF(vlhuff_v_h, uint16_t, uint16_t, ldhu_h)
-GEN_VEXT_LDFF(vlhuff_v_w, uint16_t, uint32_t, ldhu_w)
-GEN_VEXT_LDFF(vlhuff_v_d, uint16_t, uint64_t, ldhu_d)
-GEN_VEXT_LDFF(vlwuff_v_w, uint32_t, uint32_t, ldwu_w)
-GEN_VEXT_LDFF(vlwuff_v_d, uint32_t, uint64_t, ldwu_d)
+#define GEN_VEXT_LDFF(NAME, ETYPE, LOAD_FN) \
+void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ vext_ldff(vd, v0, base, env, desc, LOAD_FN, \
+ sizeof(ETYPE), GETPC()); \
+}
+
+GEN_VEXT_LDFF(vle8ff_v, int8_t, lde_b)
+GEN_VEXT_LDFF(vle16ff_v, int16_t, lde_h)
+GEN_VEXT_LDFF(vle32ff_v, int32_t, lde_w)
+GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d)
/*
*** Vector AMO Operations (Zvamo)
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 22/75] target/riscv: rvv-1.0: amo operations
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (20 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 21/75] target/riscv: rvv-1.0: fault-only-first unit stride load frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 23/75] target/riscv: rvv-1.0: load/store whole register instructions frank.chang
` (52 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/helper.h | 100 +++++++---
target/riscv/insn32-64.decode | 18 +-
target/riscv/insn32.decode | 36 +++-
target/riscv/insn_trans/trans_rvv.c.inc | 229 +++++++++++++++--------
target/riscv/vector_helper.c | 232 ++++++++++++++++--------
5 files changed, 414 insertions(+), 201 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 5eb2404a75a..b3fa28d4354 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -140,36 +140,80 @@ DEF_HELPER_5(vle16ff_v, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vle32ff_v, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vle64ff_v, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_6(vamoswapei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoswapei8_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoswapei16_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoswapei16_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoswapei32_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoswapei32_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoaddei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoaddei8_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoaddei16_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoaddei16_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoaddei32_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoaddei32_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoxorei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoxorei8_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoxorei16_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoxorei16_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoxorei32_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoxorei32_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoandei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoandei8_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoandei16_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoandei16_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoandei32_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoandei32_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoorei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoorei8_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoorei16_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoorei16_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoorei32_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoorei32_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominei8_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominei16_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominei16_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominei32_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominei32_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxei8_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxei16_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxei16_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxei32_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxei32_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominuei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominuei8_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominuei16_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominuei16_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominuei32_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominuei32_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxuei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxuei8_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxuei16_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxuei16_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxuei32_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxuei32_64_v, void, ptr, ptr, tl, ptr, env, i32)
#ifdef TARGET_RISCV64
-DEF_HELPER_6(vamoswapw_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoswapd_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoaddw_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoaddd_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoxorw_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoxord_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoandw_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoandd_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoorw_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoord_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamominw_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamomind_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamomaxw_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamomaxd_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamominuw_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamominud_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamomaxuw_v_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamomaxud_v_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoswapei64_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoswapei64_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoaddei64_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoaddei64_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoxorei64_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoxorei64_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoandei64_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoandei64_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoorei64_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamoorei64_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominei64_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominei64_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxei64_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxei64_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominuei64_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamominuei64_64_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxuei64_32_v, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vamomaxuei64_64_v, void, ptr, ptr, tl, ptr, env, i32)
#endif
-DEF_HELPER_6(vamoswapw_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoaddw_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoxorw_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoandw_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamoorw_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamominw_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamomaxw_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamominuw_v_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vamomaxuw_v_w, void, ptr, ptr, tl, ptr, env, i32)
-
DEF_HELPER_6(vadd_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 8157dee8b7c..67ddb184a47 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -58,15 +58,15 @@ amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st
amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st
#*** Vector AMO operations (in addition to Zvamo) ***
-vamoswapd_v 00001 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamoaddd_v 00000 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamoxord_v 00100 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamoandd_v 01100 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamoord_v 01000 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamomind_v 10000 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamomaxd_v 10100 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamominud_v 11000 . . ..... ..... 111 ..... 0101111 @r_wdvm
-vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamoswapei64_v 00001 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamoaddei64_v 00000 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamoxorei64_v 00100 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamoandei64_v 01100 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamoorei64_v 01000 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamominei64_v 10000 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamomaxei64_v 10100 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamominuei64_v 11000 . . ..... ..... 111 ..... 0101111 @r_wdvm
+vamomaxuei64_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
# *** RV64F Standard Extension (in addition to RV32F) ***
fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 9e4fe72560b..2047f23bd62 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -279,15 +279,33 @@ vle32ff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
vle64ff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm
#*** Vector AMO operations are encoded under the standard AMO major opcode ***
-vamoswapw_v 00001 . . ..... ..... 110 ..... 0101111 @r_wdvm
-vamoaddw_v 00000 . . ..... ..... 110 ..... 0101111 @r_wdvm
-vamoxorw_v 00100 . . ..... ..... 110 ..... 0101111 @r_wdvm
-vamoandw_v 01100 . . ..... ..... 110 ..... 0101111 @r_wdvm
-vamoorw_v 01000 . . ..... ..... 110 ..... 0101111 @r_wdvm
-vamominw_v 10000 . . ..... ..... 110 ..... 0101111 @r_wdvm
-vamomaxw_v 10100 . . ..... ..... 110 ..... 0101111 @r_wdvm
-vamominuw_v 11000 . . ..... ..... 110 ..... 0101111 @r_wdvm
-vamomaxuw_v 11100 . . ..... ..... 110 ..... 0101111 @r_wdvm
+vamoswapei8_v 00001 . . ..... ..... 000 ..... 0101111 @r_wdvm
+vamoswapei16_v 00001 . . ..... ..... 101 ..... 0101111 @r_wdvm
+vamoswapei32_v 00001 . . ..... ..... 110 ..... 0101111 @r_wdvm
+vamoaddei8_v 00000 . . ..... ..... 000 ..... 0101111 @r_wdvm
+vamoaddei16_v 00000 . . ..... ..... 101 ..... 0101111 @r_wdvm
+vamoaddei32_v 00000 . . ..... ..... 110 ..... 0101111 @r_wdvm
+vamoxorei8_v 00100 . . ..... ..... 000 ..... 0101111 @r_wdvm
+vamoxorei16_v 00100 . . ..... ..... 101 ..... 0101111 @r_wdvm
+vamoxorei32_v 00100 . . ..... ..... 110 ..... 0101111 @r_wdvm
+vamoandei8_v 01100 . . ..... ..... 000 ..... 0101111 @r_wdvm
+vamoandei16_v 01100 . . ..... ..... 101 ..... 0101111 @r_wdvm
+vamoandei32_v 01100 . . ..... ..... 110 ..... 0101111 @r_wdvm
+vamoorei8_v 01000 . . ..... ..... 000 ..... 0101111 @r_wdvm
+vamoorei16_v 01000 . . ..... ..... 101 ..... 0101111 @r_wdvm
+vamoorei32_v 01000 . . ..... ..... 110 ..... 0101111 @r_wdvm
+vamominei8_v 10000 . . ..... ..... 000 ..... 0101111 @r_wdvm
+vamominei16_v 10000 . . ..... ..... 101 ..... 0101111 @r_wdvm
+vamominei32_v 10000 . . ..... ..... 110 ..... 0101111 @r_wdvm
+vamomaxei8_v 10100 . . ..... ..... 000 ..... 0101111 @r_wdvm
+vamomaxei16_v 10100 . . ..... ..... 101 ..... 0101111 @r_wdvm
+vamomaxei32_v 10100 . . ..... ..... 110 ..... 0101111 @r_wdvm
+vamominuei8_v 11000 . . ..... ..... 000 ..... 0101111 @r_wdvm
+vamominuei16_v 11000 . . ..... ..... 101 ..... 0101111 @r_wdvm
+vamominuei32_v 11000 . . ..... ..... 110 ..... 0101111 @r_wdvm
+vamomaxuei8_v 11100 . . ..... ..... 000 ..... 0101111 @r_wdvm
+vamomaxuei16_v 11100 . . ..... ..... 101 ..... 0101111 @r_wdvm
+vamomaxuei32_v 11100 . . ..... ..... 110 ..... 0101111 @r_wdvm
# *** new major opcode OP-V ***
vadd_vv 000000 . ..... ..... 000 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 20161b1ebe3..4c93f8a5c8e 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -290,6 +290,52 @@ static bool vext_check_ld_index(DisasContext *s, int vd, int vs2,
return ret;
}
+/*
+ * Vector AMO check function.
+ *
+ * Rules to be checked here:
+ * 1. RVA must supported.
+ * 2. AMO can either operations on 64-bit (RV64 only) or 32-bit words
+ * in memory:
+ * For RV32: 32 <= SEW <= 32, EEW <= 32.
+ * For RV64: 32 <= SEW <= 64, EEW <= 64.
+ * 3. Destination vector register number is multiples of LMUL.
+ * (Section 3.3.2, 8)
+ * 4. Address vector register number is multiples of EMUL.
+ * (Section 3.3.2, 8)
+ * 5. EMUL must within the range: 1/8 <= EMUL <= 8. (Section 7.3)
+ * 6. If wd = 1:
+ * 6.1. Destination vector register group for a masked vector
+ * instruction cannot overlap the source mask register (v0).
+ * (Section 5.3)
+ * 6.2. Destination vector register cannot overlap a source vector
+ * register (vs2) group.
+ * (Section 5.2)
+ */
+static bool vext_check_amo(DisasContext *s, int vd, int vs2,
+ int wd, int vm, uint8_t eew)
+{
+ int8_t emul = eew - s->sew + s->lmul;
+ bool ret = has_ext(s, RVA) &&
+ (1 << s->sew >= 4) &&
+ (1 << s->sew <= sizeof(target_ulong)) &&
+ (eew <= (sizeof(target_ulong) << 3)) &&
+ require_align(vd, s->lmul) &&
+ require_align(vs2, emul) &&
+ (emul >= -3 && emul <= 3);
+ if (wd) {
+ ret &= require_vm(vm, vd);
+ if (eew > s->sew) {
+ if (vd != vs2) {
+ ret &= require_noover(vd, s->lmul, vs2, emul);
+ }
+ } else if (eew < s->sew) {
+ ret &= require_noover(vd, s->lmul, vs2, emul);
+ }
+ }
+ return ret;
+}
+
static bool vext_check_ss(DisasContext *s, int vd, int vs, int vm)
{
return require_vm(vm, vd) &&
@@ -1007,104 +1053,129 @@ static bool amo_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
return true;
}
-static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
+static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t eew, uint8_t seq)
{
uint32_t data = 0;
gen_helper_amo *fn;
- static gen_helper_amo *const fnsw[9] = {
- /* no atomic operation */
- gen_helper_vamoswapw_v_w,
- gen_helper_vamoaddw_v_w,
- gen_helper_vamoxorw_v_w,
- gen_helper_vamoandw_v_w,
- gen_helper_vamoorw_v_w,
- gen_helper_vamominw_v_w,
- gen_helper_vamomaxw_v_w,
- gen_helper_vamominuw_v_w,
- gen_helper_vamomaxuw_v_w
- };
+ static gen_helper_amo *const fns[36][2] = {
+ { gen_helper_vamoswapei8_32_v, gen_helper_vamoswapei8_64_v },
+ { gen_helper_vamoswapei16_32_v, gen_helper_vamoswapei16_64_v },
+ { gen_helper_vamoswapei32_32_v, gen_helper_vamoswapei32_64_v },
+ { gen_helper_vamoaddei8_32_v, gen_helper_vamoaddei8_64_v },
+ { gen_helper_vamoaddei16_32_v, gen_helper_vamoaddei16_64_v },
+ { gen_helper_vamoaddei32_32_v, gen_helper_vamoaddei32_64_v },
+ { gen_helper_vamoxorei8_32_v, gen_helper_vamoxorei8_64_v },
+ { gen_helper_vamoxorei16_32_v, gen_helper_vamoxorei16_64_v },
+ { gen_helper_vamoxorei32_32_v, gen_helper_vamoxorei32_64_v },
+ { gen_helper_vamoandei8_32_v, gen_helper_vamoandei8_64_v },
+ { gen_helper_vamoandei16_32_v, gen_helper_vamoandei16_64_v },
+ { gen_helper_vamoandei32_32_v, gen_helper_vamoandei32_64_v },
+ { gen_helper_vamoorei8_32_v, gen_helper_vamoorei8_64_v },
+ { gen_helper_vamoorei16_32_v, gen_helper_vamoorei16_64_v },
+ { gen_helper_vamoorei32_32_v, gen_helper_vamoorei32_64_v },
+ { gen_helper_vamominei8_32_v, gen_helper_vamominei8_64_v },
+ { gen_helper_vamominei16_32_v, gen_helper_vamominei16_64_v },
+ { gen_helper_vamominei32_32_v, gen_helper_vamominei32_64_v },
+ { gen_helper_vamomaxei8_32_v, gen_helper_vamomaxei8_64_v },
+ { gen_helper_vamomaxei16_32_v, gen_helper_vamomaxei16_64_v },
+ { gen_helper_vamomaxei32_32_v, gen_helper_vamomaxei32_64_v },
+ { gen_helper_vamominuei8_32_v, gen_helper_vamominuei8_64_v },
+ { gen_helper_vamominuei16_32_v, gen_helper_vamominuei16_64_v },
+ { gen_helper_vamominuei32_32_v, gen_helper_vamominuei32_64_v },
+ { gen_helper_vamomaxuei8_32_v, gen_helper_vamomaxuei8_64_v },
+ { gen_helper_vamomaxuei16_32_v, gen_helper_vamomaxuei16_64_v },
+ { gen_helper_vamomaxuei32_32_v, gen_helper_vamomaxuei32_64_v },
#ifdef TARGET_RISCV64
- static gen_helper_amo *const fnsd[18] = {
- gen_helper_vamoswapw_v_d,
- gen_helper_vamoaddw_v_d,
- gen_helper_vamoxorw_v_d,
- gen_helper_vamoandw_v_d,
- gen_helper_vamoorw_v_d,
- gen_helper_vamominw_v_d,
- gen_helper_vamomaxw_v_d,
- gen_helper_vamominuw_v_d,
- gen_helper_vamomaxuw_v_d,
- gen_helper_vamoswapd_v_d,
- gen_helper_vamoaddd_v_d,
- gen_helper_vamoxord_v_d,
- gen_helper_vamoandd_v_d,
- gen_helper_vamoord_v_d,
- gen_helper_vamomind_v_d,
- gen_helper_vamomaxd_v_d,
- gen_helper_vamominud_v_d,
- gen_helper_vamomaxud_v_d
- };
+ { gen_helper_vamoswapei64_32_v, gen_helper_vamoswapei64_64_v },
+ { gen_helper_vamoaddei64_32_v, gen_helper_vamoaddei64_64_v },
+ { gen_helper_vamoxorei64_32_v, gen_helper_vamoxorei64_64_v },
+ { gen_helper_vamoandei64_32_v, gen_helper_vamoandei64_64_v },
+ { gen_helper_vamoorei64_32_v, gen_helper_vamoorei64_64_v },
+ { gen_helper_vamominei64_32_v, gen_helper_vamominei64_64_v },
+ { gen_helper_vamomaxei64_32_v, gen_helper_vamomaxei64_64_v },
+ { gen_helper_vamominuei64_32_v, gen_helper_vamominuei64_64_v },
+ { gen_helper_vamomaxuei64_32_v, gen_helper_vamomaxuei64_64_v }
+#else
+ { NULL, NULL }, { NULL, NULL }, { NULL, NULL }, { NULL, NULL },
+ { NULL, NULL }, { NULL, NULL }, { NULL, NULL }, { NULL, NULL },
+ { NULL, NULL }
#endif
+ };
if (tb_cflags(s->base.tb) & CF_PARALLEL) {
gen_helper_exit_atomic(cpu_env);
s->base.is_jmp = DISAS_NORETURN;
return true;
- } else {
- if (s->sew == 3) {
-#ifdef TARGET_RISCV64
- fn = fnsd[seq];
-#else
- /* Check done in amo_check(). */
- g_assert_not_reached();
-#endif
- } else {
- assert(seq < ARRAY_SIZE(fnsw));
- fn = fnsw[seq];
- }
+ }
+
+ fn = fns[seq][s->sew - 2];
+ if (fn == NULL) {
+ return false;
}
data = FIELD_DP32(data, VDATA, VM, a->vm);
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, WD, a->wd);
return amo_trans(a->rd, a->rs1, a->rs2, data, fn, s);
}
+
+static bool amo_check(DisasContext *s, arg_rwdvm* a, uint8_t eew)
+{
+ return require_rvv(s) &&
+ vext_check_isa_ill(s) &&
+ vext_check_amo(s, a->rd, a->rs2, a->wd, a->vm, eew);
+}
+
+#define GEN_VEXT_AMO_TRANS(NAME, EEW, SEQ, ARGTYPE, OP, CHECK) \
+static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE * a) \
+{ \
+ if (CHECK(s, a, EEW)) { \
+ return OP(s, a, EEW, SEQ); \
+ } \
+ return false; \
+}
+
+GEN_VEXT_AMO_TRANS(vamoswapei8_v, MO_8, 0, rwdvm, amo_op, amo_check)
+GEN_VEXT_AMO_TRANS(vamoswapei16_v, MO_16, 1, rwdvm, amo_op, amo_check)
+GEN_VEXT_AMO_TRANS(vamoswapei32_v, MO_32, 2, rwdvm, amo_op, amo_check)
+GEN_VEXT_AMO_TRANS(vamoaddei8_v, MO_8, 3, rwdvm, amo_op, amo_check)
+GEN_VEXT_AMO_TRANS(vamoaddei16_v, MO_16, 4, rwdvm, amo_op, amo_check)
+GEN_VEXT_AMO_TRANS(vamoaddei32_v, MO_32, 5, rwdvm, amo_op, amo_check)
+GEN_VEXT_AMO_TRANS(vamoxorei8_v, MO_8, 6, rwdvm, amo_op, amo_check)
+GEN_VEXT_AMO_TRANS(vamoxorei16_v, MO_16, 7, rwdvm, amo_op, amo_check)
+GEN_VEXT_AMO_TRANS(vamoxorei32_v, MO_32, 8, rwdvm, amo_op, amo_check)
+GEN_VEXT_AMO_TRANS(vamoandei8_v, MO_8, 9, rwdvm, amo_op, amo_check)
+GEN_VEXT_AMO_TRANS(vamoandei16_v, MO_16, 10, rwdvm, amo_op, amo_check)
+GEN_VEXT_AMO_TRANS(vamoandei32_v, MO_32, 11, rwdvm, amo_op, amo_check)
+GEN_VEXT_AMO_TRANS(vamoorei8_v, MO_8, 12, rwdvm, amo_op, amo_check)
+GEN_VEXT_AMO_TRANS(vamoorei16_v, MO_16, 13, rwdvm, amo_op, amo_check)
+GEN_VEXT_AMO_TRANS(vamoorei32_v, MO_32, 14, rwdvm, amo_op, amo_check)
+GEN_VEXT_AMO_TRANS(vamominei8_v, MO_8, 15, rwdvm, amo_op, amo_check)
+GEN_VEXT_AMO_TRANS(vamominei16_v, MO_16, 16, rwdvm, amo_op, amo_check)
+GEN_VEXT_AMO_TRANS(vamominei32_v, MO_32, 17, rwdvm, amo_op, amo_check)
+GEN_VEXT_AMO_TRANS(vamomaxei8_v, MO_8, 18, rwdvm, amo_op, amo_check)
+GEN_VEXT_AMO_TRANS(vamomaxei16_v, MO_16, 19, rwdvm, amo_op, amo_check)
+GEN_VEXT_AMO_TRANS(vamomaxei32_v, MO_32, 20, rwdvm, amo_op, amo_check)
+GEN_VEXT_AMO_TRANS(vamominuei8_v, MO_8, 21, rwdvm, amo_op, amo_check)
+GEN_VEXT_AMO_TRANS(vamominuei16_v, MO_16, 22, rwdvm, amo_op, amo_check)
+GEN_VEXT_AMO_TRANS(vamominuei32_v, MO_32, 23, rwdvm, amo_op, amo_check)
+GEN_VEXT_AMO_TRANS(vamomaxuei8_v, MO_8, 24, rwdvm, amo_op, amo_check)
+GEN_VEXT_AMO_TRANS(vamomaxuei16_v, MO_16, 25, rwdvm, amo_op, amo_check)
+GEN_VEXT_AMO_TRANS(vamomaxuei32_v, MO_32, 26, rwdvm, amo_op, amo_check)
+
/*
- * There are two rules check here.
- *
- * 1. SEW must be at least as wide as the AMO memory element size.
- *
- * 2. If SEW is greater than XLEN, an illegal instruction exception is raised.
+ * Index EEW cannot be greater than XLEN,
+ * else an illegal instruction is raised (Section 8)
*/
-static bool amo_check(DisasContext *s, arg_rwdvm* a)
-{
- return (!s->vill && has_ext(s, RVA) &&
- (!a->wd || vext_check_overlap_mask(s, a->rd, a->vm, false)) &&
- vext_check_reg(s, a->rd, false) &&
- vext_check_reg(s, a->rs2, false) &&
- ((1 << s->sew) <= sizeof(target_ulong)) &&
- ((1 << s->sew) >= 4));
-}
-
-GEN_VEXT_TRANS(vamoswapw_v, 0, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoaddw_v, 1, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoxorw_v, 2, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoandw_v, 3, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoorw_v, 4, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamominw_v, 5, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamomaxw_v, 6, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamominuw_v, 7, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamomaxuw_v, 8, rwdvm, amo_op, amo_check)
#ifdef TARGET_RISCV64
-GEN_VEXT_TRANS(vamoswapd_v, 9, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoaddd_v, 10, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoxord_v, 11, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoandd_v, 12, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamoord_v, 13, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamomind_v, 14, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamomaxd_v, 15, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamominud_v, 16, rwdvm, amo_op, amo_check)
-GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check)
+GEN_VEXT_AMO_TRANS(vamoswapei64_v, MO_64, 27, rwdvm, amo_op, amo_check)
+GEN_VEXT_AMO_TRANS(vamoaddei64_v, MO_64, 28, rwdvm, amo_op, amo_check)
+GEN_VEXT_AMO_TRANS(vamoxorei64_v, MO_64, 29, rwdvm, amo_op, amo_check)
+GEN_VEXT_AMO_TRANS(vamoandei64_v, MO_64, 30, rwdvm, amo_op, amo_check)
+GEN_VEXT_AMO_TRANS(vamoorei64_v, MO_64, 31, rwdvm, amo_op, amo_check)
+GEN_VEXT_AMO_TRANS(vamominei64_v, MO_64, 32, rwdvm, amo_op, amo_check)
+GEN_VEXT_AMO_TRANS(vamomaxei64_v, MO_64, 33, rwdvm, amo_op, amo_check)
+GEN_VEXT_AMO_TRANS(vamominuei64_v, MO_64, 34, rwdvm, amo_op, amo_check)
+GEN_VEXT_AMO_TRANS(vamomaxuei64_v, MO_64, 35, rwdvm, amo_op, amo_check)
#endif
/*
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index fd398af8550..743883449a4 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -541,23 +541,22 @@ typedef void vext_amo_noatomic_fn(void *vs3, target_ulong addr,
uint32_t wd, uint32_t idx, CPURISCVState *env,
uintptr_t retaddr);
-/* no atomic opreation for vector atomic insructions */
+/* no atomic operation for vector atomic instructions */
#define DO_SWAP(N, M) (M)
#define DO_AND(N, M) (N & M)
#define DO_XOR(N, M) (N ^ M)
#define DO_OR(N, M) (N | M)
#define DO_ADD(N, M) (N + M)
+#define DO_MAX(N, M) ((N) >= (M) ? (N) : (M))
+#define DO_MIN(N, M) ((N) >= (M) ? (M) : (N))
-#define GEN_VEXT_AMO_NOATOMIC_OP(NAME, ESZ, MSZ, H, DO_OP, SUF) \
+#define GEN_VEXT_AMO_NOATOMIC_OP(NAME, MTYPE, H, DO_OP, SUF) \
static void \
vext_##NAME##_noatomic_op(void *vs3, target_ulong addr, \
uint32_t wd, uint32_t idx, \
CPURISCVState *env, uintptr_t retaddr)\
{ \
- typedef int##ESZ##_t ETYPE; \
- typedef int##MSZ##_t MTYPE; \
- typedef uint##MSZ##_t UMTYPE __attribute__((unused)); \
- ETYPE *pe3 = (ETYPE *)vs3 + H(idx); \
+ MTYPE *pe3 = (MTYPE *)vs3 + H(idx); \
MTYPE a = cpu_ld##SUF##_data(env, addr), b = *pe3; \
\
cpu_st##SUF##_data(env, addr, DO_OP(a, b)); \
@@ -566,42 +565,79 @@ vext_##NAME##_noatomic_op(void *vs3, target_ulong addr, \
} \
}
-/* Signed min/max */
-#define DO_MAX(N, M) ((N) >= (M) ? (N) : (M))
-#define DO_MIN(N, M) ((N) >= (M) ? (M) : (N))
-
-/* Unsigned min/max */
-#define DO_MAXU(N, M) DO_MAX((UMTYPE)N, (UMTYPE)M)
-#define DO_MINU(N, M) DO_MIN((UMTYPE)N, (UMTYPE)M)
-
-GEN_VEXT_AMO_NOATOMIC_OP(vamoswapw_v_w, 32, 32, H4, DO_SWAP, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamoaddw_v_w, 32, 32, H4, DO_ADD, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamoxorw_v_w, 32, 32, H4, DO_XOR, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamoandw_v_w, 32, 32, H4, DO_AND, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamoorw_v_w, 32, 32, H4, DO_OR, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamominw_v_w, 32, 32, H4, DO_MIN, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamomaxw_v_w, 32, 32, H4, DO_MAX, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_w, 32, 32, H4, DO_MINU, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_w, 32, 32, H4, DO_MAXU, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoswapei8_32_v, uint32_t, H4, DO_SWAP, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoswapei8_64_v, uint64_t, H8, DO_SWAP, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoswapei16_32_v, uint32_t, H4, DO_SWAP, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoswapei16_64_v, uint64_t, H8, DO_SWAP, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoswapei32_32_v, uint32_t, H4, DO_SWAP, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoswapei32_64_v, uint64_t, H8, DO_SWAP, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoaddei8_32_v, uint32_t, H4, DO_ADD, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoaddei8_64_v, uint64_t, H8, DO_ADD, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoaddei16_32_v, uint32_t, H4, DO_ADD, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoaddei16_64_v, uint64_t, H8, DO_ADD, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoaddei32_32_v, uint32_t, H4, DO_ADD, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoaddei32_64_v, uint64_t, H8, DO_ADD, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoxorei8_32_v, uint32_t, H4, DO_XOR, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoxorei8_64_v, uint64_t, H8, DO_XOR, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoxorei16_32_v, uint32_t, H4, DO_XOR, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoxorei16_64_v, uint64_t, H8, DO_XOR, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoxorei32_32_v, uint32_t, H4, DO_XOR, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoxorei32_64_v, uint64_t, H8, DO_XOR, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoandei8_32_v, uint32_t, H4, DO_AND, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoandei8_64_v, uint64_t, H8, DO_AND, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoandei16_32_v, uint32_t, H4, DO_AND, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoandei16_64_v, uint64_t, H8, DO_AND, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoandei32_32_v, uint32_t, H4, DO_AND, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoandei32_64_v, uint64_t, H8, DO_AND, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoorei8_32_v, uint32_t, H4, DO_OR, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoorei8_64_v, uint64_t, H8, DO_OR, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoorei16_32_v, uint32_t, H4, DO_OR, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoorei16_64_v, uint64_t, H8, DO_OR, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoorei32_32_v, uint32_t, H4, DO_OR, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoorei32_64_v, uint64_t, H8, DO_OR, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominei8_32_v, int32_t, H4, DO_MIN, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominei8_64_v, int64_t, H8, DO_MIN, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominei16_32_v, int32_t, H4, DO_MIN, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominei16_64_v, int64_t, H8, DO_MIN, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominei32_32_v, int32_t, H4, DO_MIN, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominei32_64_v, int64_t, H8, DO_MIN, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxei8_32_v, int32_t, H4, DO_MAX, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxei8_64_v, int64_t, H8, DO_MAX, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxei16_32_v, int32_t, H4, DO_MAX, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxei16_64_v, int64_t, H8, DO_MAX, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxei32_32_v, int32_t, H4, DO_MAX, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxei32_64_v, int64_t, H8, DO_MAX, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominuei8_32_v, uint32_t, H4, DO_MIN, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominuei8_64_v, uint64_t, H8, DO_MIN, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominuei16_32_v, uint32_t, H4, DO_MIN, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominuei16_64_v, uint64_t, H8, DO_MIN, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominuei32_32_v, uint32_t, H4, DO_MIN, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominuei32_64_v, uint64_t, H8, DO_MIN, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuei8_32_v, uint32_t, H4, DO_MAX, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuei8_64_v, uint64_t, H8, DO_MAX, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuei16_32_v, uint32_t, H4, DO_MAX, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuei16_64_v, uint64_t, H8, DO_MAX, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuei32_32_v, uint32_t, H4, DO_MAX, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuei32_64_v, uint64_t, H8, DO_MAX, q)
#ifdef TARGET_RISCV64
-GEN_VEXT_AMO_NOATOMIC_OP(vamoswapw_v_d, 64, 32, H8, DO_SWAP, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamoswapd_v_d, 64, 64, H8, DO_SWAP, q)
-GEN_VEXT_AMO_NOATOMIC_OP(vamoaddw_v_d, 64, 32, H8, DO_ADD, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamoaddd_v_d, 64, 64, H8, DO_ADD, q)
-GEN_VEXT_AMO_NOATOMIC_OP(vamoxorw_v_d, 64, 32, H8, DO_XOR, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamoxord_v_d, 64, 64, H8, DO_XOR, q)
-GEN_VEXT_AMO_NOATOMIC_OP(vamoandw_v_d, 64, 32, H8, DO_AND, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamoandd_v_d, 64, 64, H8, DO_AND, q)
-GEN_VEXT_AMO_NOATOMIC_OP(vamoorw_v_d, 64, 32, H8, DO_OR, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamoord_v_d, 64, 64, H8, DO_OR, q)
-GEN_VEXT_AMO_NOATOMIC_OP(vamominw_v_d, 64, 32, H8, DO_MIN, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamomind_v_d, 64, 64, H8, DO_MIN, q)
-GEN_VEXT_AMO_NOATOMIC_OP(vamomaxw_v_d, 64, 32, H8, DO_MAX, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamomaxd_v_d, 64, 64, H8, DO_MAX, q)
-GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_d, 64, 32, H8, DO_MINU, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamominud_v_d, 64, 64, H8, DO_MINU, q)
-GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_d, 64, 32, H8, DO_MAXU, l)
-GEN_VEXT_AMO_NOATOMIC_OP(vamomaxud_v_d, 64, 64, H8, DO_MAXU, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoswapei64_32_v, uint32_t, H4, DO_SWAP, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoswapei64_64_v, uint64_t, H8, DO_SWAP, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoaddei64_32_v, uint32_t, H4, DO_ADD, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoaddei64_64_v, uint64_t, H8, DO_ADD, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoxorei64_32_v, uint32_t, H4, DO_XOR, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoxorei64_64_v, uint64_t, H8, DO_XOR, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoandei64_32_v, uint32_t, H4, DO_AND, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoandei64_64_v, uint64_t, H8, DO_AND, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoorei64_32_v, uint32_t, H4, DO_OR, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamoorei64_64_v, uint64_t, H8, DO_OR, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominei64_32_v, int32_t, H4, DO_MIN, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominei64_64_v, int64_t, H8, DO_MIN, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxei64_32_v, int32_t, H4, DO_MAX, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxei64_64_v, int64_t, H8, DO_MAX, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominuei64_32_v, uint32_t, H4, DO_MIN, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamominuei64_64_v, uint64_t, H8, DO_MIN, q)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuei64_32_v, uint32_t, H4, DO_MAX, l)
+GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuei64_64_v, uint64_t, H8, DO_MAX, q)
#endif
static inline void
@@ -609,7 +645,7 @@ vext_amo_noatomic(void *vs3, void *v0, target_ulong base,
void *vs2, CPURISCVState *env, uint32_t desc,
vext_get_index_addr get_index_addr,
vext_amo_noatomic_fn *noatomic_op,
- uint32_t esz, uint32_t msz, uintptr_t ra)
+ uint32_t esz, uintptr_t ra)
{
uint32_t i;
target_long addr;
@@ -620,8 +656,8 @@ vext_amo_noatomic(void *vs3, void *v0, target_ulong base,
if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
- probe_pages(env, get_index_addr(base, i, vs2), msz, ra, MMU_DATA_LOAD);
- probe_pages(env, get_index_addr(base, i, vs2), msz, ra, MMU_DATA_STORE);
+ probe_pages(env, get_index_addr(base, i, vs2), esz, ra, MMU_DATA_LOAD);
+ probe_pages(env, get_index_addr(base, i, vs2), esz, ra, MMU_DATA_STORE);
}
for (i = 0; i < env->vl; i++) {
if (!vm && !vext_elem_mask(v0, i)) {
@@ -632,45 +668,89 @@ vext_amo_noatomic(void *vs3, void *v0, target_ulong base,
}
}
-#define GEN_VEXT_AMO(NAME, MTYPE, ETYPE, INDEX_FN) \
+#define GEN_VEXT_AMO(NAME, ETYPE, INDEX_FN) \
void HELPER(NAME)(void *vs3, void *v0, target_ulong base, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
vext_amo_noatomic(vs3, v0, base, vs2, env, desc, \
INDEX_FN, vext_##NAME##_noatomic_op, \
- sizeof(ETYPE), sizeof(MTYPE), \
- GETPC()); \
-}
-
+ sizeof(ETYPE), GETPC()); \
+}
+
+GEN_VEXT_AMO(vamoswapei8_32_v, int32_t, idx_b)
+GEN_VEXT_AMO(vamoswapei8_64_v, int64_t, idx_b)
+GEN_VEXT_AMO(vamoswapei16_32_v, int32_t, idx_h)
+GEN_VEXT_AMO(vamoswapei16_64_v, int64_t, idx_h)
+GEN_VEXT_AMO(vamoswapei32_32_v, int32_t, idx_w)
+GEN_VEXT_AMO(vamoswapei32_64_v, int64_t, idx_w)
+GEN_VEXT_AMO(vamoaddei8_32_v, int32_t, idx_b)
+GEN_VEXT_AMO(vamoaddei8_64_v, int64_t, idx_b)
+GEN_VEXT_AMO(vamoaddei16_32_v, int32_t, idx_h)
+GEN_VEXT_AMO(vamoaddei16_64_v, int64_t, idx_h)
+GEN_VEXT_AMO(vamoaddei32_32_v, int32_t, idx_w)
+GEN_VEXT_AMO(vamoaddei32_64_v, int64_t, idx_w)
+GEN_VEXT_AMO(vamoxorei8_32_v, int32_t, idx_b)
+GEN_VEXT_AMO(vamoxorei8_64_v, int64_t, idx_b)
+GEN_VEXT_AMO(vamoxorei16_32_v, int32_t, idx_h)
+GEN_VEXT_AMO(vamoxorei16_64_v, int64_t, idx_h)
+GEN_VEXT_AMO(vamoxorei32_32_v, int32_t, idx_w)
+GEN_VEXT_AMO(vamoxorei32_64_v, int64_t, idx_w)
+GEN_VEXT_AMO(vamoandei8_32_v, int32_t, idx_b)
+GEN_VEXT_AMO(vamoandei8_64_v, int64_t, idx_b)
+GEN_VEXT_AMO(vamoandei16_32_v, int32_t, idx_h)
+GEN_VEXT_AMO(vamoandei16_64_v, int64_t, idx_h)
+GEN_VEXT_AMO(vamoandei32_32_v, int32_t, idx_w)
+GEN_VEXT_AMO(vamoandei32_64_v, int64_t, idx_w)
+GEN_VEXT_AMO(vamoorei8_32_v, int32_t, idx_b)
+GEN_VEXT_AMO(vamoorei8_64_v, int64_t, idx_b)
+GEN_VEXT_AMO(vamoorei16_32_v, int32_t, idx_h)
+GEN_VEXT_AMO(vamoorei16_64_v, int64_t, idx_h)
+GEN_VEXT_AMO(vamoorei32_32_v, int32_t, idx_w)
+GEN_VEXT_AMO(vamoorei32_64_v, int64_t, idx_w)
+GEN_VEXT_AMO(vamominei8_32_v, int32_t, idx_b)
+GEN_VEXT_AMO(vamominei8_64_v, int64_t, idx_b)
+GEN_VEXT_AMO(vamominei16_32_v, int32_t, idx_h)
+GEN_VEXT_AMO(vamominei16_64_v, int64_t, idx_h)
+GEN_VEXT_AMO(vamominei32_32_v, int32_t, idx_w)
+GEN_VEXT_AMO(vamominei32_64_v, int64_t, idx_w)
+GEN_VEXT_AMO(vamomaxei8_32_v, int32_t, idx_b)
+GEN_VEXT_AMO(vamomaxei8_64_v, int64_t, idx_b)
+GEN_VEXT_AMO(vamomaxei16_32_v, int32_t, idx_h)
+GEN_VEXT_AMO(vamomaxei16_64_v, int64_t, idx_h)
+GEN_VEXT_AMO(vamomaxei32_32_v, int32_t, idx_w)
+GEN_VEXT_AMO(vamomaxei32_64_v, int64_t, idx_w)
+GEN_VEXT_AMO(vamominuei8_32_v, int32_t, idx_b)
+GEN_VEXT_AMO(vamominuei8_64_v, int64_t, idx_b)
+GEN_VEXT_AMO(vamominuei16_32_v, int32_t, idx_h)
+GEN_VEXT_AMO(vamominuei16_64_v, int64_t, idx_h)
+GEN_VEXT_AMO(vamominuei32_32_v, int32_t, idx_w)
+GEN_VEXT_AMO(vamominuei32_64_v, int64_t, idx_w)
+GEN_VEXT_AMO(vamomaxuei8_32_v, int32_t, idx_b)
+GEN_VEXT_AMO(vamomaxuei8_64_v, int64_t, idx_b)
+GEN_VEXT_AMO(vamomaxuei16_32_v, int32_t, idx_h)
+GEN_VEXT_AMO(vamomaxuei16_64_v, int64_t, idx_h)
+GEN_VEXT_AMO(vamomaxuei32_32_v, int32_t, idx_w)
+GEN_VEXT_AMO(vamomaxuei32_64_v, int64_t, idx_w)
#ifdef TARGET_RISCV64
-GEN_VEXT_AMO(vamoswapw_v_d, int32_t, int64_t, idx_d)
-GEN_VEXT_AMO(vamoswapd_v_d, int64_t, int64_t, idx_d)
-GEN_VEXT_AMO(vamoaddw_v_d, int32_t, int64_t, idx_d)
-GEN_VEXT_AMO(vamoaddd_v_d, int64_t, int64_t, idx_d)
-GEN_VEXT_AMO(vamoxorw_v_d, int32_t, int64_t, idx_d)
-GEN_VEXT_AMO(vamoxord_v_d, int64_t, int64_t, idx_d)
-GEN_VEXT_AMO(vamoandw_v_d, int32_t, int64_t, idx_d)
-GEN_VEXT_AMO(vamoandd_v_d, int64_t, int64_t, idx_d)
-GEN_VEXT_AMO(vamoorw_v_d, int32_t, int64_t, idx_d)
-GEN_VEXT_AMO(vamoord_v_d, int64_t, int64_t, idx_d)
-GEN_VEXT_AMO(vamominw_v_d, int32_t, int64_t, idx_d)
-GEN_VEXT_AMO(vamomind_v_d, int64_t, int64_t, idx_d)
-GEN_VEXT_AMO(vamomaxw_v_d, int32_t, int64_t, idx_d)
-GEN_VEXT_AMO(vamomaxd_v_d, int64_t, int64_t, idx_d)
-GEN_VEXT_AMO(vamominuw_v_d, uint32_t, uint64_t, idx_d)
-GEN_VEXT_AMO(vamominud_v_d, uint64_t, uint64_t, idx_d)
-GEN_VEXT_AMO(vamomaxuw_v_d, uint32_t, uint64_t, idx_d)
-GEN_VEXT_AMO(vamomaxud_v_d, uint64_t, uint64_t, idx_d)
+GEN_VEXT_AMO(vamoswapei64_32_v, int32_t, idx_d)
+GEN_VEXT_AMO(vamoswapei64_64_v, int64_t, idx_d)
+GEN_VEXT_AMO(vamoaddei64_32_v, int32_t, idx_d)
+GEN_VEXT_AMO(vamoaddei64_64_v, int64_t, idx_d)
+GEN_VEXT_AMO(vamoxorei64_32_v, int32_t, idx_d)
+GEN_VEXT_AMO(vamoxorei64_64_v, int64_t, idx_d)
+GEN_VEXT_AMO(vamoandei64_32_v, int32_t, idx_d)
+GEN_VEXT_AMO(vamoandei64_64_v, int64_t, idx_d)
+GEN_VEXT_AMO(vamoorei64_32_v, int32_t, idx_d)
+GEN_VEXT_AMO(vamoorei64_64_v, int64_t, idx_d)
+GEN_VEXT_AMO(vamominei64_32_v, int32_t, idx_d)
+GEN_VEXT_AMO(vamominei64_64_v, int64_t, idx_d)
+GEN_VEXT_AMO(vamomaxei64_32_v, int32_t, idx_d)
+GEN_VEXT_AMO(vamomaxei64_64_v, int64_t, idx_d)
+GEN_VEXT_AMO(vamominuei64_32_v, int32_t, idx_d)
+GEN_VEXT_AMO(vamominuei64_64_v, int64_t, idx_d)
+GEN_VEXT_AMO(vamomaxuei64_32_v, int32_t, idx_d)
+GEN_VEXT_AMO(vamomaxuei64_64_v, int64_t, idx_d)
#endif
-GEN_VEXT_AMO(vamoswapw_v_w, int32_t, int32_t, idx_w)
-GEN_VEXT_AMO(vamoaddw_v_w, int32_t, int32_t, idx_w)
-GEN_VEXT_AMO(vamoxorw_v_w, int32_t, int32_t, idx_w)
-GEN_VEXT_AMO(vamoandw_v_w, int32_t, int32_t, idx_w)
-GEN_VEXT_AMO(vamoorw_v_w, int32_t, int32_t, idx_w)
-GEN_VEXT_AMO(vamominw_v_w, int32_t, int32_t, idx_w)
-GEN_VEXT_AMO(vamomaxw_v_w, int32_t, int32_t, idx_w)
-GEN_VEXT_AMO(vamominuw_v_w, uint32_t, uint32_t, idx_w)
-GEN_VEXT_AMO(vamomaxuw_v_w, uint32_t, uint32_t, idx_w)
/*
*** Vector Integer Arithmetic Instructions
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 23/75] target/riscv: rvv-1.0: load/store whole register instructions
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (21 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 22/75] target/riscv: rvv-1.0: amo operations frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 24/75] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns frank.chang
` (51 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Add the following instructions:
* vl<nf>re<eew>.v
* vs<nf>r.v
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/helper.h | 21 ++++++++
target/riscv/insn32.decode | 22 ++++++++
target/riscv/insn_trans/trans_rvv.c.inc | 69 +++++++++++++++++++++++++
target/riscv/vector_helper.c | 65 +++++++++++++++++++++++
4 files changed, 177 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index b3fa28d4354..5ec364caecc 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -140,6 +140,27 @@ DEF_HELPER_5(vle16ff_v, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vle32ff_v, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vle64ff_v, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_4(vl1re8_v, void, ptr, tl, env, i32)
+DEF_HELPER_4(vl1re16_v, void, ptr, tl, env, i32)
+DEF_HELPER_4(vl1re32_v, void, ptr, tl, env, i32)
+DEF_HELPER_4(vl1re64_v, void, ptr, tl, env, i32)
+DEF_HELPER_4(vl2re8_v, void, ptr, tl, env, i32)
+DEF_HELPER_4(vl2re16_v, void, ptr, tl, env, i32)
+DEF_HELPER_4(vl2re32_v, void, ptr, tl, env, i32)
+DEF_HELPER_4(vl2re64_v, void, ptr, tl, env, i32)
+DEF_HELPER_4(vl4re8_v, void, ptr, tl, env, i32)
+DEF_HELPER_4(vl4re16_v, void, ptr, tl, env, i32)
+DEF_HELPER_4(vl4re32_v, void, ptr, tl, env, i32)
+DEF_HELPER_4(vl4re64_v, void, ptr, tl, env, i32)
+DEF_HELPER_4(vl8re8_v, void, ptr, tl, env, i32)
+DEF_HELPER_4(vl8re16_v, void, ptr, tl, env, i32)
+DEF_HELPER_4(vl8re32_v, void, ptr, tl, env, i32)
+DEF_HELPER_4(vl8re64_v, void, ptr, tl, env, i32)
+DEF_HELPER_4(vs1r_v, void, ptr, tl, env, i32)
+DEF_HELPER_4(vs2r_v, void, ptr, tl, env, i32)
+DEF_HELPER_4(vs4r_v, void, ptr, tl, env, i32)
+DEF_HELPER_4(vs8r_v, void, ptr, tl, env, i32)
+
DEF_HELPER_6(vamoswapei8_32_v, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vamoswapei8_64_v, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vamoswapei16_32_v, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 2047f23bd62..e11666f16df 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -278,6 +278,28 @@ vle16ff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm
vle32ff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
vle64ff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm
+# Vector whole register insns
+vl1re8_v 000 000 1 01000 ..... 000 ..... 0000111 @r2
+vl1re16_v 000 000 1 01000 ..... 101 ..... 0000111 @r2
+vl1re32_v 000 000 1 01000 ..... 110 ..... 0000111 @r2
+vl1re64_v 000 000 1 01000 ..... 111 ..... 0000111 @r2
+vl2re8_v 001 000 1 01000 ..... 000 ..... 0000111 @r2
+vl2re16_v 001 000 1 01000 ..... 101 ..... 0000111 @r2
+vl2re32_v 001 000 1 01000 ..... 110 ..... 0000111 @r2
+vl2re64_v 001 000 1 01000 ..... 111 ..... 0000111 @r2
+vl4re8_v 011 000 1 01000 ..... 000 ..... 0000111 @r2
+vl4re16_v 011 000 1 01000 ..... 101 ..... 0000111 @r2
+vl4re32_v 011 000 1 01000 ..... 110 ..... 0000111 @r2
+vl4re64_v 011 000 1 01000 ..... 111 ..... 0000111 @r2
+vl8re8_v 111 000 1 01000 ..... 000 ..... 0000111 @r2
+vl8re16_v 111 000 1 01000 ..... 101 ..... 0000111 @r2
+vl8re32_v 111 000 1 01000 ..... 110 ..... 0000111 @r2
+vl8re64_v 111 000 1 01000 ..... 111 ..... 0000111 @r2
+vs1r_v 000 000 1 01000 ..... 000 ..... 0100111 @r2
+vs2r_v 001 000 1 01000 ..... 000 ..... 0100111 @r2
+vs4r_v 011 000 1 01000 ..... 000 ..... 0100111 @r2
+vs8r_v 111 000 1 01000 ..... 000 ..... 0100111 @r2
+
#*** Vector AMO operations are encoded under the standard AMO major opcode ***
vamoswapei8_v 00001 . . ..... ..... 000 ..... 0101111 @r_wdvm
vamoswapei16_v 00001 . . ..... ..... 101 ..... 0101111 @r_wdvm
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 4c93f8a5c8e..2b0e0590efc 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1014,6 +1014,75 @@ GEN_VEXT_TRANS(vle16ff_v, MO_16, r2nfvm, ldff_op, ld_us_check)
GEN_VEXT_TRANS(vle32ff_v, MO_32, r2nfvm, ldff_op, ld_us_check)
GEN_VEXT_TRANS(vle64ff_v, MO_64, r2nfvm, ldff_op, ld_us_check)
+/*
+ * load and store whole register instructions
+ */
+typedef void gen_helper_ldst_whole(TCGv_ptr, TCGv, TCGv_env, TCGv_i32);
+
+static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
+ gen_helper_ldst_whole *fn, DisasContext *s,
+ bool is_store)
+{
+ TCGv_ptr dest;
+ TCGv base;
+ TCGv_i32 desc;
+
+ uint32_t data = FIELD_DP32(0, VDATA, NF, nf);
+ dest = tcg_temp_new_ptr();
+ base = tcg_temp_new();
+ desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+
+ gen_get_gpr(base, rs1);
+ tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
+
+ fn(dest, base, cpu_env, desc);
+
+ tcg_temp_free_ptr(dest);
+ tcg_temp_free(base);
+ tcg_temp_free_i32(desc);
+ if (!is_store) {
+ mark_vs_dirty(s);
+ }
+ return true;
+}
+
+/*
+ * load and store whole register instructions ignore vtype and vl setting.
+ * Thus, we don't need to check vill bit. (Section 7.9)
+ */
+#define GEN_LDST_WHOLE_TRANS(NAME, ARG_NF, IS_STORE) \
+static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
+{ \
+ if (require_rvv(s) && \
+ QEMU_IS_ALIGNED(a->rd, ARG_NF)) { \
+ return ldst_whole_trans(a->rd, a->rs1, ARG_NF, gen_helper_##NAME, \
+ s, IS_STORE); \
+ } \
+ return false; \
+}
+
+GEN_LDST_WHOLE_TRANS(vl1re8_v, 1, false)
+GEN_LDST_WHOLE_TRANS(vl1re16_v, 1, false)
+GEN_LDST_WHOLE_TRANS(vl1re32_v, 1, false)
+GEN_LDST_WHOLE_TRANS(vl1re64_v, 1, false)
+GEN_LDST_WHOLE_TRANS(vl2re8_v, 2, false)
+GEN_LDST_WHOLE_TRANS(vl2re16_v, 2, false)
+GEN_LDST_WHOLE_TRANS(vl2re32_v, 2, false)
+GEN_LDST_WHOLE_TRANS(vl2re64_v, 2, false)
+GEN_LDST_WHOLE_TRANS(vl4re8_v, 4, false)
+GEN_LDST_WHOLE_TRANS(vl4re16_v, 4, false)
+GEN_LDST_WHOLE_TRANS(vl4re32_v, 4, false)
+GEN_LDST_WHOLE_TRANS(vl4re64_v, 4, false)
+GEN_LDST_WHOLE_TRANS(vl8re8_v, 8, false)
+GEN_LDST_WHOLE_TRANS(vl8re16_v, 8, false)
+GEN_LDST_WHOLE_TRANS(vl8re32_v, 8, false)
+GEN_LDST_WHOLE_TRANS(vl8re64_v, 8, false)
+
+GEN_LDST_WHOLE_TRANS(vs1r_v, 1, true)
+GEN_LDST_WHOLE_TRANS(vs2r_v, 2, true)
+GEN_LDST_WHOLE_TRANS(vs4r_v, 4, true)
+GEN_LDST_WHOLE_TRANS(vs8r_v, 8, true)
+
/*
*** vector atomic operation
*/
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 743883449a4..57564c5c0c9 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -534,6 +534,71 @@ GEN_VEXT_LDFF(vle16ff_v, int16_t, lde_h)
GEN_VEXT_LDFF(vle32ff_v, int32_t, lde_w)
GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d)
+/*
+ *** load and store whole register instructions
+ */
+static void
+vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
+ vext_ldst_elem_fn *ldst_elem, uint32_t esz, uintptr_t ra,
+ MMUAccessType access_type)
+{
+ uint32_t i, k;
+ uint32_t nf = vext_nf(desc);
+ uint32_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
+ uint32_t max_elems = vlenb >> esz;
+
+ /* probe every access */
+ probe_pages(env, base, vlenb * nf, ra, access_type);
+
+ /* load bytes from guest memory */
+ for (k = 0; k < nf; k++) {
+ for (i = 0; i < max_elems; i++) {
+ target_ulong addr = base + ((i + k * max_elems) << esz);
+ ldst_elem(env, addr, i + k * max_elems, vd, ra);
+ }
+ }
+}
+
+#define GEN_VEXT_LD_WHOLE(NAME, ETYPE, LOAD_FN) \
+void HELPER(NAME)(void *vd, target_ulong base, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ vext_ldst_whole(vd, base, env, desc, LOAD_FN, \
+ ctzl(sizeof(ETYPE)), GETPC(), \
+ MMU_DATA_LOAD); \
+}
+
+GEN_VEXT_LD_WHOLE(vl1re8_v, int8_t, lde_b)
+GEN_VEXT_LD_WHOLE(vl1re16_v, int16_t, lde_h)
+GEN_VEXT_LD_WHOLE(vl1re32_v, int32_t, lde_w)
+GEN_VEXT_LD_WHOLE(vl1re64_v, int64_t, lde_d)
+GEN_VEXT_LD_WHOLE(vl2re8_v, int8_t, lde_b)
+GEN_VEXT_LD_WHOLE(vl2re16_v, int16_t, lde_h)
+GEN_VEXT_LD_WHOLE(vl2re32_v, int32_t, lde_w)
+GEN_VEXT_LD_WHOLE(vl2re64_v, int64_t, lde_d)
+GEN_VEXT_LD_WHOLE(vl4re8_v, int8_t, lde_b)
+GEN_VEXT_LD_WHOLE(vl4re16_v, int16_t, lde_h)
+GEN_VEXT_LD_WHOLE(vl4re32_v, int32_t, lde_w)
+GEN_VEXT_LD_WHOLE(vl4re64_v, int64_t, lde_d)
+GEN_VEXT_LD_WHOLE(vl8re8_v, int8_t, lde_b)
+GEN_VEXT_LD_WHOLE(vl8re16_v, int16_t, lde_h)
+GEN_VEXT_LD_WHOLE(vl8re32_v, int32_t, lde_w)
+GEN_VEXT_LD_WHOLE(vl8re64_v, int64_t, lde_d)
+
+#define GEN_VEXT_ST_WHOLE(NAME, ETYPE, STORE_FN) \
+void HELPER(NAME)(void *vd, target_ulong base, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ vext_ldst_whole(vd, base, env, desc, STORE_FN, \
+ ctzl(sizeof(ETYPE)), GETPC(), \
+ MMU_DATA_STORE); \
+}
+
+GEN_VEXT_ST_WHOLE(vs1r_v, int8_t, ste_b)
+GEN_VEXT_ST_WHOLE(vs2r_v, int8_t, ste_b)
+GEN_VEXT_ST_WHOLE(vs4r_v, int8_t, ste_b)
+GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b)
+
/*
*** Vector AMO Operations (Zvamo)
*/
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 24/75] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (22 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 23/75] target/riscv: rvv-1.0: load/store whole register instructions frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 25/75] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation frank.chang
` (50 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 32 +++++++--
target/riscv/vector_helper.c | 90 ++++++++++++++-----------
2 files changed, 74 insertions(+), 48 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 2b0e0590efc..367fb28186f 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -586,6 +586,12 @@ static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE * a) \
return false; \
}
+static uint8_t vext_get_emul(DisasContext *s, uint8_t eew)
+{
+ int8_t emul = eew - s->sew + s->lmul;
+ return emul < 0 ? 0 : emul;
+}
+
/*
*** unit stride load and store
*/
@@ -651,8 +657,14 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew)
return false;
}
+ /*
+ * Vector load/store instructions have the EEW encoded
+ * directly in the instructions. The maximum vector size is
+ * calculated with EMUL rather than LMUL.
+ */
+ uint8_t emul = vext_get_emul(s, eew);
data = FIELD_DP32(data, VDATA, VM, a->vm);
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, LMUL, emul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
return ldst_us_trans(a->rd, a->rs1, data, fn, s, false);
}
@@ -687,8 +699,9 @@ static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew)
return false;
}
+ uint8_t emul = vext_get_emul(s, eew);
data = FIELD_DP32(data, VDATA, VM, a->vm);
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, LMUL, emul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
return ldst_us_trans(a->rd, a->rs1, data, fn, s, true);
}
@@ -761,8 +774,9 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
return false;
}
+ uint8_t emul = vext_get_emul(s, eew);
data = FIELD_DP32(data, VDATA, VM, a->vm);
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, LMUL, emul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
}
@@ -789,8 +803,9 @@ static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
gen_helper_vsse32_v, gen_helper_vsse64_v
};
+ uint8_t emul = vext_get_emul(s, eew);
data = FIELD_DP32(data, VDATA, VM, a->vm);
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, LMUL, emul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
fn = fns[eew];
if (fn == NULL) {
@@ -887,8 +902,9 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
fn = fns[eew][s->sew];
+ uint8_t emul = vext_get_emul(s, s->sew);
data = FIELD_DP32(data, VDATA, VM, a->vm);
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, LMUL, emul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
}
@@ -938,8 +954,9 @@ static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
fn = fns[eew][s->sew];
+ uint8_t emul = vext_get_emul(s, s->sew);
data = FIELD_DP32(data, VDATA, VM, a->vm);
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, LMUL, emul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, true);
}
@@ -1003,8 +1020,9 @@ static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew)
return false;
}
+ uint8_t emul = vext_get_emul(s, eew);
data = FIELD_DP32(data, VDATA, VM, a->vm);
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, LMUL, emul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
return ldff_trans(a->rd, a->rs1, data, fn, s);
}
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 57564c5c0c9..8556ab3b0df 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -17,6 +17,7 @@
*/
#include "qemu/osdep.h"
+#include "qemu/host-utils.h"
#include "cpu.h"
#include "exec/memop.h"
#include "exec/exec-all.h"
@@ -121,14 +122,21 @@ static uint32_t vext_wd(uint32_t desc)
}
/*
- * Get vector group length in bytes. Its range is [64, 2048].
+ * Get the maximum number of elements can be operated.
*
- * As simd_desc support at most 256, the max vlen is 512 bits.
- * So vlen in bytes is encoded as maxsz.
+ * esz: log2 of element size in bytes.
*/
-static inline uint32_t vext_maxsz(uint32_t desc)
+static inline uint32_t vext_max_elems(uint32_t desc, uint32_t esz)
{
- return simd_maxsz(desc) << vext_lmul(desc);
+ /*
+ * As simd_desc support at most 256 bytes, the max vlen is 256 bits.
+ * so vlen in bytes (vlenb) is encoded as maxsz.
+ */
+ uint32_t vlenb = simd_maxsz(desc);
+
+ /* Return VLMAX */
+ int scale = vext_lmul(desc) - esz;
+ return scale < 0 ? vlenb >> -scale : vlenb << scale;
}
/*
@@ -221,14 +229,14 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
{
uint32_t i, k;
uint32_t nf = vext_nf(desc);
- uint32_t vlmax = vext_maxsz(desc) / esz;
+ uint32_t max_elems = vext_max_elems(desc, esz);
/* probe every access*/
for (i = 0; i < env->vl; i++) {
if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
- probe_pages(env, base + stride * i, nf * esz, ra, access_type);
+ probe_pages(env, base + stride * i, nf << esz, ra, access_type);
}
/* do real access */
for (i = 0; i < env->vl; i++) {
@@ -237,8 +245,8 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
continue;
}
while (k < nf) {
- target_ulong addr = base + stride * i + k * esz;
- ldst_elem(env, addr, i + k * vlmax, vd, ra);
+ target_ulong addr = base + stride * i + (k << esz);
+ ldst_elem(env, addr, i + k * max_elems, vd, ra);
k++;
}
}
@@ -251,7 +259,7 @@ void HELPER(NAME)(void *vd, void * v0, target_ulong base, \
{ \
uint32_t vm = vext_vm(desc); \
vext_ldst_stride(vd, v0, base, stride, env, desc, vm, LOAD_FN, \
- sizeof(ETYPE), GETPC(), MMU_DATA_LOAD); \
+ ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_LOAD); \
}
GEN_VEXT_LD_STRIDE(vlse8_v, int8_t, lde_b)
@@ -266,7 +274,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
{ \
uint32_t vm = vext_vm(desc); \
vext_ldst_stride(vd, v0, base, stride, env, desc, vm, STORE_FN, \
- sizeof(ETYPE), GETPC(), MMU_DATA_STORE); \
+ ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_STORE); \
}
GEN_VEXT_ST_STRIDE(vsse8_v, int8_t, ste_b)
@@ -286,16 +294,16 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
{
uint32_t i, k;
uint32_t nf = vext_nf(desc);
- uint32_t vlmax = vext_maxsz(desc) / esz;
+ uint32_t max_elems = vext_max_elems(desc, esz);
/* probe every access */
- probe_pages(env, base, env->vl * nf * esz, ra, access_type);
+ probe_pages(env, base, env->vl * (nf << esz), ra, access_type);
/* load bytes from guest memory */
for (i = 0; i < env->vl; i++) {
k = 0;
while (k < nf) {
- target_ulong addr = base + (i * nf + k) * esz;
- ldst_elem(env, addr, i + k * vlmax, vd, ra);
+ target_ulong addr = base + ((i * nf + k) << esz);
+ ldst_elem(env, addr, i + k * max_elems, vd, ra);
k++;
}
}
@@ -310,16 +318,16 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t stride = vext_nf(desc) * sizeof(ETYPE); \
+ uint32_t stride = vext_nf(desc) << ctzl(sizeof(ETYPE)); \
vext_ldst_stride(vd, v0, base, stride, env, desc, false, LOAD_FN, \
- sizeof(ETYPE), GETPC(), MMU_DATA_LOAD); \
+ ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_LOAD); \
} \
\
void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
CPURISCVState *env, uint32_t desc) \
{ \
vext_ldst_us(vd, base, env, desc, LOAD_FN, \
- sizeof(ETYPE), GETPC(), MMU_DATA_LOAD); \
+ ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_LOAD); \
}
GEN_VEXT_LD_US(vle8_v, int8_t, lde_b)
@@ -331,16 +339,16 @@ GEN_VEXT_LD_US(vle64_v, int64_t, lde_d)
void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t stride = vext_nf(desc) * sizeof(ETYPE); \
+ uint32_t stride = vext_nf(desc) << ctzl(sizeof(ETYPE)); \
vext_ldst_stride(vd, v0, base, stride, env, desc, false, STORE_FN, \
- sizeof(ETYPE), GETPC(), MMU_DATA_STORE); \
+ ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_STORE); \
} \
\
void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
CPURISCVState *env, uint32_t desc) \
{ \
vext_ldst_us(vd, base, env, desc, STORE_FN, \
- sizeof(ETYPE), GETPC(), MMU_DATA_STORE); \
+ ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_STORE); \
}
GEN_VEXT_ST_US(vse8_v, int8_t, ste_b)
@@ -376,14 +384,14 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
uint32_t i, k;
uint32_t nf = vext_nf(desc);
uint32_t vm = vext_vm(desc);
- uint32_t vlmax = vext_maxsz(desc) / esz;
+ uint32_t max_elems = vext_max_elems(desc, esz);
/* probe every access*/
for (i = 0; i < env->vl; i++) {
if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
- probe_pages(env, get_index_addr(base, i, vs2), nf * esz, ra,
+ probe_pages(env, get_index_addr(base, i, vs2), nf << esz, ra,
access_type);
}
/* load bytes from guest memory */
@@ -393,8 +401,8 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
continue;
}
while (k < nf) {
- abi_ptr addr = get_index_addr(base, i, vs2) + k * esz;
- ldst_elem(env, addr, i + k * vlmax, vd, ra);
+ abi_ptr addr = get_index_addr(base, i, vs2) + (k << esz);
+ ldst_elem(env, addr, i + k * max_elems, vd, ra);
k++;
}
}
@@ -405,7 +413,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \
- LOAD_FN, sizeof(ETYPE), GETPC(), MMU_DATA_LOAD); \
+ LOAD_FN, ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_LOAD); \
}
GEN_VEXT_LD_INDEX(vlxei8_8_v, int8_t, idx_b, lde_b)
@@ -430,7 +438,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \
- STORE_FN, sizeof(ETYPE), \
+ STORE_FN, ctzl(sizeof(ETYPE)), \
GETPC(), MMU_DATA_STORE); \
}
@@ -464,7 +472,7 @@ vext_ldff(void *vd, void *v0, target_ulong base,
uint32_t i, k, vl = 0;
uint32_t nf = vext_nf(desc);
uint32_t vm = vext_vm(desc);
- uint32_t vlmax = vext_maxsz(desc) / esz;
+ uint32_t max_elems = vext_max_elems(desc, esz);
target_ulong addr, offset, remain;
/* probe every access*/
@@ -472,24 +480,24 @@ vext_ldff(void *vd, void *v0, target_ulong base,
if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
- addr = base + nf * i * esz;
+ addr = base + i * (nf << esz);
if (i == 0) {
- probe_pages(env, addr, nf * esz, ra, MMU_DATA_LOAD);
+ probe_pages(env, addr, nf << esz, ra, MMU_DATA_LOAD);
} else {
/* if it triggers an exception, no need to check watchpoint */
- remain = nf * esz;
+ remain = nf << esz;
while (remain > 0) {
offset = -(addr | TARGET_PAGE_MASK);
host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD,
cpu_mmu_index(env, false));
if (host) {
#ifdef CONFIG_USER_ONLY
- if (page_check_range(addr, nf * esz, PAGE_READ) < 0) {
+ if (page_check_range(addr, nf << esz, PAGE_READ) < 0) {
vl = i;
goto ProbeSuccess;
}
#else
- probe_pages(env, addr, nf * esz, ra, MMU_DATA_LOAD);
+ probe_pages(env, addr, nf << esz, ra, MMU_DATA_LOAD);
#endif
} else {
vl = i;
@@ -514,8 +522,8 @@ ProbeSuccess:
continue;
}
while (k < nf) {
- target_ulong addr = base + (i * nf + k) * esz;
- ldst_elem(env, addr, i + k * vlmax, vd, ra);
+ target_ulong addr = base + ((i * nf + k) << esz);
+ ldst_elem(env, addr, i + k * max_elems, vd, ra);
k++;
}
}
@@ -526,7 +534,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
CPURISCVState *env, uint32_t desc) \
{ \
vext_ldff(vd, v0, base, env, desc, LOAD_FN, \
- sizeof(ETYPE), GETPC()); \
+ ctzl(sizeof(ETYPE)), GETPC()); \
}
GEN_VEXT_LDFF(vle8ff_v, int8_t, lde_b)
@@ -739,7 +747,7 @@ void HELPER(NAME)(void *vs3, void *v0, target_ulong base, \
{ \
vext_amo_noatomic(vs3, v0, base, vs2, env, desc, \
INDEX_FN, vext_##NAME##_noatomic_op, \
- sizeof(ETYPE), GETPC()); \
+ ctzl(sizeof(ETYPE)), GETPC()); \
}
GEN_VEXT_AMO(vamoswapei8_32_v, int32_t, idx_b)
@@ -1225,7 +1233,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
uint32_t vl = env->vl; \
- uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
+ uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(ETYPE))); \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
@@ -3880,7 +3888,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
- uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
+ uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(ETYPE))); \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
@@ -4666,7 +4674,7 @@ GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, uint64_t, H8)
void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
+ uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(ETYPE))); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t index, i; \
@@ -4694,7 +4702,7 @@ GEN_VEXT_VRGATHER_VV(vrgather_vv_d, uint64_t, H8)
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
+ uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(ETYPE))); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t index = s1, i; \
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 25/75] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (23 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 24/75] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 26/75] target/riscv: rvv-1.0: floating-point square-root instruction frank.chang
` (49 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Update vext_get_vlmax() and MAXSZ() to take fractional LMUL into
calculation for RVV 1.0.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 43 ++++++++++++++++++-------
target/riscv/insn_trans/trans_rvv.c.inc | 12 ++++++-
2 files changed, 42 insertions(+), 13 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index ad79669a2ce..367b182735f 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -395,18 +395,27 @@ FIELD(TB_FLAGS, HLSX, 15, 1)
bool riscv_cpu_is_32bit(CPURISCVState *env);
/*
- * A simplification for VLMAX
- * = (1 << LMUL) * VLEN / (8 * (1 << SEW))
- * = (VLEN << LMUL) / (8 << SEW)
- * = (VLEN << LMUL) >> (SEW + 3)
- * = VLEN >> (SEW + 3 - LMUL)
+ * Encode LMUL to lmul as follows:
+ * LMUL vlmul lmul
+ * 1 000 0
+ * 2 001 1
+ * 4 010 2
+ * 8 011 3
+ * - 100 -
+ * 1/8 101 -3
+ * 1/4 110 -2
+ * 1/2 111 -1
+ *
+ * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul)
+ * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8
+ * => VLMAX = vlen >> (1 + 3 - (-3))
+ * = 256 >> 7
+ * = 2
*/
static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
{
- uint8_t sew, lmul;
-
- sew = FIELD_EX64(vtype, VTYPE, VSEW);
- lmul = FIELD_EX64(vtype, VTYPE, VLMUL);
+ uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW);
+ int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3);
return cpu->cfg.vlen >> (sew + 3 - lmul);
}
@@ -419,12 +428,22 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
*cs_base = 0;
if (riscv_has_ext(env, RVV)) {
+ /*
+ * If env->vl equals to VLMAX, we can use generic vector operation
+ * expanders (GVEC) to accerlate the vector operations.
+ * However, as LMUL could be a fractional number. The maximum
+ * vector size can be operated might be less than 8 bytes,
+ * which is not supported by GVEC. So we set vl_eq_vlmax flag to true
+ * only when maxsz >= 8 bytes.
+ */
uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype);
- bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl);
+ uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW);
+ uint32_t maxsz = vlmax << sew;
+ bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl)
+ && (maxsz >= 8);
flags = FIELD_DP32(flags, TB_FLAGS, VILL,
FIELD_EX64(env->vtype, VTYPE, VILL));
- flags = FIELD_DP32(flags, TB_FLAGS, SEW,
- FIELD_EX64(env->vtype, VTYPE, VSEW));
+ flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew);
flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
FIELD_EX64(env->vtype, VTYPE, VLMUL));
flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 367fb28186f..72d0bc109b0 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1268,7 +1268,17 @@ GEN_VEXT_AMO_TRANS(vamomaxuei64_v, MO_64, 35, rwdvm, amo_op, amo_check)
/*
*** Vector Integer Arithmetic Instructions
*/
-#define MAXSZ(s) (s->vlen >> (3 - s->lmul))
+
+/*
+ * MAXSZ returns the maximum vector size can be operated in bytes,
+ * which is used in GVEC IR when vl_eq_vlmax flag is set to true
+ * to accerlate vector operation.
+ */
+static inline uint32_t MAXSZ(DisasContext *s)
+{
+ int scale = s->lmul - 3;
+ return scale < 0 ? s->vlen >> -scale : s->vlen << scale;
+}
static bool opivv_check(DisasContext *s, arg_rmrr *a)
{
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 26/75] target/riscv: rvv-1.0: floating-point square-root instruction
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (24 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 25/75] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 27/75] target/riscv: rvv-1.0: floating-point classify instructions frank.chang
` (48 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Alistair Francis, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index e11666f16df..c0053cfb828 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -538,7 +538,7 @@ vfwmsac_vv 111110 . ..... ..... 001 ..... 1010111 @r_vm
vfwmsac_vf 111110 . ..... ..... 101 ..... 1010111 @r_vm
vfwnmsac_vv 111111 . ..... ..... 001 ..... 1010111 @r_vm
vfwnmsac_vf 111111 . ..... ..... 101 ..... 1010111 @r_vm
-vfsqrt_v 100011 . ..... 00000 001 ..... 1010111 @r2_vm
+vfsqrt_v 010011 . ..... 00000 001 ..... 1010111 @r2_vm
vfmin_vv 000100 . ..... ..... 001 ..... 1010111 @r_vm
vfmin_vf 000100 . ..... ..... 101 ..... 1010111 @r_vm
vfmax_vv 000110 . ..... ..... 001 ..... 1010111 @r_vm
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 27/75] target/riscv: rvv-1.0: floating-point classify instructions
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (25 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 26/75] target/riscv: rvv-1.0: floating-point square-root instruction frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 28/75] target/riscv: rvv-1.0: mask population count instruction frank.chang
` (47 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Alistair Francis, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index c0053cfb828..a0a47dbceb3 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -561,7 +561,7 @@ vmfgt_vf 011101 . ..... ..... 101 ..... 1010111 @r_vm
vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm
vmford_vv 011010 . ..... ..... 001 ..... 1010111 @r_vm
vmford_vf 011010 . ..... ..... 101 ..... 1010111 @r_vm
-vfclass_v 100011 . ..... 10000 001 ..... 1010111 @r2_vm
+vfclass_v 010011 . ..... 10000 001 ..... 1010111 @r2_vm
vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0
vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2
vfcvt_xu_f_v 100010 . ..... 00000 001 ..... 1010111 @r2_vm
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 28/75] target/riscv: rvv-1.0: mask population count instruction
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (26 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 27/75] target/riscv: rvv-1.0: floating-point classify instructions frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 29/75] target/riscv: rvv-1.0: find-first-set mask bit instruction frank.chang
` (46 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/helper.h | 2 +-
target/riscv/insn32.decode | 2 +-
target/riscv/insn_trans/trans_rvv.c.inc | 7 ++++---
target/riscv/vector_helper.c | 6 +++---
4 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 5ec364caecc..9d1601510f7 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1061,7 +1061,7 @@ DEF_HELPER_6(vmnor_mm, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vmornot_mm, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vmxnor_mm, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_4(vmpopc_m, tl, ptr, ptr, env, i32)
+DEF_HELPER_4(vpopc_m, tl, ptr, ptr, env, i32)
DEF_HELPER_4(vmfirst_m, tl, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index a0a47dbceb3..0f111c885c3 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -602,7 +602,7 @@ vmor_mm 011010 - ..... ..... 010 ..... 1010111 @r
vmnor_mm 011110 - ..... ..... 010 ..... 1010111 @r
vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r
vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r
-vmpopc_m 010100 . ..... ----- 010 ..... 1010111 @r2_vm
+vpopc_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm
vmfirst_m 010101 . ..... ----- 010 ..... 1010111 @r2_vm
vmsbf_m 010110 . ..... 00001 010 ..... 1010111 @r2_vm
vmsif_m 010110 . ..... 00011 010 ..... 1010111 @r2_vm
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 72d0bc109b0..f658f8566da 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2893,8 +2893,8 @@ GEN_MM_TRANS(vmnor_mm)
GEN_MM_TRANS(vmornot_mm)
GEN_MM_TRANS(vmxnor_mm)
-/* Vector mask population count vmpopc */
-static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
+/* Vector mask population count vpopc */
+static bool trans_vpopc_m(DisasContext *s, arg_rmr *a)
{
if (require_rvv(s) &&
vext_check_isa_ill(s)) {
@@ -2913,13 +2913,14 @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
- gen_helper_vmpopc_m(dst, mask, src2, cpu_env, desc);
+ gen_helper_vpopc_m(dst, mask, src2, cpu_env, desc);
gen_set_gpr(a->rd, dst);
tcg_temp_free_ptr(mask);
tcg_temp_free_ptr(src2);
tcg_temp_free(dst);
tcg_temp_free_i32(desc);
+
return true;
}
return false;
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 8556ab3b0df..517e7344b96 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4420,9 +4420,9 @@ GEN_VEXT_MASK_VV(vmnor_mm, DO_NOR)
GEN_VEXT_MASK_VV(vmornot_mm, DO_ORNOT)
GEN_VEXT_MASK_VV(vmxnor_mm, DO_XNOR)
-/* Vector mask population count vmpopc */
-target_ulong HELPER(vmpopc_m)(void *v0, void *vs2, CPURISCVState *env,
- uint32_t desc)
+/* Vector mask population count vpopc */
+target_ulong HELPER(vpopc_m)(void *v0, void *vs2, CPURISCVState *env,
+ uint32_t desc)
{
target_ulong cnt = 0;
uint32_t vm = vext_vm(desc);
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 29/75] target/riscv: rvv-1.0: find-first-set mask bit instruction
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (27 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 28/75] target/riscv: rvv-1.0: mask population count instruction frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 30/75] target/riscv: rvv-1.0: set-X-first mask bit instructions frank.chang
` (45 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/helper.h | 2 +-
target/riscv/insn32.decode | 2 +-
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
target/riscv/vector_helper.c | 6 +++---
4 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 9d1601510f7..abf08dbc710 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1063,7 +1063,7 @@ DEF_HELPER_6(vmxnor_mm, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_4(vpopc_m, tl, ptr, ptr, env, i32)
-DEF_HELPER_4(vmfirst_m, tl, ptr, ptr, env, i32)
+DEF_HELPER_4(vfirst_m, tl, ptr, ptr, env, i32)
DEF_HELPER_5(vmsbf_m, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vmsif_m, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 0f111c885c3..0b53ce432c1 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -603,7 +603,7 @@ vmnor_mm 011110 - ..... ..... 010 ..... 1010111 @r
vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r
vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r
vpopc_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm
-vmfirst_m 010101 . ..... ----- 010 ..... 1010111 @r2_vm
+vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm
vmsbf_m 010110 . ..... 00001 010 ..... 1010111 @r2_vm
vmsif_m 010110 . ..... 00011 010 ..... 1010111 @r2_vm
vmsof_m 010110 . ..... 00010 010 ..... 1010111 @r2_vm
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index f658f8566da..97ad16f2b21 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2927,7 +2927,7 @@ static bool trans_vpopc_m(DisasContext *s, arg_rmr *a)
}
/* vmfirst find-first-set mask bit */
-static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a)
+static bool trans_vfirst_m(DisasContext *s, arg_rmr *a)
{
if (require_rvv(s) &&
vext_check_isa_ill(s)) {
@@ -2946,7 +2946,7 @@ static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a)
tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
- gen_helper_vmfirst_m(dst, mask, src2, cpu_env, desc);
+ gen_helper_vfirst_m(dst, mask, src2, cpu_env, desc);
gen_set_gpr(a->rd, dst);
tcg_temp_free_ptr(mask);
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 517e7344b96..ecc9be77335 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4439,9 +4439,9 @@ target_ulong HELPER(vpopc_m)(void *v0, void *vs2, CPURISCVState *env,
return cnt;
}
-/* vmfirst find-first-set mask bit*/
-target_ulong HELPER(vmfirst_m)(void *v0, void *vs2, CPURISCVState *env,
- uint32_t desc)
+/* vfirst find-first-set mask bit*/
+target_ulong HELPER(vfirst_m)(void *v0, void *vs2, CPURISCVState *env,
+ uint32_t desc)
{
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 30/75] target/riscv: rvv-1.0: set-X-first mask bit instructions
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (28 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 29/75] target/riscv: rvv-1.0: find-first-set mask bit instruction frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 31/75] target/riscv: rvv-1.0: iota instruction frank.chang
` (44 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn32.decode | 6 +++---
target/riscv/insn_trans/trans_rvv.c.inc | 5 ++++-
target/riscv/vector_helper.c | 4 ----
3 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 0b53ce432c1..6b3caef1721 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -604,9 +604,9 @@ vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r
vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r
vpopc_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm
vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm
-vmsbf_m 010110 . ..... 00001 010 ..... 1010111 @r2_vm
-vmsif_m 010110 . ..... 00011 010 ..... 1010111 @r2_vm
-vmsof_m 010110 . ..... 00010 010 ..... 1010111 @r2_vm
+vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm
+vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm
+vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm
viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm
vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm
vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 97ad16f2b21..5b229d55307 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2964,7 +2964,10 @@ static bool trans_vfirst_m(DisasContext *s, arg_rmr *a)
#define GEN_M_TRANS(NAME) \
static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
{ \
- if (vext_check_isa_ill(s)) { \
+ if (require_rvv(s) && \
+ vext_check_isa_ill(s) && \
+ require_vm(a->vm, a->rd) && \
+ (a->rd != a->rs2)) { \
uint32_t data = 0; \
gen_helper_gvec_3_ptr *fn = gen_helper_##NAME; \
TCGLabel *over = gen_new_label(); \
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index ecc9be77335..8ccf538141c 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4466,7 +4466,6 @@ enum set_mask_type {
static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env,
uint32_t desc, enum set_mask_type type)
{
- uint32_t vlmax = env_archcpu(env)->cfg.vlen;
uint32_t vm = vext_vm(desc);
uint32_t vl = env->vl;
int i;
@@ -4496,9 +4495,6 @@ static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env,
}
}
}
- for (; i < vlmax; i++) {
- vext_set_elem_mask(vd, i, 0);
- }
}
void HELPER(vmsbf_m)(void *vd, void *v0, void *vs2, CPURISCVState *env,
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 31/75] target/riscv: rvv-1.0: iota instruction
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (29 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 30/75] target/riscv: rvv-1.0: set-X-first mask bit instructions frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 32/75] target/riscv: rvv-1.0: element index instruction frank.chang
` (43 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn32.decode | 2 +-
target/riscv/insn_trans/trans_rvv.c.inc | 10 ++++++++--
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 6b3caef1721..fae5ea3fa63 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -607,7 +607,7 @@ vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm
vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm
vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm
vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm
-viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm
+viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm
vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm
vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 5b229d55307..6e45186b9b4 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2989,12 +2989,18 @@ GEN_M_TRANS(vmsbf_m)
GEN_M_TRANS(vmsif_m)
GEN_M_TRANS(vmsof_m)
-/* Vector Iota Instruction */
+/*
+ * Vector Iota Instruction
+ *
+ * 1. The destination register cannot overlap the source register.
+ * 2. If masked, cannot overlap the mask register ('v0').
+ * 3. An illegal instruction exception is raised if vstart is non-zero.
+ */
static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
{
if (require_rvv(s) &&
vext_check_isa_ill(s) &&
- require_noover(a->rd, s->lmul, a->rs2, 0) &&
+ !is_overlapped(a->rd, 1 << MAX(s->lmul, 0), a->rs2, 1) &&
require_vm(a->vm, a->rd) &&
require_align(a->rd, s->lmul)) {
uint32_t data = 0;
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 32/75] target/riscv: rvv-1.0: element index instruction
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (30 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 31/75] target/riscv: rvv-1.0: iota instruction frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 33/75] target/riscv: rvv-1.0: allow load element with sign-extended frank.chang
` (42 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Alistair Francis, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index fae5ea3fa63..a593938e5c8 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -608,7 +608,7 @@ vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm
vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm
vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm
viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm
-vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm
+vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm
vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2
vfmv_f_s 001100 1 ..... 00000 001 ..... 1010111 @r2rd
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 33/75] target/riscv: rvv-1.0: allow load element with sign-extended
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (31 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 32/75] target/riscv: rvv-1.0: element index instruction frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 34/75] target/riscv: rvv-1.0: register gather instructions frank.chang
` (41 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
For some vector instructions (e.g. vmv.s.x), the element is loaded with
sign-extended.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvv.c.inc | 32 +++++++++++++++++--------
1 file changed, 22 insertions(+), 10 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 6e45186b9b4..72222d73e0e 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3056,17 +3056,29 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
/* Integer Extract Instruction */
static void load_element(TCGv_i64 dest, TCGv_ptr base,
- int ofs, int sew)
+ int ofs, int sew, bool sign)
{
switch (sew) {
case MO_8:
- tcg_gen_ld8u_i64(dest, base, ofs);
+ if (!sign) {
+ tcg_gen_ld8u_i64(dest, base, ofs);
+ } else {
+ tcg_gen_ld8s_i64(dest, base, ofs);
+ }
break;
case MO_16:
- tcg_gen_ld16u_i64(dest, base, ofs);
+ if (!sign) {
+ tcg_gen_ld16u_i64(dest, base, ofs);
+ } else {
+ tcg_gen_ld16s_i64(dest, base, ofs);
+ }
break;
case MO_32:
- tcg_gen_ld32u_i64(dest, base, ofs);
+ if (!sign) {
+ tcg_gen_ld32u_i64(dest, base, ofs);
+ } else {
+ tcg_gen_ld32s_i64(dest, base, ofs);
+ }
break;
case MO_64:
tcg_gen_ld_i64(dest, base, ofs);
@@ -3121,7 +3133,7 @@ static void vec_element_loadx(DisasContext *s, TCGv_i64 dest,
/* Perform the load. */
load_element(dest, base,
- vreg_ofs(s, vreg), s->sew);
+ vreg_ofs(s, vreg), s->sew, false);
tcg_temp_free_ptr(base);
tcg_temp_free_i32(ofs);
@@ -3139,9 +3151,9 @@ static void vec_element_loadx(DisasContext *s, TCGv_i64 dest,
}
static void vec_element_loadi(DisasContext *s, TCGv_i64 dest,
- int vreg, int idx)
+ int vreg, int idx, bool sign)
{
- load_element(dest, cpu_env, endian_ofs(s, vreg, idx), s->sew);
+ load_element(dest, cpu_env, endian_ofs(s, vreg, idx), s->sew, sign);
}
static bool trans_vext_x_v(DisasContext *s, arg_r *a)
@@ -3151,7 +3163,7 @@ static bool trans_vext_x_v(DisasContext *s, arg_r *a)
if (a->rs1 == 0) {
/* Special case vmv.x.s rd, vs2. */
- vec_element_loadi(s, tmp, a->rs2, 0);
+ vec_element_loadi(s, tmp, a->rs2, 0, false);
} else {
/* This instruction ignores LMUL and vector register groups */
int vlmax = s->vlen >> (3 + s->sew);
@@ -3233,7 +3245,7 @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a)
(s->mstatus_fs != 0) && (s->sew != 0)) {
unsigned int len = 8 << s->sew;
- vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0);
+ vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0, false);
if (len < 64) {
tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd],
MAKE_64BIT_MASK(len, 64 - len));
@@ -3335,7 +3347,7 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a)
TCGv_i64 dest = tcg_temp_new_i64();
if (a->rs1 == 0) {
- vec_element_loadi(s, dest, a->rs2, 0);
+ vec_element_loadi(s, dest, a->rs2, 0, false);
} else {
vec_element_loadx(s, dest, a->rs2, cpu_gpr[a->rs1], vlmax);
}
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 34/75] target/riscv: rvv-1.0: register gather instructions
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (32 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 33/75] target/riscv: rvv-1.0: allow load element with sign-extended frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 35/75] target/riscv: rvv-1.0: integer scalar move instructions frank.chang
` (40 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
* Add vrgatherei16.vv instruction.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/helper.h | 4 ++++
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.c.inc | 27 ++++++++++++++++++++++---
target/riscv/vector_helper.c | 23 ++++++++++++---------
4 files changed, 43 insertions(+), 12 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index abf08dbc710..ea6c39b49a8 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1100,6 +1100,10 @@ DEF_HELPER_6(vrgather_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vrgather_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vrgather_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vrgather_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vrgatherei16_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vrgatherei16_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vrgatherei16_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vrgatherei16_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vrgather_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vrgather_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vrgather_vx_w, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index a593938e5c8..85cb3c81be0 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -620,6 +620,7 @@ vslidedown_vx 001111 . ..... ..... 100 ..... 1010111 @r_vm
vslidedown_vi 001111 . ..... ..... 011 ..... 1010111 @r_vm
vslide1down_vx 001111 . ..... ..... 110 ..... 1010111 @r_vm
vrgather_vv 001100 . ..... ..... 000 ..... 1010111 @r_vm
+vrgatherei16_vv 001110 . ..... ..... 000 ..... 1010111 @r_vm
vrgather_vx 001100 . ..... ..... 100 ..... 1010111 @r_vm
vrgather_vi 001100 . ..... ..... 011 ..... 1010111 @r_vm
vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 72222d73e0e..bc780912b2b 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3323,7 +3323,25 @@ static bool vrgather_vv_check(DisasContext *s, arg_rmrr *a)
require_vm(a->vm, a->rd);
}
+static bool vrgatherei16_vv_check(DisasContext *s, arg_rmrr *a)
+{
+ int8_t emul = MO_16 - s->sew + s->lmul;
+ return require_rvv(s) &&
+ vext_check_isa_ill(s) &&
+ (emul >= -3 && emul <= 3) &&
+ require_align(a->rd, s->lmul) &&
+ require_align(a->rs1, emul) &&
+ require_align(a->rs2, s->lmul) &&
+ (a->rd != a->rs2 && a->rd != a->rs1) &&
+ !is_overlapped(a->rd, 1 << MAX(s->lmul, 0),
+ a->rs1, 1 << MAX(emul, 0)) &&
+ !is_overlapped(a->rd, 1 << MAX(s->lmul, 0),
+ a->rs2, 1 << MAX(s->lmul, 0)) &&
+ require_vm(a->vm, a->rd);
+}
+
GEN_OPIVV_TRANS(vrgather_vv, vrgather_vv_check)
+GEN_OPIVV_TRANS(vrgatherei16_vv, vrgatherei16_vv_check)
static bool vrgather_vx_check(DisasContext *s, arg_rmrr *a)
{
@@ -3343,7 +3361,8 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a)
}
if (a->vm && s->vl_eq_vlmax) {
- int vlmax = s->vlen;
+ int scale = s->lmul - (s->sew + 3);
+ int vlmax = scale < 0 ? s->vlen >> -scale : s->vlen << scale;
TCGv_i64 dest = tcg_temp_new_i64();
if (a->rs1 == 0) {
@@ -3374,8 +3393,10 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a)
}
if (a->vm && s->vl_eq_vlmax) {
- if (a->rs1 >= s->vlen) {
- tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd),
+ int scale = s->lmul - (s->sew + 3);
+ int vlmax = scale < 0 ? s->vlen >> -scale : s->vlen << scale;
+ if (a->rs1 >= vlmax) {
+ tcg_gen_gvec_dup_imm(MO_64, vreg_ofs(s, a->rd),
MAXSZ(s), MAXSZ(s), 0);
} else {
tcg_gen_gvec_dup_mem(s->sew, vreg_ofs(s, a->rd),
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 8ccf538141c..782fe086f3e 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4666,11 +4666,11 @@ GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_w, uint32_t, H4)
GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, uint64_t, H8)
/* Vector Register Gather Instruction */
-#define GEN_VEXT_VRGATHER_VV(NAME, ETYPE, H) \
+#define GEN_VEXT_VRGATHER_VV(NAME, TS1, TS2, HS1, HS2) \
void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(ETYPE))); \
+ uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(TS1))); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t index, i; \
@@ -4679,20 +4679,25 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
- index = *((ETYPE *)vs1 + H(i)); \
+ index = *((TS1 *)vs1 + HS1(i)); \
if (index >= vlmax) { \
- *((ETYPE *)vd + H(i)) = 0; \
+ *((TS2 *)vd + HS2(i)) = 0; \
} else { \
- *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(index)); \
+ *((TS2 *)vd + HS2(i)) = *((TS2 *)vs2 + HS2(index)); \
} \
} \
}
/* vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]]; */
-GEN_VEXT_VRGATHER_VV(vrgather_vv_b, uint8_t, H1)
-GEN_VEXT_VRGATHER_VV(vrgather_vv_h, uint16_t, H2)
-GEN_VEXT_VRGATHER_VV(vrgather_vv_w, uint32_t, H4)
-GEN_VEXT_VRGATHER_VV(vrgather_vv_d, uint64_t, H8)
+GEN_VEXT_VRGATHER_VV(vrgather_vv_b, uint8_t, uint8_t, H1, H1)
+GEN_VEXT_VRGATHER_VV(vrgather_vv_h, uint16_t, uint16_t, H2, H2)
+GEN_VEXT_VRGATHER_VV(vrgather_vv_w, uint32_t, uint32_t, H4, H4)
+GEN_VEXT_VRGATHER_VV(vrgather_vv_d, uint64_t, uint64_t, H8, H8)
+
+GEN_VEXT_VRGATHER_VV(vrgatherei16_vv_b, uint16_t, uint8_t, H2, H1)
+GEN_VEXT_VRGATHER_VV(vrgatherei16_vv_h, uint16_t, uint16_t, H2, H2)
+GEN_VEXT_VRGATHER_VV(vrgatherei16_vv_w, uint16_t, uint32_t, H2, H4)
+GEN_VEXT_VRGATHER_VV(vrgatherei16_vv_d, uint16_t, uint64_t, H2, H8)
#define GEN_VEXT_VRGATHER_VX(NAME, ETYPE, H) \
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 35/75] target/riscv: rvv-1.0: integer scalar move instructions
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (33 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 34/75] target/riscv: rvv-1.0: register gather instructions frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 36/75] target/riscv: rvv-1.0: floating-point move instruction frank.chang
` (39 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
* Remove "vmv.s.x: dothing if rs1 == 0" constraint.
* Add vmv.x.s instruction.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn32.decode | 3 +-
target/riscv/insn_trans/trans_rvv.c.inc | 45 ++++++++++++++++++++-----
2 files changed, 39 insertions(+), 9 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 85cb3c81be0..f26723a4d27 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -609,8 +609,9 @@ vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm
vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm
viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm
vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm
+vmv_x_s 010000 1 ..... 00000 010 ..... 1010111 @r2rd
+vmv_s_x 010000 1 00000 ..... 110 ..... 1010111 @r2
vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
-vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2
vfmv_f_s 001100 1 ..... 00000 001 ..... 1010111 @r2rd
vfmv_s_f 001101 1 00000 ..... 101 ..... 1010111 @r2
vslideup_vx 001110 . ..... ..... 100 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index bc780912b2b..1839fc0a56b 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3211,27 +3211,56 @@ static void vec_element_storei(DisasContext *s, int vreg,
store_element(val, cpu_env, endian_ofs(s, vreg, idx), s->sew);
}
+/* vmv.x.s rd, vs2 # x[rd] = vs2[0] */
+static bool trans_vmv_x_s(DisasContext *s, arg_vmv_x_s *a)
+{
+ if (require_rvv(s) &&
+ vext_check_isa_ill(s)) {
+ TCGv_i64 t1;
+ TCGv dest;
+
+ t1 = tcg_temp_new_i64();
+ dest = tcg_temp_new();
+ /*
+ * load vreg and sign-extend to 64 bits,
+ * then truncate to XLEN bits before storing to gpr.
+ */
+ vec_element_loadi(s, t1, a->rs2, 0, true);
+ tcg_gen_trunc_i64_tl(dest, t1);
+ gen_set_gpr(a->rd, dest);
+ tcg_temp_free_i64(t1);
+ tcg_temp_free(dest);
+
+ return true;
+ }
+ return false;
+}
+
/* vmv.s.x vd, rs1 # vd[0] = rs1 */
static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
{
- if (vext_check_isa_ill(s)) {
+ if (require_rvv(s) &&
+ vext_check_isa_ill(s)) {
/* This instruction ignores LMUL and vector register groups */
- int maxsz = s->vlen >> 3;
TCGv_i64 t1;
+ TCGv s1;
TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
- tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), maxsz, maxsz, 0);
- if (a->rs1 == 0) {
- goto done;
- }
t1 = tcg_temp_new_i64();
- tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]);
+ s1 = tcg_temp_new();
+
+ /*
+ * load gpr and sign-extend to 64 bits,
+ * then truncate to SEW bits when storing to vreg.
+ */
+ gen_get_gpr(s1, a->rs1);
+ tcg_gen_ext_tl_i64(t1, s1);
vec_element_storei(s, a->rd, 0, t1);
tcg_temp_free_i64(t1);
+ tcg_temp_free(s1);
mark_vs_dirty(s);
- done:
gen_set_label(over);
return true;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 36/75] target/riscv: rvv-1.0: floating-point move instruction
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (34 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 35/75] target/riscv: rvv-1.0: integer scalar move instructions frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 37/75] target/riscv: rvv-1.0: floating-point scalar move instructions frank.chang
` (38 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
NaN-boxed the scalar floating-point register based on RVV 1.0's rules.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 1839fc0a56b..7ac7d6a2b92 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2691,9 +2691,15 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
require_rvf(s) &&
vext_check_isa_ill(s) &&
require_align(a->rd, s->lmul)) {
+ TCGv_i64 t1;
+
if (s->vl_eq_vlmax) {
+ t1 = tcg_temp_new_i64();
+ /* NaN-box f[rs1] */
+ do_nanbox(s, t1, cpu_fpr[a->rs1]);
+
tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
- MAXSZ(s), MAXSZ(s), cpu_fpr[a->rs1]);
+ MAXSZ(s), MAXSZ(s), t1);
mark_vs_dirty(s);
} else {
TCGv_ptr dest;
@@ -2707,16 +2713,22 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+ t1 = tcg_temp_new_i64();
+ /* NaN-box f[rs1] */
+ do_nanbox(s, t1, cpu_fpr[a->rs1]);
+
dest = tcg_temp_new_ptr();
desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
- fns[s->sew - 1](dest, cpu_fpr[a->rs1], cpu_env, desc);
+
+ fns[s->sew - 1](dest, t1, cpu_env, desc);
tcg_temp_free_ptr(dest);
tcg_temp_free_i32(desc);
mark_vs_dirty(s);
gen_set_label(over);
}
+ tcg_temp_free_i64(t1);
return true;
}
return false;
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 37/75] target/riscv: rvv-1.0: floating-point scalar move instructions
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (35 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 36/75] target/riscv: rvv-1.0: floating-point move instruction frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 38/75] target/riscv: rvv-1.0: whole register " frank.chang
` (37 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
NaN-boxed the scalar floating-point register based on RVV 1.0's rules.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 4 +--
target/riscv/insn_trans/trans_rvv.c.inc | 39 +++++++++++++------------
target/riscv/internals.h | 5 ----
3 files changed, 22 insertions(+), 26 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index f26723a4d27..8516a12b126 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -612,8 +612,8 @@ vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm
vmv_x_s 010000 1 ..... 00000 010 ..... 1010111 @r2rd
vmv_s_x 010000 1 00000 ..... 110 ..... 1010111 @r2
vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
-vfmv_f_s 001100 1 ..... 00000 001 ..... 1010111 @r2rd
-vfmv_s_f 001101 1 00000 ..... 101 ..... 1010111 @r2
+vfmv_f_s 010000 1 ..... 00000 001 ..... 1010111 @r2rd
+vfmv_s_f 010000 1 00000 ..... 101 ..... 1010111 @r2
vslideup_vx 001110 . ..... ..... 100 ..... 1010111 @r_vm
vslideup_vi 001110 . ..... ..... 011 ..... 1010111 @r_vm
vslide1up_vx 001110 . ..... ..... 110 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 7ac7d6a2b92..63e31299b3b 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3282,14 +3282,20 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
/* Floating-Point Scalar Move Instructions */
static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a)
{
- if (!s->vill && has_ext(s, RVF) &&
- (s->mstatus_fs != 0) && (s->sew != 0)) {
- unsigned int len = 8 << s->sew;
+ if (require_rvv(s) &&
+ require_rvf(s) &&
+ vext_check_isa_ill(s)) {
+ unsigned int ofs = (8 << s->sew);
+ unsigned int len = 64 - ofs;
+ TCGv_i64 t_nan;
vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0, false);
- if (len < 64) {
- tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd],
- MAKE_64BIT_MASK(len, 64 - len));
+ /* NaN-box f[rd] as necessary for SEW */
+ if (len) {
+ t_nan = tcg_const_i64(UINT64_MAX);
+ tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rd],
+ t_nan, ofs, len);
+ tcg_temp_free_i64(t_nan);
}
mark_fs_dirty(s);
@@ -3301,25 +3307,20 @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a)
/* vfmv.s.f vd, rs1 # vd[0] = rs1 (vs2=0) */
static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
{
- if (!s->vill && has_ext(s, RVF) && (s->sew != 0)) {
- TCGv_i64 t1;
+ if (require_rvv(s) &&
+ require_rvf(s) &&
+ vext_check_isa_ill(s)) {
/* The instructions ignore LMUL and vector register group. */
- uint32_t vlmax = s->vlen >> 3;
+ TCGv_i64 t1;
+ TCGLabel *over = gen_new_label();
/* if vl == 0, skip vector register write back */
- TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
- /* zeroed all elements */
- tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), vlmax, vlmax, 0);
-
- /* NaN-box f[rs1] as necessary for SEW */
+ /* NaN-box f[rs1] */
t1 = tcg_temp_new_i64();
- if (s->sew == MO_64 && !has_ext(s, RVD)) {
- tcg_gen_ori_i64(t1, cpu_fpr[a->rs1], MAKE_64BIT_MASK(32, 32));
- } else {
- tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]);
- }
+ do_nanbox(s, t1, cpu_fpr[a->rs1]);
+
vec_element_storei(s, a->rd, 0, t1);
tcg_temp_free_i64(t1);
mark_vs_dirty(s);
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index c3bbeea9a94..959b81b3016 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -32,11 +32,6 @@ target_ulong fclass_h(uint64_t frs1);
target_ulong fclass_s(uint64_t frs1);
target_ulong fclass_d(uint64_t frs1);
-#define SEW8 0
-#define SEW16 1
-#define SEW32 2
-#define SEW64 3
-
#ifndef CONFIG_USER_ONLY
extern const VMStateDescription vmstate_riscv_cpu;
#endif
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 38/75] target/riscv: rvv-1.0: whole register move instructions
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (36 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 37/75] target/riscv: rvv-1.0: floating-point scalar move instructions frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 39/75] target/riscv: rvv-1.0: integer extension instructions frank.chang
` (36 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Add the following instructions:
* vmv1r.v
* vmv2r.v
* vmv4r.v
* vmv8r.v
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 4 ++++
target/riscv/insn_trans/trans_rvv.c.inc | 25 +++++++++++++++++++++++++
2 files changed, 29 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 8516a12b126..beef6ca7167 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -625,6 +625,10 @@ vrgatherei16_vv 001110 . ..... ..... 000 ..... 1010111 @r_vm
vrgather_vx 001100 . ..... ..... 100 ..... 1010111 @r_vm
vrgather_vi 001100 . ..... ..... 011 ..... 1010111 @r_vm
vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r
+vmv1r_v 100111 1 ..... 00000 011 ..... 1010111 @r2rd
+vmv2r_v 100111 1 ..... 00001 011 ..... 1010111 @r2rd
+vmv4r_v 100111 1 ..... 00011 011 ..... 1010111 @r2rd
+vmv8r_v 100111 1 ..... 00111 011 ..... 1010111 @r2rd
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 63e31299b3b..f92e5c806c8 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3489,3 +3489,28 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
}
return false;
}
+
+/*
+ * Whole Vector Register Move Instructions ignore vtype and vl setting.
+ * Thus, we don't need to check vill bit. (Section 17.6)
+ */
+#define GEN_VMV_WHOLE_TRANS(NAME, LEN) \
+static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
+{ \
+ if (require_rvv(s) && \
+ QEMU_IS_ALIGNED(a->rd, LEN) && \
+ QEMU_IS_ALIGNED(a->rs2, LEN)) { \
+ /* EEW = 8 */ \
+ tcg_gen_gvec_mov(MO_8, vreg_ofs(s, a->rd), \
+ vreg_ofs(s, a->rs2), \
+ s->vlen / 8 * LEN, s->vlen / 8 * LEN); \
+ mark_vs_dirty(s); \
+ return true; \
+ } \
+ return false; \
+}
+
+GEN_VMV_WHOLE_TRANS(vmv1r_v, 1)
+GEN_VMV_WHOLE_TRANS(vmv2r_v, 2)
+GEN_VMV_WHOLE_TRANS(vmv4r_v, 4)
+GEN_VMV_WHOLE_TRANS(vmv8r_v, 8)
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 39/75] target/riscv: rvv-1.0: integer extension instructions
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (37 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 38/75] target/riscv: rvv-1.0: whole register " frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 40/75] target/riscv: rvv-1.0: single-width averaging add and subtract instructions frank.chang
` (35 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Add the following instructions:
* vzext.vf2
* vzext.vf4
* vzext.vf8
* vsext.vf2
* vsext.vf4
* vsext.vf8
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/helper.h | 14 +++++
target/riscv/insn32.decode | 8 +++
target/riscv/insn_trans/trans_rvv.c.inc | 80 +++++++++++++++++++++++++
target/riscv/vector_helper.c | 31 ++++++++++
4 files changed, 133 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index ea6c39b49a8..25c0e2eee28 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1113,3 +1113,17 @@ DEF_HELPER_6(vcompress_vm_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vcompress_vm_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vcompress_vm_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vcompress_vm_d, void, ptr, ptr, ptr, ptr, env, i32)
+
+DEF_HELPER_5(vzext_vf2_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vzext_vf2_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vzext_vf2_d, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vzext_vf4_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vzext_vf4_d, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vzext_vf8_d, void, ptr, ptr, ptr, env, i32)
+
+DEF_HELPER_5(vsext_vf2_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vsext_vf2_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vsext_vf2_d, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vsext_vf4_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vsext_vf4_d, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vsext_vf8_d, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index beef6ca7167..369827ca98f 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -630,5 +630,13 @@ vmv2r_v 100111 1 ..... 00001 011 ..... 1010111 @r2rd
vmv4r_v 100111 1 ..... 00011 011 ..... 1010111 @r2rd
vmv8r_v 100111 1 ..... 00111 011 ..... 1010111 @r2rd
+# Vector Integer Extension
+vzext_vf2 010010 . ..... 00110 010 ..... 1010111 @r2_vm
+vzext_vf4 010010 . ..... 00100 010 ..... 1010111 @r2_vm
+vzext_vf8 010010 . ..... 00010 010 ..... 1010111 @r2_vm
+vsext_vf2 010010 . ..... 00111 010 ..... 1010111 @r2_vm
+vsext_vf4 010010 . ..... 00101 010 ..... 1010111 @r2_vm
+vsext_vf8 010010 . ..... 00011 010 ..... 1010111 @r2_vm
+
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index f92e5c806c8..f3184fb0535 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3514,3 +3514,83 @@ GEN_VMV_WHOLE_TRANS(vmv1r_v, 1)
GEN_VMV_WHOLE_TRANS(vmv2r_v, 2)
GEN_VMV_WHOLE_TRANS(vmv4r_v, 4)
GEN_VMV_WHOLE_TRANS(vmv8r_v, 8)
+
+static bool int_ext_check(DisasContext *s, arg_rmr *a, uint8_t div)
+{
+ uint8_t from = (s->sew + 3) - div;
+ bool ret = require_rvv(s) &&
+ (from >= 3 && from <= 8) &&
+ (a->rd != a->rs2) &&
+ require_align(a->rd, s->lmul) &&
+ require_align(a->rs2, s->lmul - div) &&
+ require_vm(a->vm, a->rd) &&
+ require_noover(a->rd, s->lmul, a->rs2, s->lmul - div);
+ return ret;
+}
+
+static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq)
+{
+ uint32_t data = 0;
+ gen_helper_gvec_3_ptr *fn;
+ TCGLabel *over = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+ static gen_helper_gvec_3_ptr * const fns[6][4] = {
+ {
+ NULL, gen_helper_vzext_vf2_h,
+ gen_helper_vzext_vf2_w, gen_helper_vzext_vf2_d
+ },
+ {
+ NULL, NULL,
+ gen_helper_vzext_vf4_w, gen_helper_vzext_vf4_d,
+ },
+ {
+ NULL, NULL,
+ NULL, gen_helper_vzext_vf8_d
+ },
+ {
+ NULL, gen_helper_vsext_vf2_h,
+ gen_helper_vsext_vf2_w, gen_helper_vsext_vf2_d
+ },
+ {
+ NULL, NULL,
+ gen_helper_vsext_vf4_w, gen_helper_vsext_vf4_d,
+ },
+ {
+ NULL, NULL,
+ NULL, gen_helper_vsext_vf8_d
+ }
+ };
+
+ fn = fns[seq][s->sew];
+ if (fn == NULL) {
+ return false;
+ }
+
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
+
+ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
+ vreg_ofs(s, a->rs2), cpu_env, 0,
+ s->vlen / 8, data, fn);
+
+ mark_vs_dirty(s);
+ gen_set_label(over);
+ return true;
+}
+
+/* Vector Integer Extension */
+#define GEN_INT_EXT_TRANS(NAME, DIV, SEQ) \
+static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
+{ \
+ if (int_ext_check(s, a, DIV)) { \
+ return int_ext_op(s, a, SEQ); \
+ } \
+ return false; \
+}
+
+GEN_INT_EXT_TRANS(vzext_vf2, 1, 0)
+GEN_INT_EXT_TRANS(vzext_vf4, 2, 1)
+GEN_INT_EXT_TRANS(vzext_vf8, 3, 2)
+GEN_INT_EXT_TRANS(vsext_vf2, 1, 3)
+GEN_INT_EXT_TRANS(vsext_vf4, 2, 4)
+GEN_INT_EXT_TRANS(vsext_vf8, 3, 5)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 782fe086f3e..40ef5ab53ae 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4748,3 +4748,34 @@ GEN_VEXT_VCOMPRESS_VM(vcompress_vm_b, uint8_t, H1)
GEN_VEXT_VCOMPRESS_VM(vcompress_vm_h, uint16_t, H2)
GEN_VEXT_VCOMPRESS_VM(vcompress_vm_w, uint32_t, H4)
GEN_VEXT_VCOMPRESS_VM(vcompress_vm_d, uint64_t, H8)
+
+/* Vector Integer Extension */
+#define GEN_VEXT_INT_EXT(NAME, ETYPE, DTYPE, HD, HS1) \
+void HELPER(NAME)(void *vd, void *v0, void *vs2, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ uint32_t vl = env->vl; \
+ uint32_t vm = vext_vm(desc); \
+ uint32_t i; \
+ \
+ for (i = 0; i < vl; i++) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
+ continue; \
+ } \
+ *((ETYPE *)vd + HD(i)) = *((DTYPE *)vs2 + HS1(i)); \
+ } \
+}
+
+GEN_VEXT_INT_EXT(vzext_vf2_h, uint16_t, uint8_t, H2, H1)
+GEN_VEXT_INT_EXT(vzext_vf2_w, uint32_t, uint16_t, H4, H2)
+GEN_VEXT_INT_EXT(vzext_vf2_d, uint64_t, uint32_t, H8, H4)
+GEN_VEXT_INT_EXT(vzext_vf4_w, uint32_t, uint8_t, H4, H1)
+GEN_VEXT_INT_EXT(vzext_vf4_d, uint64_t, uint16_t, H8, H2)
+GEN_VEXT_INT_EXT(vzext_vf8_d, uint64_t, uint8_t, H8, H1)
+
+GEN_VEXT_INT_EXT(vsext_vf2_h, int16_t, int8_t, H2, H1)
+GEN_VEXT_INT_EXT(vsext_vf2_w, int32_t, int16_t, H4, H2)
+GEN_VEXT_INT_EXT(vsext_vf2_d, int64_t, int32_t, H8, H4)
+GEN_VEXT_INT_EXT(vsext_vf4_w, int32_t, int8_t, H4, H1)
+GEN_VEXT_INT_EXT(vsext_vf4_d, int64_t, int16_t, H8, H2)
+GEN_VEXT_INT_EXT(vsext_vf8_d, int64_t, int8_t, H8, H1)
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 40/75] target/riscv: rvv-1.0: single-width averaging add and subtract instructions
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (38 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 39/75] target/riscv: rvv-1.0: integer extension instructions frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 41/75] target/riscv: rvv-1.0: single-width bit shift instructions frank.chang
` (34 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Add the following instructions:
* vaaddu.vv
* vaaddu.vx
* vasubu.vv
* vasubu.vx
Remove the following instructions:
* vadd.vi
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/helper.h | 16 ++++++
target/riscv/insn32.decode | 13 +++--
target/riscv/insn_trans/trans_rvv.c.inc | 5 +-
target/riscv/vector_helper.c | 74 +++++++++++++++++++++++++
4 files changed, 102 insertions(+), 6 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 25c0e2eee28..421bc423c98 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -689,18 +689,34 @@ DEF_HELPER_6(vaadd_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vaadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vaadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vaadd_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vaaddu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vaaddu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vaaddu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vaaddu_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vasub_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vasub_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vasub_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vasub_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vasubu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vasubu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vasubu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vasubu_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vaadd_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vaadd_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vaadd_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vaadd_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vaaddu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vaaddu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vaaddu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vaaddu_vx_d, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vasub_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vasub_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vasub_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vasub_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vasubu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vasubu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vasubu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vasubu_vx_d, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vsmul_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vsmul_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 369827ca98f..1e2508adfb8 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -468,11 +468,14 @@ vssubu_vv 100010 . ..... ..... 000 ..... 1010111 @r_vm
vssubu_vx 100010 . ..... ..... 100 ..... 1010111 @r_vm
vssub_vv 100011 . ..... ..... 000 ..... 1010111 @r_vm
vssub_vx 100011 . ..... ..... 100 ..... 1010111 @r_vm
-vaadd_vv 100100 . ..... ..... 000 ..... 1010111 @r_vm
-vaadd_vx 100100 . ..... ..... 100 ..... 1010111 @r_vm
-vaadd_vi 100100 . ..... ..... 011 ..... 1010111 @r_vm
-vasub_vv 100110 . ..... ..... 000 ..... 1010111 @r_vm
-vasub_vx 100110 . ..... ..... 100 ..... 1010111 @r_vm
+vaadd_vv 001001 . ..... ..... 010 ..... 1010111 @r_vm
+vaadd_vx 001001 . ..... ..... 110 ..... 1010111 @r_vm
+vaaddu_vv 001000 . ..... ..... 010 ..... 1010111 @r_vm
+vaaddu_vx 001000 . ..... ..... 110 ..... 1010111 @r_vm
+vasub_vv 001011 . ..... ..... 010 ..... 1010111 @r_vm
+vasub_vx 001011 . ..... ..... 110 ..... 1010111 @r_vm
+vasubu_vv 001010 . ..... ..... 010 ..... 1010111 @r_vm
+vasubu_vx 001010 . ..... ..... 110 ..... 1010111 @r_vm
vsmul_vv 100111 . ..... ..... 000 ..... 1010111 @r_vm
vsmul_vx 100111 . ..... ..... 100 ..... 1010111 @r_vm
vwsmaccu_vv 111100 . ..... ..... 000 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index f3184fb0535..308c9fa44be 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2237,10 +2237,13 @@ GEN_OPIVI_TRANS(vsadd_vi, IMM_SX, vsadd_vx, opivx_check)
/* Vector Single-Width Averaging Add and Subtract */
GEN_OPIVV_TRANS(vaadd_vv, opivv_check)
+GEN_OPIVV_TRANS(vaaddu_vv, opivv_check)
GEN_OPIVV_TRANS(vasub_vv, opivv_check)
+GEN_OPIVV_TRANS(vasubu_vv, opivv_check)
GEN_OPIVX_TRANS(vaadd_vx, opivx_check)
+GEN_OPIVX_TRANS(vaaddu_vx, opivx_check)
GEN_OPIVX_TRANS(vasub_vx, opivx_check)
-GEN_OPIVI_TRANS(vaadd_vi, 0, vaadd_vx, opivx_check)
+GEN_OPIVX_TRANS(vasubu_vx, opivx_check)
/* Vector Single-Width Fractional Multiply with Rounding and Saturation */
GEN_OPIVV_TRANS(vsmul_vv, opivv_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 40ef5ab53ae..c37d0404113 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -2502,6 +2502,43 @@ GEN_VEXT_VX_RM(vaadd_vx_h, 2, 2)
GEN_VEXT_VX_RM(vaadd_vx_w, 4, 4)
GEN_VEXT_VX_RM(vaadd_vx_d, 8, 8)
+static inline uint32_t aaddu32(CPURISCVState *env, int vxrm,
+ uint32_t a, uint32_t b)
+{
+ uint64_t res = (uint64_t)a + b;
+ uint8_t round = get_round(vxrm, res, 1);
+
+ return (res >> 1) + round;
+}
+
+static inline uint64_t aaddu64(CPURISCVState *env, int vxrm,
+ uint64_t a, uint64_t b)
+{
+ uint64_t res = a + b;
+ uint8_t round = get_round(vxrm, res, 1);
+ uint64_t over = (uint64_t)(res < a) << 63;
+
+ return ((res >> 1) | over) + round;
+}
+
+RVVCALL(OPIVV2_RM, vaaddu_vv_b, OP_UUU_B, H1, H1, H1, aaddu32)
+RVVCALL(OPIVV2_RM, vaaddu_vv_h, OP_UUU_H, H2, H2, H2, aaddu32)
+RVVCALL(OPIVV2_RM, vaaddu_vv_w, OP_UUU_W, H4, H4, H4, aaddu32)
+RVVCALL(OPIVV2_RM, vaaddu_vv_d, OP_UUU_D, H8, H8, H8, aaddu64)
+GEN_VEXT_VV_RM(vaaddu_vv_b, 1, 1)
+GEN_VEXT_VV_RM(vaaddu_vv_h, 2, 2)
+GEN_VEXT_VV_RM(vaaddu_vv_w, 4, 4)
+GEN_VEXT_VV_RM(vaaddu_vv_d, 8, 8)
+
+RVVCALL(OPIVX2_RM, vaaddu_vx_b, OP_UUU_B, H1, H1, aaddu32)
+RVVCALL(OPIVX2_RM, vaaddu_vx_h, OP_UUU_H, H2, H2, aaddu32)
+RVVCALL(OPIVX2_RM, vaaddu_vx_w, OP_UUU_W, H4, H4, aaddu32)
+RVVCALL(OPIVX2_RM, vaaddu_vx_d, OP_UUU_D, H8, H8, aaddu64)
+GEN_VEXT_VX_RM(vaaddu_vx_b, 1, 1)
+GEN_VEXT_VX_RM(vaaddu_vx_h, 2, 2)
+GEN_VEXT_VX_RM(vaaddu_vx_w, 4, 4)
+GEN_VEXT_VX_RM(vaaddu_vx_d, 8, 8)
+
static inline int32_t asub32(CPURISCVState *env, int vxrm, int32_t a, int32_t b)
{
int64_t res = (int64_t)a - b;
@@ -2538,6 +2575,43 @@ GEN_VEXT_VX_RM(vasub_vx_h, 2, 2)
GEN_VEXT_VX_RM(vasub_vx_w, 4, 4)
GEN_VEXT_VX_RM(vasub_vx_d, 8, 8)
+static inline uint32_t asubu32(CPURISCVState *env, int vxrm,
+ uint32_t a, uint32_t b)
+{
+ int64_t res = (int64_t)a - b;
+ uint8_t round = get_round(vxrm, res, 1);
+
+ return (res >> 1) + round;
+}
+
+static inline uint64_t asubu64(CPURISCVState *env, int vxrm,
+ uint64_t a, uint64_t b)
+{
+ uint64_t res = (uint64_t)a - b;
+ uint8_t round = get_round(vxrm, res, 1);
+ uint64_t over = (uint64_t)(res > a) << 63;
+
+ return ((res >> 1) | over) + round;
+}
+
+RVVCALL(OPIVV2_RM, vasubu_vv_b, OP_UUU_B, H1, H1, H1, asubu32)
+RVVCALL(OPIVV2_RM, vasubu_vv_h, OP_UUU_H, H2, H2, H2, asubu32)
+RVVCALL(OPIVV2_RM, vasubu_vv_w, OP_UUU_W, H4, H4, H4, asubu32)
+RVVCALL(OPIVV2_RM, vasubu_vv_d, OP_UUU_D, H8, H8, H8, asubu64)
+GEN_VEXT_VV_RM(vasubu_vv_b, 1, 1)
+GEN_VEXT_VV_RM(vasubu_vv_h, 2, 2)
+GEN_VEXT_VV_RM(vasubu_vv_w, 4, 4)
+GEN_VEXT_VV_RM(vasubu_vv_d, 8, 8)
+
+RVVCALL(OPIVX2_RM, vasubu_vx_b, OP_UUU_B, H1, H1, asubu32)
+RVVCALL(OPIVX2_RM, vasubu_vx_h, OP_UUU_H, H2, H2, asubu32)
+RVVCALL(OPIVX2_RM, vasubu_vx_w, OP_UUU_W, H4, H4, asubu32)
+RVVCALL(OPIVX2_RM, vasubu_vx_d, OP_UUU_D, H8, H8, asubu64)
+GEN_VEXT_VX_RM(vasubu_vx_b, 1, 1)
+GEN_VEXT_VX_RM(vasubu_vx_h, 2, 2)
+GEN_VEXT_VX_RM(vasubu_vx_w, 4, 4)
+GEN_VEXT_VX_RM(vasubu_vx_d, 8, 8)
+
/* Vector Single-Width Fractional Multiply with Rounding and Saturation */
static inline int8_t vsmul8(CPURISCVState *env, int vxrm, int8_t a, int8_t b)
{
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 41/75] target/riscv: rvv-1.0: single-width bit shift instructions
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (39 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 40/75] target/riscv: rvv-1.0: single-width averaging add and subtract instructions frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 42/75] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow frank.chang
` (33 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Truncate vsll.vi, vsrl.vi, vsra.vi's immediate values to lg2(SEW) bits.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvv.c.inc | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 308c9fa44be..91936ec464a 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1915,9 +1915,9 @@ GEN_OPIVX_GVEC_SHIFT_TRANS(vsll_vx, shls)
GEN_OPIVX_GVEC_SHIFT_TRANS(vsrl_vx, shrs)
GEN_OPIVX_GVEC_SHIFT_TRANS(vsra_vx, sars)
-GEN_OPIVI_GVEC_TRANS(vsll_vi, IMM_ZX, vsll_vx, shli)
-GEN_OPIVI_GVEC_TRANS(vsrl_vi, IMM_ZX, vsrl_vx, shri)
-GEN_OPIVI_GVEC_TRANS(vsra_vi, IMM_ZX, vsra_vx, sari)
+GEN_OPIVI_GVEC_TRANS(vsll_vi, IMM_TRUNC_SEW, vsll_vx, shli)
+GEN_OPIVI_GVEC_TRANS(vsrl_vi, IMM_TRUNC_SEW, vsrl_vx, shri)
+GEN_OPIVI_GVEC_TRANS(vsra_vi, IMM_TRUNC_SEW, vsra_vx, sari)
/* Vector Narrowing Integer Right Shift Instructions */
static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a)
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 42/75] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (40 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 41/75] target/riscv: rvv-1.0: single-width bit shift instructions frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 43/75] target/riscv: rvv-1.0: narrowing integer right shift instructions frank.chang
` (32 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
* Only do carry-in or borrow-in if is masked (vm=0).
* Remove clear function from helper functions as the tail elements
are unchanged in RVV 1.0.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 20 ++++++++++----------
target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
target/riscv/vector_helper.c | 20 ++++++--------------
3 files changed, 17 insertions(+), 25 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 1e2508adfb8..2806334a31c 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -353,16 +353,16 @@ vwsubu_wv 110110 . ..... ..... 010 ..... 1010111 @r_vm
vwsubu_wx 110110 . ..... ..... 110 ..... 1010111 @r_vm
vwsub_wv 110111 . ..... ..... 010 ..... 1010111 @r_vm
vwsub_wx 110111 . ..... ..... 110 ..... 1010111 @r_vm
-vadc_vvm 010000 1 ..... ..... 000 ..... 1010111 @r_vm_1
-vadc_vxm 010000 1 ..... ..... 100 ..... 1010111 @r_vm_1
-vadc_vim 010000 1 ..... ..... 011 ..... 1010111 @r_vm_1
-vmadc_vvm 010001 1 ..... ..... 000 ..... 1010111 @r_vm_1
-vmadc_vxm 010001 1 ..... ..... 100 ..... 1010111 @r_vm_1
-vmadc_vim 010001 1 ..... ..... 011 ..... 1010111 @r_vm_1
-vsbc_vvm 010010 1 ..... ..... 000 ..... 1010111 @r_vm_1
-vsbc_vxm 010010 1 ..... ..... 100 ..... 1010111 @r_vm_1
-vmsbc_vvm 010011 1 ..... ..... 000 ..... 1010111 @r_vm_1
-vmsbc_vxm 010011 1 ..... ..... 100 ..... 1010111 @r_vm_1
+vadc_vvm 010000 0 ..... ..... 000 ..... 1010111 @r_vm_1
+vadc_vxm 010000 0 ..... ..... 100 ..... 1010111 @r_vm_1
+vadc_vim 010000 0 ..... ..... 011 ..... 1010111 @r_vm_1
+vmadc_vvm 010001 . ..... ..... 000 ..... 1010111 @r_vm
+vmadc_vxm 010001 . ..... ..... 100 ..... 1010111 @r_vm
+vmadc_vim 010001 . ..... ..... 011 ..... 1010111 @r_vm
+vsbc_vvm 010010 0 ..... ..... 000 ..... 1010111 @r_vm_1
+vsbc_vxm 010010 0 ..... ..... 100 ..... 1010111 @r_vm_1
+vmsbc_vvm 010011 . ..... ..... 000 ..... 1010111 @r_vm
+vmsbc_vxm 010011 . ..... ..... 100 ..... 1010111 @r_vm
vand_vv 001001 . ..... ..... 000 ..... 1010111 @r_vm
vand_vx 001001 . ..... ..... 100 ..... 1010111 @r_vm
vand_vi 001001 . ..... ..... 011 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 91936ec464a..7711f86230c 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1774,7 +1774,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
/*
* For vadc and vsbc, an illegal instruction exception is raised if the
- * destination vector register is v0 and LMUL > 1. (Section 12.3)
+ * destination vector register is v0 and LMUL > 1. (Section 12.4)
*/
static bool opivv_vadc_check(DisasContext *s, arg_rmrr *a)
{
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index c37d0404113..8e122ba41d0 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -1153,7 +1153,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
for (i = 0; i < vl; i++) { \
ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- uint8_t carry = vext_elem_mask(v0, i); \
+ ETYPE carry = vext_elem_mask(v0, i); \
\
*((ETYPE *)vd + H(i)) = DO_OP(s2, s1, carry); \
} \
@@ -1178,7 +1178,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
\
for (i = 0; i < vl; i++) { \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- uint8_t carry = vext_elem_mask(v0, i); \
+ ETYPE carry = vext_elem_mask(v0, i); \
\
*((ETYPE *)vd + H(i)) = DO_OP(s2, (ETYPE)(target_long)s1, carry);\
} \
@@ -1203,19 +1203,15 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
uint32_t vl = env->vl; \
- uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
+ uint32_t vm = vext_vm(desc); \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- uint8_t carry = vext_elem_mask(v0, i); \
- \
+ ETYPE carry = !vm && vext_elem_mask(v0, i); \
vext_set_elem_mask(vd, i, DO_OP(s2, s1, carry)); \
} \
- for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, i, 0); \
- } \
}
GEN_VEXT_VMADC_VVM(vmadc_vvm_b, uint8_t, H1, DO_MADC)
@@ -1233,19 +1229,15 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
void *vs2, CPURISCVState *env, uint32_t desc) \
{ \
uint32_t vl = env->vl; \
- uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(ETYPE))); \
+ uint32_t vm = vext_vm(desc); \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
- uint8_t carry = vext_elem_mask(v0, i); \
- \
+ ETYPE carry = !vm && vext_elem_mask(v0, i); \
vext_set_elem_mask(vd, i, \
DO_OP(s2, (ETYPE)(target_long)s1, carry)); \
} \
- for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, i, 0); \
- } \
}
GEN_VEXT_VMADC_VXM(vmadc_vxm_b, uint8_t, H1, DO_MADC)
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 43/75] target/riscv: rvv-1.0: narrowing integer right shift instructions
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (41 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 42/75] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 44/75] target/riscv: rvv-1.0: widening integer multiply-add instructions frank.chang
` (31 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/helper.h | 24 ++++++++++----------
target/riscv/insn32.decode | 12 +++++-----
target/riscv/insn_trans/trans_rvv.c.inc | 30 ++++++++++++-------------
target/riscv/vector_helper.c | 24 ++++++++++----------
4 files changed, 45 insertions(+), 45 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 421bc423c98..f5f34c2dcdb 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -392,18 +392,18 @@ DEF_HELPER_6(vsra_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vsra_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vsra_vx_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnsrl_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnsrl_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnsrl_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnsra_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnsra_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnsra_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnsrl_vx_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnsrl_vx_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnsrl_vx_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnsra_vx_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnsra_vx_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnsra_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnsrl_wv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnsrl_wv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnsrl_wv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnsra_wv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnsra_wv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnsra_wv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnsrl_wx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnsrl_wx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnsrl_wx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnsra_wx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnsra_wx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnsra_wx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vmseq_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vmseq_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 2806334a31c..022530697ec 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -381,12 +381,12 @@ vsrl_vi 101000 . ..... ..... 011 ..... 1010111 @r_vm
vsra_vv 101001 . ..... ..... 000 ..... 1010111 @r_vm
vsra_vx 101001 . ..... ..... 100 ..... 1010111 @r_vm
vsra_vi 101001 . ..... ..... 011 ..... 1010111 @r_vm
-vnsrl_vv 101100 . ..... ..... 000 ..... 1010111 @r_vm
-vnsrl_vx 101100 . ..... ..... 100 ..... 1010111 @r_vm
-vnsrl_vi 101100 . ..... ..... 011 ..... 1010111 @r_vm
-vnsra_vv 101101 . ..... ..... 000 ..... 1010111 @r_vm
-vnsra_vx 101101 . ..... ..... 100 ..... 1010111 @r_vm
-vnsra_vi 101101 . ..... ..... 011 ..... 1010111 @r_vm
+vnsrl_wv 101100 . ..... ..... 000 ..... 1010111 @r_vm
+vnsrl_wx 101100 . ..... ..... 100 ..... 1010111 @r_vm
+vnsrl_wi 101100 . ..... ..... 011 ..... 1010111 @r_vm
+vnsra_wv 101101 . ..... ..... 000 ..... 1010111 @r_vm
+vnsra_wx 101101 . ..... ..... 100 ..... 1010111 @r_vm
+vnsra_wi 101101 . ..... ..... 011 ..... 1010111 @r_vm
vmseq_vv 011000 . ..... ..... 000 ..... 1010111 @r_vm
vmseq_vx 011000 . ..... ..... 100 ..... 1010111 @r_vm
vmseq_vi 011000 . ..... ..... 011 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 7711f86230c..113a20af4d7 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1920,7 +1920,7 @@ GEN_OPIVI_GVEC_TRANS(vsrl_vi, IMM_TRUNC_SEW, vsrl_vx, shri)
GEN_OPIVI_GVEC_TRANS(vsra_vi, IMM_TRUNC_SEW, vsra_vx, sari)
/* Vector Narrowing Integer Right Shift Instructions */
-static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a)
+static bool opiwv_narrow_check(DisasContext *s, arg_rmrr *a)
{
return require_rvv(s) &&
vext_check_isa_ill(s) &&
@@ -1928,10 +1928,10 @@ static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a)
}
/* OPIVV with NARROW */
-#define GEN_OPIVV_NARROW_TRANS(NAME) \
+#define GEN_OPIWV_NARROW_TRANS(NAME) \
static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
{ \
- if (opivv_narrow_check(s, a)) { \
+ if (opiwv_narrow_check(s, a)) { \
uint32_t data = 0; \
static gen_helper_gvec_4_ptr * const fns[3] = { \
gen_helper_##NAME##_b, \
@@ -1953,10 +1953,10 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
} \
return false; \
}
-GEN_OPIVV_NARROW_TRANS(vnsra_vv)
-GEN_OPIVV_NARROW_TRANS(vnsrl_vv)
+GEN_OPIWV_NARROW_TRANS(vnsra_wv)
+GEN_OPIWV_NARROW_TRANS(vnsrl_wv)
-static bool opivx_narrow_check(DisasContext *s, arg_rmrr *a)
+static bool opiwx_narrow_check(DisasContext *s, arg_rmrr *a)
{
return require_rvv(s) &&
vext_check_isa_ill(s) &&
@@ -1964,10 +1964,10 @@ static bool opivx_narrow_check(DisasContext *s, arg_rmrr *a)
}
/* OPIVX with NARROW */
-#define GEN_OPIVX_NARROW_TRANS(NAME) \
+#define GEN_OPIWX_NARROW_TRANS(NAME) \
static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
{ \
- if (opivx_narrow_check(s, a)) { \
+ if (opiwx_narrow_check(s, a)) { \
static gen_helper_opivx * const fns[3] = { \
gen_helper_##NAME##_b, \
gen_helper_##NAME##_h, \
@@ -1978,14 +1978,14 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
return false; \
}
-GEN_OPIVX_NARROW_TRANS(vnsra_vx)
-GEN_OPIVX_NARROW_TRANS(vnsrl_vx)
+GEN_OPIWX_NARROW_TRANS(vnsra_wx)
+GEN_OPIWX_NARROW_TRANS(vnsrl_wx)
-/* OPIVI with NARROW */
-#define GEN_OPIVI_NARROW_TRANS(NAME, IMM_MODE, OPIVX) \
+/* OPIWI with NARROW */
+#define GEN_OPIWI_NARROW_TRANS(NAME, IMM_MODE, OPIVX) \
static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
{ \
- if (opivx_narrow_check(s, a)) { \
+ if (opiwx_narrow_check(s, a)) { \
static gen_helper_opivx * const fns[3] = { \
gen_helper_##OPIVX##_b, \
gen_helper_##OPIVX##_h, \
@@ -1997,8 +1997,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
return false; \
}
-GEN_OPIVI_NARROW_TRANS(vnsra_vi, IMM_ZX, vnsra_vx)
-GEN_OPIVI_NARROW_TRANS(vnsrl_vi, IMM_ZX, vnsrl_vx)
+GEN_OPIWI_NARROW_TRANS(vnsra_wi, IMM_ZX, vnsra_wx)
+GEN_OPIWI_NARROW_TRANS(vnsrl_wi, IMM_ZX, vnsrl_wx)
/* Vector Integer Comparison Instructions */
/*
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 8e122ba41d0..e14626b40bb 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -1373,18 +1373,18 @@ GEN_VEXT_SHIFT_VX(vsra_vx_w, int32_t, int32_t, H4, H4, DO_SRL, 0x1f)
GEN_VEXT_SHIFT_VX(vsra_vx_d, int64_t, int64_t, H8, H8, DO_SRL, 0x3f)
/* Vector Narrowing Integer Right Shift Instructions */
-GEN_VEXT_SHIFT_VV(vnsrl_vv_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf)
-GEN_VEXT_SHIFT_VV(vnsrl_vv_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f)
-GEN_VEXT_SHIFT_VV(vnsrl_vv_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f)
-GEN_VEXT_SHIFT_VV(vnsra_vv_b, uint8_t, int16_t, H1, H2, DO_SRL, 0xf)
-GEN_VEXT_SHIFT_VV(vnsra_vv_h, uint16_t, int32_t, H2, H4, DO_SRL, 0x1f)
-GEN_VEXT_SHIFT_VV(vnsra_vv_w, uint32_t, int64_t, H4, H8, DO_SRL, 0x3f)
-GEN_VEXT_SHIFT_VX(vnsrl_vx_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf)
-GEN_VEXT_SHIFT_VX(vnsrl_vx_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f)
-GEN_VEXT_SHIFT_VX(vnsrl_vx_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f)
-GEN_VEXT_SHIFT_VX(vnsra_vx_b, int8_t, int16_t, H1, H2, DO_SRL, 0xf)
-GEN_VEXT_SHIFT_VX(vnsra_vx_h, int16_t, int32_t, H2, H4, DO_SRL, 0x1f)
-GEN_VEXT_SHIFT_VX(vnsra_vx_w, int32_t, int64_t, H4, H8, DO_SRL, 0x3f)
+GEN_VEXT_SHIFT_VV(vnsrl_wv_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf)
+GEN_VEXT_SHIFT_VV(vnsrl_wv_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f)
+GEN_VEXT_SHIFT_VV(vnsrl_wv_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f)
+GEN_VEXT_SHIFT_VV(vnsra_wv_b, uint8_t, int16_t, H1, H2, DO_SRL, 0xf)
+GEN_VEXT_SHIFT_VV(vnsra_wv_h, uint16_t, int32_t, H2, H4, DO_SRL, 0x1f)
+GEN_VEXT_SHIFT_VV(vnsra_wv_w, uint32_t, int64_t, H4, H8, DO_SRL, 0x3f)
+GEN_VEXT_SHIFT_VX(vnsrl_wx_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf)
+GEN_VEXT_SHIFT_VX(vnsrl_wx_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f)
+GEN_VEXT_SHIFT_VX(vnsrl_wx_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f)
+GEN_VEXT_SHIFT_VX(vnsra_wx_b, int8_t, int16_t, H1, H2, DO_SRL, 0xf)
+GEN_VEXT_SHIFT_VX(vnsra_wx_h, int16_t, int32_t, H2, H4, DO_SRL, 0x1f)
+GEN_VEXT_SHIFT_VX(vnsra_wx_w, int32_t, int64_t, H4, H8, DO_SRL, 0x3f)
/* Vector Integer Comparison Instructions */
#define DO_MSEQ(N, M) (N == M)
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 44/75] target/riscv: rvv-1.0: widening integer multiply-add instructions
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (42 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 43/75] target/riscv: rvv-1.0: narrowing integer right shift instructions frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 45/75] target/riscv: rvv-1.0: single-width saturating add and subtract instructions frank.chang
` (30 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Alistair Francis, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn32.decode | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 022530697ec..8467dfc84b1 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -449,9 +449,9 @@ vwmaccu_vv 111100 . ..... ..... 010 ..... 1010111 @r_vm
vwmaccu_vx 111100 . ..... ..... 110 ..... 1010111 @r_vm
vwmacc_vv 111101 . ..... ..... 010 ..... 1010111 @r_vm
vwmacc_vx 111101 . ..... ..... 110 ..... 1010111 @r_vm
-vwmaccsu_vv 111110 . ..... ..... 010 ..... 1010111 @r_vm
-vwmaccsu_vx 111110 . ..... ..... 110 ..... 1010111 @r_vm
-vwmaccus_vx 111111 . ..... ..... 110 ..... 1010111 @r_vm
+vwmaccsu_vv 111111 . ..... ..... 010 ..... 1010111 @r_vm
+vwmaccsu_vx 111111 . ..... ..... 110 ..... 1010111 @r_vm
+vwmaccus_vx 111110 . ..... ..... 110 ..... 1010111 @r_vm
vmv_v_v 010111 1 00000 ..... 000 ..... 1010111 @r2
vmv_v_x 010111 1 00000 ..... 100 ..... 1010111 @r2
vmv_v_i 010111 1 00000 ..... 011 ..... 1010111 @r2
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 45/75] target/riscv: rvv-1.0: single-width saturating add and subtract instructions
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (43 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 44/75] target/riscv: rvv-1.0: widening integer multiply-add instructions frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 46/75] target/riscv: rvv-1.0: integer comparison instructions frank.chang
` (29 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Sign-extend vsaddu.vi immediate value.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 113a20af4d7..39e2d21da5e 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2232,7 +2232,7 @@ GEN_OPIVX_TRANS(vsaddu_vx, opivx_check)
GEN_OPIVX_TRANS(vsadd_vx, opivx_check)
GEN_OPIVX_TRANS(vssubu_vx, opivx_check)
GEN_OPIVX_TRANS(vssub_vx, opivx_check)
-GEN_OPIVI_TRANS(vsaddu_vi, IMM_ZX, vsaddu_vx, opivx_check)
+GEN_OPIVI_TRANS(vsaddu_vi, IMM_SX, vsaddu_vx, opivx_check)
GEN_OPIVI_TRANS(vsadd_vi, IMM_SX, vsadd_vx, opivx_check)
/* Vector Single-Width Averaging Add and Subtract */
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 46/75] target/riscv: rvv-1.0: integer comparison instructions
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (44 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 45/75] target/riscv: rvv-1.0: single-width saturating add and subtract instructions frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 47/75] target/riscv: rvv-1.0: floating-point compare instructions frank.chang
` (28 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
* Sign-extend vmselu.vi and vmsgtu.vi immediate values.
* Remove "set tail elements to zeros" as tail elements can be unchanged
for either VTA to have undisturbed or agnostic setting.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
target/riscv/vector_helper.c | 8 --------
2 files changed, 2 insertions(+), 10 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 39e2d21da5e..523c6cf7f6d 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2038,9 +2038,9 @@ GEN_OPIVX_TRANS(vmsgt_vx, opivx_cmp_check)
GEN_OPIVI_TRANS(vmseq_vi, IMM_SX, vmseq_vx, opivx_cmp_check)
GEN_OPIVI_TRANS(vmsne_vi, IMM_SX, vmsne_vx, opivx_cmp_check)
-GEN_OPIVI_TRANS(vmsleu_vi, IMM_ZX, vmsleu_vx, opivx_cmp_check)
+GEN_OPIVI_TRANS(vmsleu_vi, IMM_SX, vmsleu_vx, opivx_cmp_check)
GEN_OPIVI_TRANS(vmsle_vi, IMM_SX, vmsle_vx, opivx_cmp_check)
-GEN_OPIVI_TRANS(vmsgtu_vi, IMM_ZX, vmsgtu_vx, opivx_cmp_check)
+GEN_OPIVI_TRANS(vmsgtu_vi, IMM_SX, vmsgtu_vx, opivx_cmp_check)
GEN_OPIVI_TRANS(vmsgt_vi, IMM_SX, vmsgt_vx, opivx_cmp_check)
/* Vector Integer Min/Max Instructions */
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index e14626b40bb..5622fb23f85 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -1399,7 +1399,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
- uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
@@ -1410,9 +1409,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
} \
vext_set_elem_mask(vd, i, DO_OP(s2, s1)); \
} \
- for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, i, 0); \
- } \
}
GEN_VEXT_CMP_VV(vmseq_vv_b, uint8_t, H1, DO_MSEQ)
@@ -1451,7 +1447,6 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
- uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
@@ -1462,9 +1457,6 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
vext_set_elem_mask(vd, i, \
DO_OP(s2, (ETYPE)(target_long)s1)); \
} \
- for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, i, 0); \
- } \
}
GEN_VEXT_CMP_VX(vmseq_vx_b, uint8_t, H1, DO_MSEQ)
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 47/75] target/riscv: rvv-1.0: floating-point compare instructions
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (45 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 46/75] target/riscv: rvv-1.0: integer comparison instructions frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 48/75] target/riscv: rvv-1.0: mask-register logical instructions frank.chang
` (27 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Alistair Francis, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/vector_helper.c | 8 --------
1 file changed, 8 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 5622fb23f85..93ed6f54e99 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -3919,7 +3919,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
- uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
@@ -3931,9 +3930,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
vext_set_elem_mask(vd, i, \
DO_OP(s2, s1, &env->fp_status)); \
} \
- for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, i, 0); \
- } \
}
GEN_VEXT_CMP_VV_ENV(vmfeq_vv_h, uint16_t, H2, float16_eq_quiet)
@@ -3946,7 +3942,6 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
- uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(ETYPE))); \
uint32_t i; \
\
for (i = 0; i < vl; i++) { \
@@ -3957,9 +3952,6 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
vext_set_elem_mask(vd, i, \
DO_OP(s2, (ETYPE)s1, &env->fp_status)); \
} \
- for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, i, 0); \
- } \
}
GEN_VEXT_CMP_VF(vmfeq_vf_h, uint16_t, H2, float16_eq_quiet)
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 48/75] target/riscv: rvv-1.0: mask-register logical instructions
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (46 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 47/75] target/riscv: rvv-1.0: floating-point compare instructions frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 49/75] target/riscv: rvv-1.0: slide instructions frank.chang
` (26 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
target/riscv/vector_helper.c | 4 ----
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 523c6cf7f6d..8386f4f2aa8 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2881,7 +2881,8 @@ GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check)
#define GEN_MM_TRANS(NAME) \
static bool trans_##NAME(DisasContext *s, arg_r *a) \
{ \
- if (vext_check_isa_ill(s)) { \
+ if (require_rvv(s) && \
+ vext_check_isa_ill(s)) { \
uint32_t data = 0; \
gen_helper_gvec_4_ptr *fn = gen_helper_##NAME; \
TCGLabel *over = gen_new_label(); \
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 93ed6f54e99..a2ef6b708c8 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4440,7 +4440,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
void *vs2, CPURISCVState *env, \
uint32_t desc) \
{ \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
uint32_t vl = env->vl; \
uint32_t i; \
int a, b; \
@@ -4450,9 +4449,6 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
b = vext_elem_mask(vs2, i); \
vext_set_elem_mask(vd, i, OP(b, a)); \
} \
- for (; i < vlmax; i++) { \
- vext_set_elem_mask(vd, i, 0); \
- } \
}
#define DO_NAND(N, M) (!(N & M))
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 49/75] target/riscv: rvv-1.0: slide instructions
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (47 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 48/75] target/riscv: rvv-1.0: mask-register logical instructions frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 50/75] target/riscv: rvv-1.0: floating-point " frank.chang
` (25 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Alistair Francis, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
* Remove clear function from helper functions as the tail elements
are unchanged in RVV 1.0.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/vector_helper.c | 19 ++++++++++++-------
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index a2ef6b708c8..fac387353fb 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4639,17 +4639,22 @@ GEN_VEXT_VSLIDEUP_VX(vslideup_vx_d, uint64_t, H8)
void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t vlmax = env_archcpu(env)->cfg.vlen; \
+ uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(ETYPE))); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
- target_ulong offset = s1, i; \
+ target_ulong i_max, i; \
\
- for (i = 0; i < vl; ++i) { \
- target_ulong j = i + offset; \
- if (!vm && !vext_elem_mask(v0, i)) { \
- continue; \
+ i_max = MIN(s1 < vlmax ? vlmax - s1 : 0, vl); \
+ for (i = 0; i < i_max; ++i) { \
+ if (vm || vext_elem_mask(v0, i)) { \
+ *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i + s1)); \
+ } \
+ } \
+ \
+ for (i = i_max; i < vl; ++i) { \
+ if (vm || vext_elem_mask(v0, i)) { \
+ *((ETYPE *)vd + H(i)) = 0; \
} \
- *((ETYPE *)vd + H(i)) = j >= vlmax ? 0 : *((ETYPE *)vs2 + H(j)); \
} \
}
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 50/75] target/riscv: rvv-1.0: floating-point slide instructions
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (48 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 49/75] target/riscv: rvv-1.0: slide instructions frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 51/75] target/riscv: rvv-1.0: narrowing fixed-point clip instructions frank.chang
` (24 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Add the following instructions:
* vfslide1up.vf
* vfslide1down.vf
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 7 ++
target/riscv/insn32.decode | 2 +
target/riscv/insn_trans/trans_rvv.c.inc | 16 +++
target/riscv/vector_helper.c | 141 ++++++++++++++++--------
4 files changed, 121 insertions(+), 45 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index f5f34c2dcdb..1e1e35bf800 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1112,6 +1112,13 @@ DEF_HELPER_6(vslide1down_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vslide1down_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vslide1down_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vfslide1up_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfslide1up_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfslide1up_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfslide1down_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfslide1down_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfslide1down_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+
DEF_HELPER_6(vrgather_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vrgather_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vrgather_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 8467dfc84b1..06e4e4f74b4 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -552,6 +552,8 @@ vfsgnjn_vv 001001 . ..... ..... 001 ..... 1010111 @r_vm
vfsgnjn_vf 001001 . ..... ..... 101 ..... 1010111 @r_vm
vfsgnjx_vv 001010 . ..... ..... 001 ..... 1010111 @r_vm
vfsgnjx_vf 001010 . ..... ..... 101 ..... 1010111 @r_vm
+vfslide1up_vf 001110 . ..... ..... 101 ..... 1010111 @r_vm
+vfslide1down_vf 001111 . ..... ..... 101 ..... 1010111 @r_vm
vmfeq_vv 011000 . ..... ..... 001 ..... 1010111 @r_vm
vmfeq_vf 011000 . ..... ..... 101 ..... 1010111 @r_vm
vmfne_vv 011100 . ..... ..... 001 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 8386f4f2aa8..26652f044f8 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3357,6 +3357,22 @@ GEN_OPIVX_TRANS(vslidedown_vx, slidedown_check)
GEN_OPIVX_TRANS(vslide1down_vx, slidedown_check)
GEN_OPIVI_TRANS(vslidedown_vi, IMM_ZX, vslidedown_vx, slidedown_check)
+/* Vector Floating-Point Slide Instructions */
+static bool fslideup_check(DisasContext *s, arg_rmrr *a)
+{
+ return slideup_check(s, a) &&
+ require_rvf(s);
+}
+
+static bool fslidedown_check(DisasContext *s, arg_rmrr *a)
+{
+ return slidedown_check(s, a) &&
+ require_rvf(s);
+}
+
+GEN_OPFVF_TRANS(vfslide1up_vf, fslideup_check)
+GEN_OPFVF_TRANS(vfslide1down_vf, fslidedown_check)
+
/* Vector Register Gather Instruction */
static bool vrgather_vv_check(DisasContext *s, arg_rmrr *a)
{
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index fac387353fb..df4f0b2d6a7 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4664,57 +4664,108 @@ GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_h, uint16_t, H2)
GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_w, uint32_t, H4)
GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_d, uint64_t, H8)
-#define GEN_VEXT_VSLIDE1UP_VX(NAME, ETYPE, H) \
-void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
- CPURISCVState *env, uint32_t desc) \
-{ \
- uint32_t vm = vext_vm(desc); \
- uint32_t vl = env->vl; \
- uint32_t i; \
- \
- for (i = 0; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, i)) { \
- continue; \
- } \
- if (i == 0) { \
- *((ETYPE *)vd + H(i)) = s1; \
- } else { \
- *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - 1)); \
- } \
- } \
+#define GEN_VEXT_VSLIE1UP(ESZ, H) \
+static void vslide1up_##ESZ(void *vd, void *v0, target_ulong s1, void *vs2, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ typedef uint##ESZ##_t ETYPE; \
+ uint32_t vm = vext_vm(desc); \
+ uint32_t vl = env->vl; \
+ uint32_t i; \
+ \
+ for (i = 0; i < vl; i++) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
+ continue; \
+ } \
+ if (i == 0) { \
+ *((ETYPE *)vd + H(i)) = s1; \
+ } else { \
+ *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - 1)); \
+ } \
+ } \
+}
+
+GEN_VEXT_VSLIE1UP(8, H1)
+GEN_VEXT_VSLIE1UP(16, H2)
+GEN_VEXT_VSLIE1UP(32, H4)
+GEN_VEXT_VSLIE1UP(64, H8)
+
+#define GEN_VEXT_VSLIDE1UP_VX(NAME, ESZ) \
+void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ vslide1up_##ESZ(vd, v0, s1, vs2, env, desc); \
}
/* vslide1up.vx vd, vs2, rs1, vm # vd[0]=x[rs1], vd[i+1] = vs2[i] */
-GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_b, uint8_t, H1)
-GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_h, uint16_t, H2)
-GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_w, uint32_t, H4)
-GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, uint64_t, H8)
-
-#define GEN_VEXT_VSLIDE1DOWN_VX(NAME, ETYPE, H) \
-void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
- CPURISCVState *env, uint32_t desc) \
-{ \
- uint32_t vm = vext_vm(desc); \
- uint32_t vl = env->vl; \
- uint32_t i; \
- \
- for (i = 0; i < vl; i++) { \
- if (!vm && !vext_elem_mask(v0, i)) { \
- continue; \
- } \
- if (i == vl - 1) { \
- *((ETYPE *)vd + H(i)) = s1; \
- } else { \
- *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i + 1)); \
- } \
- } \
+GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_b, 8)
+GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_h, 16)
+GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_w, 32)
+GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, 64)
+
+#define GEN_VEXT_VSLIDE1DOWN(ESZ, H) \
+static void vslide1down_##ESZ(void *vd, void *v0, target_ulong s1, void *vs2, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ typedef uint##ESZ##_t ETYPE; \
+ uint32_t vm = vext_vm(desc); \
+ uint32_t vl = env->vl; \
+ uint32_t i; \
+ \
+ for (i = 0; i < vl; i++) { \
+ if (!vm && !vext_elem_mask(v0, i)) { \
+ continue; \
+ } \
+ if (i == vl - 1) { \
+ *((ETYPE *)vd + H(i)) = s1; \
+ } else { \
+ *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i + 1)); \
+ } \
+ } \
+}
+
+GEN_VEXT_VSLIDE1DOWN(8, H1)
+GEN_VEXT_VSLIDE1DOWN(16, H2)
+GEN_VEXT_VSLIDE1DOWN(32, H4)
+GEN_VEXT_VSLIDE1DOWN(64, H8)
+
+#define GEN_VEXT_VSLIDE1DOWN_VX(NAME, ESZ) \
+void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ vslide1down_##ESZ(vd, v0, s1, vs2, env, desc); \
}
/* vslide1down.vx vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=x[rs1] */
-GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_b, uint8_t, H1)
-GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_h, uint16_t, H2)
-GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_w, uint32_t, H4)
-GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, uint64_t, H8)
+GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_b, 8)
+GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_h, 16)
+GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_w, 32)
+GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, 64)
+
+/* Vector Floating-Point Slide Instructions */
+#define GEN_VEXT_VFSLIDE1UP_VF(NAME, ESZ) \
+void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ vslide1up_##ESZ(vd, v0, s1, vs2, env, desc); \
+}
+
+/* vfslide1up.vf vd, vs2, rs1, vm # vd[0]=f[rs1], vd[i+1] = vs2[i] */
+GEN_VEXT_VFSLIDE1UP_VF(vfslide1up_vf_h, 16)
+GEN_VEXT_VFSLIDE1UP_VF(vfslide1up_vf_w, 32)
+GEN_VEXT_VFSLIDE1UP_VF(vfslide1up_vf_d, 64)
+
+#define GEN_VEXT_VFSLIDE1DOWN_VF(NAME, ESZ) \
+void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ vslide1down_##ESZ(vd, v0, s1, vs2, env, desc); \
+}
+
+/* vfslide1down.vf vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=f[rs1] */
+GEN_VEXT_VFSLIDE1DOWN_VF(vfslide1down_vf_h, 16)
+GEN_VEXT_VFSLIDE1DOWN_VF(vfslide1down_vf_w, 32)
+GEN_VEXT_VFSLIDE1DOWN_VF(vfslide1down_vf_d, 64)
/* Vector Register Gather Instruction */
#define GEN_VEXT_VRGATHER_VV(NAME, TS1, TS2, HS1, HS2) \
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 51/75] target/riscv: rvv-1.0: narrowing fixed-point clip instructions
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (49 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 50/75] target/riscv: rvv-1.0: floating-point " frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 52/75] target/riscv: rvv-1.0: single-width floating-point reduction frank.chang
` (23 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/helper.h | 24 ++++++------
target/riscv/insn32.decode | 12 +++---
target/riscv/insn_trans/trans_rvv.c.inc | 12 +++---
target/riscv/vector_helper.c | 52 ++++++++++++-------------
4 files changed, 50 insertions(+), 50 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 1e1e35bf800..2e4ed26f89c 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -766,18 +766,18 @@ DEF_HELPER_6(vssra_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vssra_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vssra_vx_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnclip_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnclip_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnclip_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnclipu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnclipu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnclipu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vnclipu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnclipu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnclipu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnclip_vx_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnclip_vx_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vnclip_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnclip_wv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnclip_wv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnclip_wv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnclipu_wv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnclipu_wv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnclipu_wv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnclipu_wx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnclipu_wx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnclipu_wx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnclip_wx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnclip_wx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnclip_wx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vfadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 06e4e4f74b4..ac1bcab9627 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -491,12 +491,12 @@ vssrl_vi 101010 . ..... ..... 011 ..... 1010111 @r_vm
vssra_vv 101011 . ..... ..... 000 ..... 1010111 @r_vm
vssra_vx 101011 . ..... ..... 100 ..... 1010111 @r_vm
vssra_vi 101011 . ..... ..... 011 ..... 1010111 @r_vm
-vnclipu_vv 101110 . ..... ..... 000 ..... 1010111 @r_vm
-vnclipu_vx 101110 . ..... ..... 100 ..... 1010111 @r_vm
-vnclipu_vi 101110 . ..... ..... 011 ..... 1010111 @r_vm
-vnclip_vv 101111 . ..... ..... 000 ..... 1010111 @r_vm
-vnclip_vx 101111 . ..... ..... 100 ..... 1010111 @r_vm
-vnclip_vi 101111 . ..... ..... 011 ..... 1010111 @r_vm
+vnclipu_wv 101110 . ..... ..... 000 ..... 1010111 @r_vm
+vnclipu_wx 101110 . ..... ..... 100 ..... 1010111 @r_vm
+vnclipu_wi 101110 . ..... ..... 011 ..... 1010111 @r_vm
+vnclip_wv 101111 . ..... ..... 000 ..... 1010111 @r_vm
+vnclip_wx 101111 . ..... ..... 100 ..... 1010111 @r_vm
+vnclip_wi 101111 . ..... ..... 011 ..... 1010111 @r_vm
vfadd_vv 000000 . ..... ..... 001 ..... 1010111 @r_vm
vfadd_vf 000000 . ..... ..... 101 ..... 1010111 @r_vm
vfsub_vv 000010 . ..... ..... 001 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 26652f044f8..731c4bdd04b 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2267,12 +2267,12 @@ GEN_OPIVI_TRANS(vssrl_vi, IMM_ZX, vssrl_vx, opivx_check)
GEN_OPIVI_TRANS(vssra_vi, IMM_SX, vssra_vx, opivx_check)
/* Vector Narrowing Fixed-Point Clip Instructions */
-GEN_OPIVV_NARROW_TRANS(vnclipu_vv)
-GEN_OPIVV_NARROW_TRANS(vnclip_vv)
-GEN_OPIVX_NARROW_TRANS(vnclipu_vx)
-GEN_OPIVX_NARROW_TRANS(vnclip_vx)
-GEN_OPIVI_NARROW_TRANS(vnclipu_vi, IMM_ZX, vnclipu_vx)
-GEN_OPIVI_NARROW_TRANS(vnclip_vi, IMM_ZX, vnclip_vx)
+GEN_OPIWV_NARROW_TRANS(vnclipu_wv)
+GEN_OPIWV_NARROW_TRANS(vnclip_wv)
+GEN_OPIWX_NARROW_TRANS(vnclipu_wx)
+GEN_OPIWX_NARROW_TRANS(vnclip_wx)
+GEN_OPIWI_NARROW_TRANS(vnclipu_wi, IMM_ZX, vnclipu_wx)
+GEN_OPIWI_NARROW_TRANS(vnclip_wi, IMM_ZX, vnclip_wx)
/*
*** Vector Float Point Arithmetic Instructions
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index df4f0b2d6a7..c5048882e91 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -3084,19 +3084,19 @@ vnclip32(CPURISCVState *env, int vxrm, int64_t a, int32_t b)
}
}
-RVVCALL(OPIVV2_RM, vnclip_vv_b, NOP_SSS_B, H1, H2, H1, vnclip8)
-RVVCALL(OPIVV2_RM, vnclip_vv_h, NOP_SSS_H, H2, H4, H2, vnclip16)
-RVVCALL(OPIVV2_RM, vnclip_vv_w, NOP_SSS_W, H4, H8, H4, vnclip32)
-GEN_VEXT_VV_RM(vnclip_vv_b, 1, 1)
-GEN_VEXT_VV_RM(vnclip_vv_h, 2, 2)
-GEN_VEXT_VV_RM(vnclip_vv_w, 4, 4)
-
-RVVCALL(OPIVX2_RM, vnclip_vx_b, NOP_SSS_B, H1, H2, vnclip8)
-RVVCALL(OPIVX2_RM, vnclip_vx_h, NOP_SSS_H, H2, H4, vnclip16)
-RVVCALL(OPIVX2_RM, vnclip_vx_w, NOP_SSS_W, H4, H8, vnclip32)
-GEN_VEXT_VX_RM(vnclip_vx_b, 1, 1)
-GEN_VEXT_VX_RM(vnclip_vx_h, 2, 2)
-GEN_VEXT_VX_RM(vnclip_vx_w, 4, 4)
+RVVCALL(OPIVV2_RM, vnclip_wv_b, NOP_SSS_B, H1, H2, H1, vnclip8)
+RVVCALL(OPIVV2_RM, vnclip_wv_h, NOP_SSS_H, H2, H4, H2, vnclip16)
+RVVCALL(OPIVV2_RM, vnclip_wv_w, NOP_SSS_W, H4, H8, H4, vnclip32)
+GEN_VEXT_VV_RM(vnclip_wv_b, 1, 1)
+GEN_VEXT_VV_RM(vnclip_wv_h, 2, 2)
+GEN_VEXT_VV_RM(vnclip_wv_w, 4, 4)
+
+RVVCALL(OPIVX2_RM, vnclip_wx_b, NOP_SSS_B, H1, H2, vnclip8)
+RVVCALL(OPIVX2_RM, vnclip_wx_h, NOP_SSS_H, H2, H4, vnclip16)
+RVVCALL(OPIVX2_RM, vnclip_wx_w, NOP_SSS_W, H4, H8, vnclip32)
+GEN_VEXT_VX_RM(vnclip_wx_b, 1, 1)
+GEN_VEXT_VX_RM(vnclip_wx_h, 2, 2)
+GEN_VEXT_VX_RM(vnclip_wx_w, 4, 4)
static inline uint8_t
vnclipu8(CPURISCVState *env, int vxrm, uint16_t a, uint8_t b)
@@ -3134,7 +3134,7 @@ static inline uint32_t
vnclipu32(CPURISCVState *env, int vxrm, uint64_t a, uint32_t b)
{
uint8_t round, shift = b & 0x3f;
- int64_t res;
+ uint64_t res;
round = get_round(vxrm, a, shift);
res = (a >> shift) + round;
@@ -3146,19 +3146,19 @@ vnclipu32(CPURISCVState *env, int vxrm, uint64_t a, uint32_t b)
}
}
-RVVCALL(OPIVV2_RM, vnclipu_vv_b, NOP_UUU_B, H1, H2, H1, vnclipu8)
-RVVCALL(OPIVV2_RM, vnclipu_vv_h, NOP_UUU_H, H2, H4, H2, vnclipu16)
-RVVCALL(OPIVV2_RM, vnclipu_vv_w, NOP_UUU_W, H4, H8, H4, vnclipu32)
-GEN_VEXT_VV_RM(vnclipu_vv_b, 1, 1)
-GEN_VEXT_VV_RM(vnclipu_vv_h, 2, 2)
-GEN_VEXT_VV_RM(vnclipu_vv_w, 4, 4)
+RVVCALL(OPIVV2_RM, vnclipu_wv_b, NOP_UUU_B, H1, H2, H1, vnclipu8)
+RVVCALL(OPIVV2_RM, vnclipu_wv_h, NOP_UUU_H, H2, H4, H2, vnclipu16)
+RVVCALL(OPIVV2_RM, vnclipu_wv_w, NOP_UUU_W, H4, H8, H4, vnclipu32)
+GEN_VEXT_VV_RM(vnclipu_wv_b, 1, 1)
+GEN_VEXT_VV_RM(vnclipu_wv_h, 2, 2)
+GEN_VEXT_VV_RM(vnclipu_wv_w, 4, 4)
-RVVCALL(OPIVX2_RM, vnclipu_vx_b, NOP_UUU_B, H1, H2, vnclipu8)
-RVVCALL(OPIVX2_RM, vnclipu_vx_h, NOP_UUU_H, H2, H4, vnclipu16)
-RVVCALL(OPIVX2_RM, vnclipu_vx_w, NOP_UUU_W, H4, H8, vnclipu32)
-GEN_VEXT_VX_RM(vnclipu_vx_b, 1, 1)
-GEN_VEXT_VX_RM(vnclipu_vx_h, 2, 2)
-GEN_VEXT_VX_RM(vnclipu_vx_w, 4, 4)
+RVVCALL(OPIVX2_RM, vnclipu_wx_b, NOP_UUU_B, H1, H2, vnclipu8)
+RVVCALL(OPIVX2_RM, vnclipu_wx_h, NOP_UUU_H, H2, H4, vnclipu16)
+RVVCALL(OPIVX2_RM, vnclipu_wx_w, NOP_UUU_W, H4, H8, vnclipu32)
+GEN_VEXT_VX_RM(vnclipu_wx_b, 1, 1)
+GEN_VEXT_VX_RM(vnclipu_wx_h, 2, 2)
+GEN_VEXT_VX_RM(vnclipu_wx_w, 4, 4)
/*
*** Vector Float Point Arithmetic Instructions
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 52/75] target/riscv: rvv-1.0: single-width floating-point reduction
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (50 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 51/75] target/riscv: rvv-1.0: narrowing fixed-point clip instructions frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 53/75] target/riscv: rvv-1.0: widening floating-point reduction instructions frank.chang
` (22 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvv.c.inc | 12 +++++++++---
target/riscv/vector_helper.c | 12 ++++++------
2 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 731c4bdd04b..c4ccccb0370 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2866,9 +2866,15 @@ GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_widen_check)
GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_widen_check)
/* Vector Single-Width Floating-Point Reduction Instructions */
-GEN_OPFVV_TRANS(vfredsum_vs, reduction_check)
-GEN_OPFVV_TRANS(vfredmax_vs, reduction_check)
-GEN_OPFVV_TRANS(vfredmin_vs, reduction_check)
+static bool freduction_check(DisasContext *s, arg_rmrr *a)
+{
+ return reduction_check(s, a) &&
+ require_rvf(s);
+}
+
+GEN_OPFVV_TRANS(vfredsum_vs, freduction_check)
+GEN_OPFVV_TRANS(vfredmax_vs, freduction_check)
+GEN_OPFVV_TRANS(vfredmin_vs, freduction_check)
/* Vector Widening Floating-Point Reduction Instructions */
GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index c5048882e91..e6931466d40 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4382,14 +4382,14 @@ GEN_VEXT_FRED(vfredsum_vs_w, uint32_t, uint32_t, H4, H4, float32_add)
GEN_VEXT_FRED(vfredsum_vs_d, uint64_t, uint64_t, H8, H8, float64_add)
/* Maximum value */
-GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2, float16_maxnum)
-GEN_VEXT_FRED(vfredmax_vs_w, uint32_t, uint32_t, H4, H4, float32_maxnum)
-GEN_VEXT_FRED(vfredmax_vs_d, uint64_t, uint64_t, H8, H8, float64_maxnum)
+GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2, float16_maxnum_noprop)
+GEN_VEXT_FRED(vfredmax_vs_w, uint32_t, uint32_t, H4, H4, float32_maxnum_noprop)
+GEN_VEXT_FRED(vfredmax_vs_d, uint64_t, uint64_t, H8, H8, float64_maxnum_noprop)
/* Minimum value */
-GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2, float16_minnum)
-GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4, float32_minnum)
-GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, float64_minnum)
+GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2, float16_minnum_noprop)
+GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4, float32_minnum_noprop)
+GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, float64_minnum_noprop)
/* Vector Widening Floating-Point Reduction Instructions */
/* Unordered reduce 2*SEW = 2*SEW + sum(promote(SEW)) */
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 53/75] target/riscv: rvv-1.0: widening floating-point reduction instructions
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (51 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 52/75] target/riscv: rvv-1.0: single-width floating-point reduction frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 54/75] target/riscv: rvv-1.0: single-width scaling shift instructions frank.chang
` (21 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvv.c.inc | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index c4ccccb0370..49889a7706b 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2877,7 +2877,14 @@ GEN_OPFVV_TRANS(vfredmax_vs, freduction_check)
GEN_OPFVV_TRANS(vfredmin_vs, freduction_check)
/* Vector Widening Floating-Point Reduction Instructions */
-GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check)
+static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
+{
+ return reduction_widen_check(s, a) &&
+ require_scale_rvf(s) &&
+ (s->sew != MO_8);
+}
+
+GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, freduction_widen_check)
/*
*** Vector Mask Operations
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 54/75] target/riscv: rvv-1.0: single-width scaling shift instructions
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (52 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 53/75] target/riscv: rvv-1.0: widening floating-point reduction instructions frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 55/75] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add frank.chang
` (20 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
log(SEW) truncate vssra.vi immediate value.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 49889a7706b..2188e92064f 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2263,8 +2263,8 @@ GEN_OPIVV_TRANS(vssrl_vv, opivv_check)
GEN_OPIVV_TRANS(vssra_vv, opivv_check)
GEN_OPIVX_TRANS(vssrl_vx, opivx_check)
GEN_OPIVX_TRANS(vssra_vx, opivx_check)
-GEN_OPIVI_TRANS(vssrl_vi, IMM_ZX, vssrl_vx, opivx_check)
-GEN_OPIVI_TRANS(vssra_vi, IMM_SX, vssra_vx, opivx_check)
+GEN_OPIVI_TRANS(vssrl_vi, IMM_TRUNC_SEW, vssrl_vx, opivx_check)
+GEN_OPIVI_TRANS(vssra_vi, IMM_TRUNC_SEW, vssra_vx, opivx_check)
/* Vector Narrowing Fixed-Point Clip Instructions */
GEN_OPIWV_NARROW_TRANS(vnclipu_wv)
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 55/75] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (53 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 54/75] target/riscv: rvv-1.0: single-width scaling shift instructions frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 56/75] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf frank.chang
` (19 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/helper.h | 22 ---
target/riscv/insn32.decode | 7 -
target/riscv/insn_trans/trans_rvv.c.inc | 9 --
target/riscv/vector_helper.c | 205 ------------------------
4 files changed, 243 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 2e4ed26f89c..24fdc4396bd 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -727,28 +727,6 @@ DEF_HELPER_6(vsmul_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vsmul_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vsmul_vx_d, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vwsmaccu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vwsmaccu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vwsmaccu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vwsmacc_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vwsmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vwsmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vwsmaccsu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vwsmaccsu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vwsmaccsu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vwsmaccu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vwsmaccu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vwsmaccu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vwsmacc_vx_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vwsmacc_vx_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vwsmacc_vx_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vwsmaccsu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vwsmaccsu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vwsmaccsu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vwsmaccus_vx_b, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vwsmaccus_vx_h, void, ptr, ptr, tl, ptr, env, i32)
-DEF_HELPER_6(vwsmaccus_vx_w, void, ptr, ptr, tl, ptr, env, i32)
-
DEF_HELPER_6(vssrl_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vssrl_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vssrl_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index ac1bcab9627..0ac3329b3c0 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -478,13 +478,6 @@ vasubu_vv 001010 . ..... ..... 010 ..... 1010111 @r_vm
vasubu_vx 001010 . ..... ..... 110 ..... 1010111 @r_vm
vsmul_vv 100111 . ..... ..... 000 ..... 1010111 @r_vm
vsmul_vx 100111 . ..... ..... 100 ..... 1010111 @r_vm
-vwsmaccu_vv 111100 . ..... ..... 000 ..... 1010111 @r_vm
-vwsmaccu_vx 111100 . ..... ..... 100 ..... 1010111 @r_vm
-vwsmacc_vv 111101 . ..... ..... 000 ..... 1010111 @r_vm
-vwsmacc_vx 111101 . ..... ..... 100 ..... 1010111 @r_vm
-vwsmaccsu_vv 111110 . ..... ..... 000 ..... 1010111 @r_vm
-vwsmaccsu_vx 111110 . ..... ..... 100 ..... 1010111 @r_vm
-vwsmaccus_vx 111111 . ..... ..... 100 ..... 1010111 @r_vm
vssrl_vv 101010 . ..... ..... 000 ..... 1010111 @r_vm
vssrl_vx 101010 . ..... ..... 100 ..... 1010111 @r_vm
vssrl_vi 101010 . ..... ..... 011 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 2188e92064f..4abafcd2edc 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2249,15 +2249,6 @@ GEN_OPIVX_TRANS(vasubu_vx, opivx_check)
GEN_OPIVV_TRANS(vsmul_vv, opivv_check)
GEN_OPIVX_TRANS(vsmul_vx, opivx_check)
-/* Vector Widening Saturating Scaled Multiply-Add */
-GEN_OPIVV_WIDEN_TRANS(vwsmaccu_vv, opivv_widen_check)
-GEN_OPIVV_WIDEN_TRANS(vwsmacc_vv, opivv_widen_check)
-GEN_OPIVV_WIDEN_TRANS(vwsmaccsu_vv, opivv_widen_check)
-GEN_OPIVX_WIDEN_TRANS(vwsmaccu_vx)
-GEN_OPIVX_WIDEN_TRANS(vwsmacc_vx)
-GEN_OPIVX_WIDEN_TRANS(vwsmaccsu_vx)
-GEN_OPIVX_WIDEN_TRANS(vwsmaccus_vx)
-
/* Vector Single-Width Scaling Shift Instructions */
GEN_OPIVV_TRANS(vssrl_vv, opivv_check)
GEN_OPIVV_TRANS(vssra_vv, opivv_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index e6931466d40..549a476490e 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -2703,211 +2703,6 @@ GEN_VEXT_VX_RM(vsmul_vx_h, 2, 2)
GEN_VEXT_VX_RM(vsmul_vx_w, 4, 4)
GEN_VEXT_VX_RM(vsmul_vx_d, 8, 8)
-/* Vector Widening Saturating Scaled Multiply-Add */
-static inline uint16_t
-vwsmaccu8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b,
- uint16_t c)
-{
- uint8_t round;
- uint16_t res = (uint16_t)a * b;
-
- round = get_round(vxrm, res, 4);
- res = (res >> 4) + round;
- return saddu16(env, vxrm, c, res);
-}
-
-static inline uint32_t
-vwsmaccu16(CPURISCVState *env, int vxrm, uint16_t a, uint16_t b,
- uint32_t c)
-{
- uint8_t round;
- uint32_t res = (uint32_t)a * b;
-
- round = get_round(vxrm, res, 8);
- res = (res >> 8) + round;
- return saddu32(env, vxrm, c, res);
-}
-
-static inline uint64_t
-vwsmaccu32(CPURISCVState *env, int vxrm, uint32_t a, uint32_t b,
- uint64_t c)
-{
- uint8_t round;
- uint64_t res = (uint64_t)a * b;
-
- round = get_round(vxrm, res, 16);
- res = (res >> 16) + round;
- return saddu64(env, vxrm, c, res);
-}
-
-#define OPIVV3_RM(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \
-static inline void \
-do_##NAME(void *vd, void *vs1, void *vs2, int i, \
- CPURISCVState *env, int vxrm) \
-{ \
- TX1 s1 = *((T1 *)vs1 + HS1(i)); \
- TX2 s2 = *((T2 *)vs2 + HS2(i)); \
- TD d = *((TD *)vd + HD(i)); \
- *((TD *)vd + HD(i)) = OP(env, vxrm, s2, s1, d); \
-}
-
-RVVCALL(OPIVV3_RM, vwsmaccu_vv_b, WOP_UUU_B, H2, H1, H1, vwsmaccu8)
-RVVCALL(OPIVV3_RM, vwsmaccu_vv_h, WOP_UUU_H, H4, H2, H2, vwsmaccu16)
-RVVCALL(OPIVV3_RM, vwsmaccu_vv_w, WOP_UUU_W, H8, H4, H4, vwsmaccu32)
-GEN_VEXT_VV_RM(vwsmaccu_vv_b, 1, 2)
-GEN_VEXT_VV_RM(vwsmaccu_vv_h, 2, 4)
-GEN_VEXT_VV_RM(vwsmaccu_vv_w, 4, 8)
-
-#define OPIVX3_RM(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \
-static inline void \
-do_##NAME(void *vd, target_long s1, void *vs2, int i, \
- CPURISCVState *env, int vxrm) \
-{ \
- TX2 s2 = *((T2 *)vs2 + HS2(i)); \
- TD d = *((TD *)vd + HD(i)); \
- *((TD *)vd + HD(i)) = OP(env, vxrm, s2, (TX1)(T1)s1, d); \
-}
-
-RVVCALL(OPIVX3_RM, vwsmaccu_vx_b, WOP_UUU_B, H2, H1, vwsmaccu8)
-RVVCALL(OPIVX3_RM, vwsmaccu_vx_h, WOP_UUU_H, H4, H2, vwsmaccu16)
-RVVCALL(OPIVX3_RM, vwsmaccu_vx_w, WOP_UUU_W, H8, H4, vwsmaccu32)
-GEN_VEXT_VX_RM(vwsmaccu_vx_b, 1, 2)
-GEN_VEXT_VX_RM(vwsmaccu_vx_h, 2, 4)
-GEN_VEXT_VX_RM(vwsmaccu_vx_w, 4, 8)
-
-static inline int16_t
-vwsmacc8(CPURISCVState *env, int vxrm, int8_t a, int8_t b, int16_t c)
-{
- uint8_t round;
- int16_t res = (int16_t)a * b;
-
- round = get_round(vxrm, res, 4);
- res = (res >> 4) + round;
- return sadd16(env, vxrm, c, res);
-}
-
-static inline int32_t
-vwsmacc16(CPURISCVState *env, int vxrm, int16_t a, int16_t b, int32_t c)
-{
- uint8_t round;
- int32_t res = (int32_t)a * b;
-
- round = get_round(vxrm, res, 8);
- res = (res >> 8) + round;
- return sadd32(env, vxrm, c, res);
-
-}
-
-static inline int64_t
-vwsmacc32(CPURISCVState *env, int vxrm, int32_t a, int32_t b, int64_t c)
-{
- uint8_t round;
- int64_t res = (int64_t)a * b;
-
- round = get_round(vxrm, res, 16);
- res = (res >> 16) + round;
- return sadd64(env, vxrm, c, res);
-}
-
-RVVCALL(OPIVV3_RM, vwsmacc_vv_b, WOP_SSS_B, H2, H1, H1, vwsmacc8)
-RVVCALL(OPIVV3_RM, vwsmacc_vv_h, WOP_SSS_H, H4, H2, H2, vwsmacc16)
-RVVCALL(OPIVV3_RM, vwsmacc_vv_w, WOP_SSS_W, H8, H4, H4, vwsmacc32)
-GEN_VEXT_VV_RM(vwsmacc_vv_b, 1, 2)
-GEN_VEXT_VV_RM(vwsmacc_vv_h, 2, 4)
-GEN_VEXT_VV_RM(vwsmacc_vv_w, 4, 8)
-RVVCALL(OPIVX3_RM, vwsmacc_vx_b, WOP_SSS_B, H2, H1, vwsmacc8)
-RVVCALL(OPIVX3_RM, vwsmacc_vx_h, WOP_SSS_H, H4, H2, vwsmacc16)
-RVVCALL(OPIVX3_RM, vwsmacc_vx_w, WOP_SSS_W, H8, H4, vwsmacc32)
-GEN_VEXT_VX_RM(vwsmacc_vx_b, 1, 2)
-GEN_VEXT_VX_RM(vwsmacc_vx_h, 2, 4)
-GEN_VEXT_VX_RM(vwsmacc_vx_w, 4, 8)
-
-static inline int16_t
-vwsmaccsu8(CPURISCVState *env, int vxrm, uint8_t a, int8_t b, int16_t c)
-{
- uint8_t round;
- int16_t res = a * (int16_t)b;
-
- round = get_round(vxrm, res, 4);
- res = (res >> 4) + round;
- return ssub16(env, vxrm, c, res);
-}
-
-static inline int32_t
-vwsmaccsu16(CPURISCVState *env, int vxrm, uint16_t a, int16_t b, uint32_t c)
-{
- uint8_t round;
- int32_t res = a * (int32_t)b;
-
- round = get_round(vxrm, res, 8);
- res = (res >> 8) + round;
- return ssub32(env, vxrm, c, res);
-}
-
-static inline int64_t
-vwsmaccsu32(CPURISCVState *env, int vxrm, uint32_t a, int32_t b, int64_t c)
-{
- uint8_t round;
- int64_t res = a * (int64_t)b;
-
- round = get_round(vxrm, res, 16);
- res = (res >> 16) + round;
- return ssub64(env, vxrm, c, res);
-}
-
-RVVCALL(OPIVV3_RM, vwsmaccsu_vv_b, WOP_SSU_B, H2, H1, H1, vwsmaccsu8)
-RVVCALL(OPIVV3_RM, vwsmaccsu_vv_h, WOP_SSU_H, H4, H2, H2, vwsmaccsu16)
-RVVCALL(OPIVV3_RM, vwsmaccsu_vv_w, WOP_SSU_W, H8, H4, H4, vwsmaccsu32)
-GEN_VEXT_VV_RM(vwsmaccsu_vv_b, 1, 2)
-GEN_VEXT_VV_RM(vwsmaccsu_vv_h, 2, 4)
-GEN_VEXT_VV_RM(vwsmaccsu_vv_w, 4, 8)
-RVVCALL(OPIVX3_RM, vwsmaccsu_vx_b, WOP_SSU_B, H2, H1, vwsmaccsu8)
-RVVCALL(OPIVX3_RM, vwsmaccsu_vx_h, WOP_SSU_H, H4, H2, vwsmaccsu16)
-RVVCALL(OPIVX3_RM, vwsmaccsu_vx_w, WOP_SSU_W, H8, H4, vwsmaccsu32)
-GEN_VEXT_VX_RM(vwsmaccsu_vx_b, 1, 2)
-GEN_VEXT_VX_RM(vwsmaccsu_vx_h, 2, 4)
-GEN_VEXT_VX_RM(vwsmaccsu_vx_w, 4, 8)
-
-static inline int16_t
-vwsmaccus8(CPURISCVState *env, int vxrm, int8_t a, uint8_t b, int16_t c)
-{
- uint8_t round;
- int16_t res = (int16_t)a * b;
-
- round = get_round(vxrm, res, 4);
- res = (res >> 4) + round;
- return ssub16(env, vxrm, c, res);
-}
-
-static inline int32_t
-vwsmaccus16(CPURISCVState *env, int vxrm, int16_t a, uint16_t b, int32_t c)
-{
- uint8_t round;
- int32_t res = (int32_t)a * b;
-
- round = get_round(vxrm, res, 8);
- res = (res >> 8) + round;
- return ssub32(env, vxrm, c, res);
-}
-
-static inline int64_t
-vwsmaccus32(CPURISCVState *env, int vxrm, int32_t a, uint32_t b, int64_t c)
-{
- uint8_t round;
- int64_t res = (int64_t)a * b;
-
- round = get_round(vxrm, res, 16);
- res = (res >> 16) + round;
- return ssub64(env, vxrm, c, res);
-}
-
-RVVCALL(OPIVX3_RM, vwsmaccus_vx_b, WOP_SUS_B, H2, H1, vwsmaccus8)
-RVVCALL(OPIVX3_RM, vwsmaccus_vx_h, WOP_SUS_H, H4, H2, vwsmaccus16)
-RVVCALL(OPIVX3_RM, vwsmaccus_vx_w, WOP_SUS_W, H8, H4, vwsmaccus32)
-GEN_VEXT_VX_RM(vwsmaccus_vx_b, 1, 2)
-GEN_VEXT_VX_RM(vwsmaccus_vx_h, 2, 4)
-GEN_VEXT_VX_RM(vwsmaccus_vx_w, 4, 8)
-
/* Vector Single-Width Scaling Shift Instructions */
static inline uint8_t
vssrl8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b)
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 56/75] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (54 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 55/75] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 57/75] target/riscv: rvv-1.0: remove integer extract instruction frank.chang
` (18 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/helper.h | 6 ------
target/riscv/insn32.decode | 2 --
target/riscv/insn_trans/trans_rvv.c.inc | 2 --
target/riscv/vector_helper.c | 7 -------
4 files changed, 17 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 24fdc4396bd..cdaa21b7008 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -943,12 +943,6 @@ DEF_HELPER_6(vmfgt_vf_d, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vmfge_vf_h, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vmfge_vf_w, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vmfge_vf_d, void, ptr, ptr, i64, ptr, env, i32)
-DEF_HELPER_6(vmford_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vmford_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vmford_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_6(vmford_vf_h, void, ptr, ptr, i64, ptr, env, i32)
-DEF_HELPER_6(vmford_vf_w, void, ptr, ptr, i64, ptr, env, i32)
-DEF_HELPER_6(vmford_vf_d, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_5(vfclass_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfclass_v_w, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 0ac3329b3c0..2d96c53d066 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -557,8 +557,6 @@ vmfle_vv 011001 . ..... ..... 001 ..... 1010111 @r_vm
vmfle_vf 011001 . ..... ..... 101 ..... 1010111 @r_vm
vmfgt_vf 011101 . ..... ..... 101 ..... 1010111 @r_vm
vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm
-vmford_vv 011010 . ..... ..... 001 ..... 1010111 @r_vm
-vmford_vf 011010 . ..... ..... 101 ..... 1010111 @r_vm
vfclass_v 010011 . ..... 10000 001 ..... 1010111 @r2_vm
vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0
vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 4abafcd2edc..c3ec88e238c 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2655,7 +2655,6 @@ GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check)
GEN_OPFVV_TRANS(vmfne_vv, opfvv_cmp_check)
GEN_OPFVV_TRANS(vmflt_vv, opfvv_cmp_check)
GEN_OPFVV_TRANS(vmfle_vv, opfvv_cmp_check)
-GEN_OPFVV_TRANS(vmford_vv, opfvv_cmp_check)
static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a)
{
@@ -2671,7 +2670,6 @@ GEN_OPFVF_TRANS(vmflt_vf, opfvf_cmp_check)
GEN_OPFVF_TRANS(vmfle_vf, opfvf_cmp_check)
GEN_OPFVF_TRANS(vmfgt_vf, opfvf_cmp_check)
GEN_OPFVF_TRANS(vmfge_vf, opfvf_cmp_check)
-GEN_OPFVF_TRANS(vmford_vf, opfvf_cmp_check)
/* Vector Floating-Point Classify Instruction */
GEN_OPFV_TRANS(vfclass_v, opfv_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 549a476490e..c5e65720120 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -3839,13 +3839,6 @@ GEN_VEXT_CMP_VF(vmfge_vf_h, uint16_t, H2, vmfge16)
GEN_VEXT_CMP_VF(vmfge_vf_w, uint32_t, H4, vmfge32)
GEN_VEXT_CMP_VF(vmfge_vf_d, uint64_t, H8, vmfge64)
-GEN_VEXT_CMP_VV_ENV(vmford_vv_h, uint16_t, H2, !float16_unordered_quiet)
-GEN_VEXT_CMP_VV_ENV(vmford_vv_w, uint32_t, H4, !float32_unordered_quiet)
-GEN_VEXT_CMP_VV_ENV(vmford_vv_d, uint64_t, H8, !float64_unordered_quiet)
-GEN_VEXT_CMP_VF(vmford_vf_h, uint16_t, H2, !float16_unordered_quiet)
-GEN_VEXT_CMP_VF(vmford_vf_w, uint32_t, H4, !float32_unordered_quiet)
-GEN_VEXT_CMP_VF(vmford_vf_d, uint64_t, H8, !float64_unordered_quiet)
-
/* Vector Floating-Point Classify Instruction */
#define OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP) \
static void do_##NAME(void *vd, void *vs2, int i) \
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 57/75] target/riscv: rvv-1.0: remove integer extract instruction
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (55 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 56/75] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 58/75] target/riscv: rvv-1.0: floating-point min/max instructions frank.chang
` (17 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn32.decode | 1 -
target/riscv/insn_trans/trans_rvv.c.inc | 23 -----------------------
2 files changed, 24 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 2d96c53d066..0d29ac2b2a1 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -607,7 +607,6 @@ viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm
vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm
vmv_x_s 010000 1 ..... 00000 010 ..... 1010111 @r2rd
vmv_s_x 010000 1 00000 ..... 110 ..... 1010111 @r2
-vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
vfmv_f_s 010000 1 ..... 00000 001 ..... 1010111 @r2rd
vfmv_s_f 010000 1 00000 ..... 101 ..... 1010111 @r2
vslideup_vx 001110 . ..... ..... 100 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index c3ec88e238c..de7152dc323 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3071,8 +3071,6 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
*** Vector Permutation Instructions
*/
-/* Integer Extract Instruction */
-
static void load_element(TCGv_i64 dest, TCGv_ptr base,
int ofs, int sew, bool sign)
{
@@ -3174,27 +3172,6 @@ static void vec_element_loadi(DisasContext *s, TCGv_i64 dest,
load_element(dest, cpu_env, endian_ofs(s, vreg, idx), s->sew, sign);
}
-static bool trans_vext_x_v(DisasContext *s, arg_r *a)
-{
- TCGv_i64 tmp = tcg_temp_new_i64();
- TCGv dest = tcg_temp_new();
-
- if (a->rs1 == 0) {
- /* Special case vmv.x.s rd, vs2. */
- vec_element_loadi(s, tmp, a->rs2, 0, false);
- } else {
- /* This instruction ignores LMUL and vector register groups */
- int vlmax = s->vlen >> (3 + s->sew);
- vec_element_loadx(s, tmp, a->rs2, cpu_gpr[a->rs1], vlmax);
- }
- tcg_gen_trunc_i64_tl(dest, tmp);
- gen_set_gpr(a->rd, dest);
-
- tcg_temp_free(dest);
- tcg_temp_free_i64(tmp);
- return true;
-}
-
/* Integer Scalar Move Instruction */
static void store_element(TCGv_i64 val, TCGv_ptr base,
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 58/75] target/riscv: rvv-1.0: floating-point min/max instructions
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (56 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 57/75] target/riscv: rvv-1.0: remove integer extract instruction frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 59/75] target/riscv: introduce floating-point rounding mode enum frank.chang
` (16 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Alistair Francis, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/vector_helper.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index c5e65720120..e3056a06fe2 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -3596,28 +3596,28 @@ GEN_VEXT_V_ENV(vfsqrt_v_w, 4, 4)
GEN_VEXT_V_ENV(vfsqrt_v_d, 8, 8)
/* Vector Floating-Point MIN/MAX Instructions */
-RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minnum)
-RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minnum)
-RVVCALL(OPFVV2, vfmin_vv_d, OP_UUU_D, H8, H8, H8, float64_minnum)
+RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minnum_noprop)
+RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minnum_noprop)
+RVVCALL(OPFVV2, vfmin_vv_d, OP_UUU_D, H8, H8, H8, float64_minnum_noprop)
GEN_VEXT_VV_ENV(vfmin_vv_h, 2, 2)
GEN_VEXT_VV_ENV(vfmin_vv_w, 4, 4)
GEN_VEXT_VV_ENV(vfmin_vv_d, 8, 8)
-RVVCALL(OPFVF2, vfmin_vf_h, OP_UUU_H, H2, H2, float16_minnum)
-RVVCALL(OPFVF2, vfmin_vf_w, OP_UUU_W, H4, H4, float32_minnum)
-RVVCALL(OPFVF2, vfmin_vf_d, OP_UUU_D, H8, H8, float64_minnum)
+RVVCALL(OPFVF2, vfmin_vf_h, OP_UUU_H, H2, H2, float16_minnum_noprop)
+RVVCALL(OPFVF2, vfmin_vf_w, OP_UUU_W, H4, H4, float32_minnum_noprop)
+RVVCALL(OPFVF2, vfmin_vf_d, OP_UUU_D, H8, H8, float64_minnum_noprop)
GEN_VEXT_VF(vfmin_vf_h, 2, 2)
GEN_VEXT_VF(vfmin_vf_w, 4, 4)
GEN_VEXT_VF(vfmin_vf_d, 8, 8)
-RVVCALL(OPFVV2, vfmax_vv_h, OP_UUU_H, H2, H2, H2, float16_maxnum)
-RVVCALL(OPFVV2, vfmax_vv_w, OP_UUU_W, H4, H4, H4, float32_maxnum)
-RVVCALL(OPFVV2, vfmax_vv_d, OP_UUU_D, H8, H8, H8, float64_maxnum)
+RVVCALL(OPFVV2, vfmax_vv_h, OP_UUU_H, H2, H2, H2, float16_maxnum_noprop)
+RVVCALL(OPFVV2, vfmax_vv_w, OP_UUU_W, H4, H4, H4, float32_maxnum_noprop)
+RVVCALL(OPFVV2, vfmax_vv_d, OP_UUU_D, H8, H8, H8, float64_maxnum_noprop)
GEN_VEXT_VV_ENV(vfmax_vv_h, 2, 2)
GEN_VEXT_VV_ENV(vfmax_vv_w, 4, 4)
GEN_VEXT_VV_ENV(vfmax_vv_d, 8, 8)
-RVVCALL(OPFVF2, vfmax_vf_h, OP_UUU_H, H2, H2, float16_maxnum)
-RVVCALL(OPFVF2, vfmax_vf_w, OP_UUU_W, H4, H4, float32_maxnum)
-RVVCALL(OPFVF2, vfmax_vf_d, OP_UUU_D, H8, H8, float64_maxnum)
+RVVCALL(OPFVF2, vfmax_vf_h, OP_UUU_H, H2, H2, float16_maxnum_noprop)
+RVVCALL(OPFVF2, vfmax_vf_w, OP_UUU_W, H4, H4, float32_maxnum_noprop)
+RVVCALL(OPFVF2, vfmax_vf_d, OP_UUU_D, H8, H8, float64_maxnum_noprop)
GEN_VEXT_VF(vfmax_vf_h, 2, 2)
GEN_VEXT_VF(vfmax_vf_w, 4, 4)
GEN_VEXT_VF(vfmax_vf_d, 8, 8)
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 59/75] target/riscv: introduce floating-point rounding mode enum
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (57 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 58/75] target/riscv: rvv-1.0: floating-point min/max instructions frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 60/75] target/riscv: rvv-1.0: floating-point/integer type-convert instructions frank.chang
` (15 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/fpu_helper.c | 12 ++++++------
target/riscv/insn_trans/trans_rvv.c.inc | 18 +++++++++---------
target/riscv/internals.h | 9 +++++++++
3 files changed, 24 insertions(+), 15 deletions(-)
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index 7c4ab92ecbe..ad84aeebc1c 100644
--- a/target/riscv/fpu_helper.c
+++ b/target/riscv/fpu_helper.c
@@ -55,23 +55,23 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm)
{
int softrm;
- if (rm == 7) {
+ if (rm == RISCV_FRM_DYN) {
rm = env->frm;
}
switch (rm) {
- case 0:
+ case RISCV_FRM_RNE:
softrm = float_round_nearest_even;
break;
- case 1:
+ case RISCV_FRM_RTZ:
softrm = float_round_to_zero;
break;
- case 2:
+ case RISCV_FRM_RDN:
softrm = float_round_down;
break;
- case 3:
+ case RISCV_FRM_RUP:
softrm = float_round_up;
break;
- case 4:
+ case RISCV_FRM_RMM:
softrm = float_round_ties_away;
break;
default:
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index de7152dc323..3f453ed457a 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2321,7 +2321,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_helper_##NAME##_d, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, RISCV_FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2400,7 +2400,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_helper_##NAME##_w, \
gen_helper_##NAME##_d, \
}; \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, RISCV_FRM_DYN); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
@@ -2432,7 +2432,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, RISCV_FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2468,7 +2468,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
static gen_helper_opfvf *const fns[2] = { \
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, RISCV_FRM_DYN); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
@@ -2498,7 +2498,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, RISCV_FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2534,7 +2534,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
static gen_helper_opfvf *const fns[2] = { \
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, RISCV_FRM_DYN); \
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
@@ -2611,7 +2611,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
gen_helper_##NAME##_d, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, RISCV_FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2757,7 +2757,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
gen_helper_##NAME##_w, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, RISCV_FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2804,7 +2804,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
gen_helper_##NAME##_w, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, 7); \
+ gen_set_rm(s, RISCV_FRM_DYN); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index 959b81b3016..469cc418c4e 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -36,6 +36,15 @@ target_ulong fclass_d(uint64_t frs1);
extern const VMStateDescription vmstate_riscv_cpu;
#endif
+enum {
+ RISCV_FRM_RNE = 0, /* Round to Nearest, ties to Even */
+ RISCV_FRM_RTZ = 1, /* Round towards Zero */
+ RISCV_FRM_RDN = 2, /* Round Down */
+ RISCV_FRM_RUP = 3, /* Round Up */
+ RISCV_FRM_RMM = 4, /* Round to Nearest, ties to Max Magnitude */
+ RISCV_FRM_DYN = 7, /* Dynamic rounding mode */
+};
+
static inline uint64_t nanbox_s(float32 f)
{
return f | MAKE_64BIT_MASK(32, 32);
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 60/75] target/riscv: rvv-1.0: floating-point/integer type-convert instructions
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (58 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 59/75] target/riscv: introduce floating-point rounding mode enum frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 61/75] target/riscv: rvv-1.0: widening floating-point/integer type-convert frank.chang
` (14 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Add the following instructions:
* vfcvt.rtz.xu.f.v
* vfcvt.rtz.x.f.v
Also adjust GEN_OPFV_TRANS() to accept multiple floating-point rounding
modes.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 11 ++--
target/riscv/insn_trans/trans_rvv.c.inc | 83 ++++++++++++++++---------
2 files changed, 59 insertions(+), 35 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 0d29ac2b2a1..c15ed5d3dbb 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -560,10 +560,13 @@ vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm
vfclass_v 010011 . ..... 10000 001 ..... 1010111 @r2_vm
vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0
vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2
-vfcvt_xu_f_v 100010 . ..... 00000 001 ..... 1010111 @r2_vm
-vfcvt_x_f_v 100010 . ..... 00001 001 ..... 1010111 @r2_vm
-vfcvt_f_xu_v 100010 . ..... 00010 001 ..... 1010111 @r2_vm
-vfcvt_f_x_v 100010 . ..... 00011 001 ..... 1010111 @r2_vm
+
+vfcvt_xu_f_v 010010 . ..... 00000 001 ..... 1010111 @r2_vm
+vfcvt_x_f_v 010010 . ..... 00001 001 ..... 1010111 @r2_vm
+vfcvt_f_xu_v 010010 . ..... 00010 001 ..... 1010111 @r2_vm
+vfcvt_f_x_v 010010 . ..... 00011 001 ..... 1010111 @r2_vm
+vfcvt_rtz_xu_f_v 010010 . ..... 00110 001 ..... 1010111 @r2_vm
+vfcvt_rtz_x_f_v 010010 . ..... 00111 001 ..... 1010111 @r2_vm
vfwcvt_xu_f_v 100010 . ..... 01000 001 ..... 1010111 @r2_vm
vfwcvt_x_f_v 100010 . ..... 01001 001 ..... 1010111 @r2_vm
vfwcvt_f_xu_v 100010 . ..... 01010 001 ..... 1010111 @r2_vm
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 3f453ed457a..4f5f36aae8f 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1,5 +1,4 @@
/*
- * RISC-V translation routines for the RVV Standard Extension.
*
* Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved.
*
@@ -2600,33 +2599,41 @@ static bool opfv_check(DisasContext *s, arg_rmr *a)
vext_check_ss(s, a->rd, a->rs2, a->vm);
}
-#define GEN_OPFV_TRANS(NAME, CHECK) \
-static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
-{ \
- if (CHECK(s, a)) { \
- uint32_t data = 0; \
- static gen_helper_gvec_3_ptr * const fns[3] = { \
- gen_helper_##NAME##_h, \
- gen_helper_##NAME##_w, \
- gen_helper_##NAME##_d, \
- }; \
- TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, RISCV_FRM_DYN); \
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
- \
- data = FIELD_DP32(data, VDATA, VM, a->vm); \
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
- tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
- vreg_ofs(s, a->rs2), cpu_env, 0, \
- s->vlen / 8, data, fns[s->sew - 1]); \
- mark_vs_dirty(s); \
- gen_set_label(over); \
- return true; \
- } \
- return false; \
+static bool do_opfv(DisasContext *s, arg_rmr *a,
+ gen_helper_gvec_3_ptr *fn,
+ bool (*checkfn)(DisasContext *, arg_rmr *),
+ int rm)
+{
+ if (checkfn(s, a)) {
+ uint32_t data = 0;
+ TCGLabel *over = gen_new_label();
+ gen_set_rm(s, rm);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+
+ data = FIELD_DP32(data, VDATA, VM, a->vm);
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
+ vreg_ofs(s, a->rs2), cpu_env, 0,
+ s->vlen / 8, data, fn);
+ mark_vs_dirty(s);
+ gen_set_label(over);
+ return true;
+ }
+ return false;
+}
+
+#define GEN_OPFV_TRANS(NAME, CHECK, FRM) \
+static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
+{ \
+ static gen_helper_gvec_3_ptr * const fns[3] = { \
+ gen_helper_##NAME##_h, \
+ gen_helper_##NAME##_w, \
+ gen_helper_##NAME##_d \
+ }; \
+ return do_opfv(s, a, fns[s->sew - 1], CHECK, FRM); \
}
-GEN_OPFV_TRANS(vfsqrt_v, opfv_check)
+GEN_OPFV_TRANS(vfsqrt_v, opfv_check, RISCV_FRM_DYN)
/* Vector Floating-Point MIN/MAX Instructions */
GEN_OPFVV_TRANS(vfmin_vv, opfvv_check)
@@ -2672,7 +2679,7 @@ GEN_OPFVF_TRANS(vmfgt_vf, opfvf_cmp_check)
GEN_OPFVF_TRANS(vmfge_vf, opfvf_cmp_check)
/* Vector Floating-Point Classify Instruction */
-GEN_OPFV_TRANS(vfclass_v, opfv_check)
+GEN_OPFV_TRANS(vfclass_v, opfv_check, RISCV_FRM_DYN)
/* Vector Floating-Point Merge Instruction */
GEN_OPFVF_TRANS(vfmerge_vfm, opfvf_check)
@@ -2727,10 +2734,24 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
}
/* Single-Width Floating-Point/Integer Type-Convert Instructions */
-GEN_OPFV_TRANS(vfcvt_xu_f_v, opfv_check)
-GEN_OPFV_TRANS(vfcvt_x_f_v, opfv_check)
-GEN_OPFV_TRANS(vfcvt_f_xu_v, opfv_check)
-GEN_OPFV_TRANS(vfcvt_f_x_v, opfv_check)
+#define GEN_OPFV_CVT_TRANS(NAME, HELPER, FRM) \
+static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
+{ \
+ static gen_helper_gvec_3_ptr * const fns[3] = { \
+ gen_helper_##HELPER##_h, \
+ gen_helper_##HELPER##_w, \
+ gen_helper_##HELPER##_d \
+ }; \
+ return do_opfv(s, a, fns[s->sew - 1], opfv_check, FRM); \
+}
+
+GEN_OPFV_CVT_TRANS(vfcvt_xu_f_v, vfcvt_xu_f_v, RISCV_FRM_DYN)
+GEN_OPFV_CVT_TRANS(vfcvt_x_f_v, vfcvt_x_f_v, RISCV_FRM_DYN)
+GEN_OPFV_CVT_TRANS(vfcvt_f_xu_v, vfcvt_f_xu_v, RISCV_FRM_DYN)
+GEN_OPFV_CVT_TRANS(vfcvt_f_x_v, vfcvt_f_x_v, RISCV_FRM_DYN)
+/* Reuse the helper functions from vfcvt.xu.f.v and vfcvt.x.f.v */
+GEN_OPFV_CVT_TRANS(vfcvt_rtz_xu_f_v, vfcvt_xu_f_v, RISCV_FRM_RTZ)
+GEN_OPFV_CVT_TRANS(vfcvt_rtz_x_f_v, vfcvt_x_f_v, RISCV_FRM_RTZ)
/* Widening Floating-Point/Integer Type-Convert Instructions */
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 61/75] target/riscv: rvv-1.0: widening floating-point/integer type-convert
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (59 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 60/75] target/riscv: rvv-1.0: floating-point/integer type-convert instructions frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 62/75] target/riscv: add "set round to odd" rounding mode helper function frank.chang
` (13 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Add the following instructions:
* vfwcvt.rtz.xu.f.v
* vfwcvt.rtz.x.f.v
Also adjust GEN_OPFV_WIDEN_TRANS() to accept multiple floating-point
rounding modes.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 2 +
target/riscv/insn32.decode | 13 +++---
target/riscv/insn_trans/trans_rvv.c.inc | 54 +++++++++++++++++++++----
target/riscv/vector_helper.c | 7 +++-
4 files changed, 62 insertions(+), 14 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index cdaa21b7008..e11cce3e8ea 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -969,8 +969,10 @@ DEF_HELPER_5(vfwcvt_xu_f_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_xu_f_v_w, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_x_f_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_x_f_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfwcvt_f_xu_v_b, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_f_xu_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_f_xu_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfwcvt_f_x_v_b, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_f_x_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_f_x_v_w, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_f_f_v_h, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index c15ed5d3dbb..34bb062c200 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -567,11 +567,14 @@ vfcvt_f_xu_v 010010 . ..... 00010 001 ..... 1010111 @r2_vm
vfcvt_f_x_v 010010 . ..... 00011 001 ..... 1010111 @r2_vm
vfcvt_rtz_xu_f_v 010010 . ..... 00110 001 ..... 1010111 @r2_vm
vfcvt_rtz_x_f_v 010010 . ..... 00111 001 ..... 1010111 @r2_vm
-vfwcvt_xu_f_v 100010 . ..... 01000 001 ..... 1010111 @r2_vm
-vfwcvt_x_f_v 100010 . ..... 01001 001 ..... 1010111 @r2_vm
-vfwcvt_f_xu_v 100010 . ..... 01010 001 ..... 1010111 @r2_vm
-vfwcvt_f_x_v 100010 . ..... 01011 001 ..... 1010111 @r2_vm
-vfwcvt_f_f_v 100010 . ..... 01100 001 ..... 1010111 @r2_vm
+
+vfwcvt_xu_f_v 010010 . ..... 01000 001 ..... 1010111 @r2_vm
+vfwcvt_x_f_v 010010 . ..... 01001 001 ..... 1010111 @r2_vm
+vfwcvt_f_xu_v 010010 . ..... 01010 001 ..... 1010111 @r2_vm
+vfwcvt_f_x_v 010010 . ..... 01011 001 ..... 1010111 @r2_vm
+vfwcvt_f_f_v 010010 . ..... 01100 001 ..... 1010111 @r2_vm
+vfwcvt_rtz_xu_f_v 010010 . ..... 01110 001 ..... 1010111 @r2_vm
+vfwcvt_rtz_x_f_v 010010 . ..... 01111 001 ..... 1010111 @r2_vm
vfncvt_xu_f_v 100010 . ..... 10000 001 ..... 1010111 @r2_vm
vfncvt_x_f_v 100010 . ..... 10001 001 ..... 1010111 @r2_vm
vfncvt_f_xu_v 100010 . ..... 10010 001 ..... 1010111 @r2_vm
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 4f5f36aae8f..b134a883bb2 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2768,12 +2768,54 @@ static bool opfv_widen_check(DisasContext *s, arg_rmr *a)
vext_check_ds(s, a->rd, a->rs2, a->vm);
}
-#define GEN_OPFV_WIDEN_TRANS(NAME) \
+#define GEN_OPFV_WIDEN_TRANS(NAME, HELPER, FRM) \
static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
{ \
if (opfv_widen_check(s, a)) { \
uint32_t data = 0; \
static gen_helper_gvec_3_ptr * const fns[2] = { \
+ gen_helper_##HELPER##_h, \
+ gen_helper_##HELPER##_w, \
+ }; \
+ TCGLabel *over = gen_new_label(); \
+ gen_set_rm(s, FRM); \
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ \
+ data = FIELD_DP32(data, VDATA, VM, a->vm); \
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
+ vreg_ofs(s, a->rs2), cpu_env, 0, \
+ s->vlen / 8, data, fns[s->sew - 1]); \
+ mark_vs_dirty(s); \
+ gen_set_label(over); \
+ return true; \
+ } \
+ return false; \
+}
+
+GEN_OPFV_WIDEN_TRANS(vfwcvt_xu_f_v, vfwcvt_xu_f_v, RISCV_FRM_DYN)
+GEN_OPFV_WIDEN_TRANS(vfwcvt_x_f_v, vfwcvt_x_f_v, RISCV_FRM_DYN)
+GEN_OPFV_WIDEN_TRANS(vfwcvt_f_f_v, vfwcvt_f_f_v, RISCV_FRM_DYN)
+/* Reuse the helper functions from vfwcvt.xu.f.v and vfwcvt.x.f.v */
+GEN_OPFV_WIDEN_TRANS(vfwcvt_rtz_xu_f_v, vfwcvt_xu_f_v, RISCV_FRM_RTZ)
+GEN_OPFV_WIDEN_TRANS(vfwcvt_rtz_x_f_v, vfwcvt_x_f_v, RISCV_FRM_RTZ)
+
+static bool opfxv_widen_check(DisasContext *s, arg_rmr *a)
+{
+ return require_rvv(s) &&
+ require_scale_rvf(s) &&
+ vext_check_isa_ill(s) &&
+ /* OPFV widening instructions ignore vs1 check */
+ vext_check_ds(s, a->rd, a->rs2, a->vm);
+}
+
+#define GEN_OPFXV_WIDEN_TRANS(NAME) \
+static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
+{ \
+ if (opfxv_widen_check(s, a)) { \
+ uint32_t data = 0; \
+ static gen_helper_gvec_3_ptr * const fns[3] = { \
+ gen_helper_##NAME##_b, \
gen_helper_##NAME##_h, \
gen_helper_##NAME##_w, \
}; \
@@ -2782,10 +2824,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
- data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), cpu_env, 0, \
- s->vlen / 8, data, fns[s->sew - 1]); \
+ s->vlen / 8, data, fns[s->sew]); \
mark_vs_dirty(s); \
gen_set_label(over); \
return true; \
@@ -2793,11 +2834,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
return false; \
}
-GEN_OPFV_WIDEN_TRANS(vfwcvt_xu_f_v)
-GEN_OPFV_WIDEN_TRANS(vfwcvt_x_f_v)
-GEN_OPFV_WIDEN_TRANS(vfwcvt_f_xu_v)
-GEN_OPFV_WIDEN_TRANS(vfwcvt_f_x_v)
-GEN_OPFV_WIDEN_TRANS(vfwcvt_f_f_v)
+GEN_OPFXV_WIDEN_TRANS(vfwcvt_f_xu_v)
+GEN_OPFXV_WIDEN_TRANS(vfwcvt_f_x_v)
/* Narrowing Floating-Point/Integer Type-Convert Instructions */
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index e3056a06fe2..e8de460b29b 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -3982,6 +3982,7 @@ GEN_VEXT_V_ENV(vfcvt_f_x_v_d, 8, 8)
/* Widening Floating-Point/Integer Type-Convert Instructions */
/* (TD, T2, TX2) */
+#define WOP_UU_B uint16_t, uint8_t, uint8_t
#define WOP_UU_H uint32_t, uint16_t, uint16_t
#define WOP_UU_W uint64_t, uint32_t, uint32_t
/* vfwcvt.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer.*/
@@ -3997,19 +3998,23 @@ GEN_VEXT_V_ENV(vfwcvt_x_f_v_h, 2, 4)
GEN_VEXT_V_ENV(vfwcvt_x_f_v_w, 4, 8)
/* vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to double-width float */
+RVVCALL(OPFVV1, vfwcvt_f_xu_v_b, WOP_UU_B, H2, H1, uint8_to_float16)
RVVCALL(OPFVV1, vfwcvt_f_xu_v_h, WOP_UU_H, H4, H2, uint16_to_float32)
RVVCALL(OPFVV1, vfwcvt_f_xu_v_w, WOP_UU_W, H8, H4, uint32_to_float64)
+GEN_VEXT_V_ENV(vfwcvt_f_xu_v_b, 1, 2)
GEN_VEXT_V_ENV(vfwcvt_f_xu_v_h, 2, 4)
GEN_VEXT_V_ENV(vfwcvt_f_xu_v_w, 4, 8)
/* vfwcvt.f.x.v vd, vs2, vm # Convert integer to double-width float. */
+RVVCALL(OPFVV1, vfwcvt_f_x_v_b, WOP_UU_B, H2, H1, int8_to_float16)
RVVCALL(OPFVV1, vfwcvt_f_x_v_h, WOP_UU_H, H4, H2, int16_to_float32)
RVVCALL(OPFVV1, vfwcvt_f_x_v_w, WOP_UU_W, H8, H4, int32_to_float64)
+GEN_VEXT_V_ENV(vfwcvt_f_x_v_b, 1, 2)
GEN_VEXT_V_ENV(vfwcvt_f_x_v_h, 2, 4)
GEN_VEXT_V_ENV(vfwcvt_f_x_v_w, 4, 8)
/*
- * vfwcvt.f.f.v vd, vs2, vm #
+ * vfwcvt.f.f.v vd, vs2, vm
* Convert single-width float to double-width float.
*/
static uint32_t vfwcvtffv16(uint16_t a, float_status *s)
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 62/75] target/riscv: add "set round to odd" rounding mode helper function
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (60 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 61/75] target/riscv: rvv-1.0: widening floating-point/integer type-convert frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 63/75] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert frank.chang
` (12 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Alistair Francis, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
helper_set_rounding_mode() is responsible for SIGILL, and "round to odd"
should be an interface private to translation, so add a new independent
helper_set_rod_rounding_mode().
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/fpu_helper.c | 5 +++++
target/riscv/helper.h | 1 +
target/riscv/internals.h | 1 +
target/riscv/translate.c | 5 +++++
4 files changed, 12 insertions(+)
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index ad84aeebc1c..ac3e7b4d08f 100644
--- a/target/riscv/fpu_helper.c
+++ b/target/riscv/fpu_helper.c
@@ -81,6 +81,11 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm)
set_float_rounding_mode(softrm, &env->fp_status);
}
+void helper_set_rod_rounding_mode(CPURISCVState *env)
+{
+ set_float_rounding_mode(float_round_to_odd, &env->fp_status);
+}
+
static uint64_t do_fmadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2,
uint64_t rs3, int flags)
{
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index e11cce3e8ea..1d52936c399 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -3,6 +3,7 @@ DEF_HELPER_2(raise_exception, noreturn, env, i32)
/* Floating Point - rounding mode */
DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_WG, void, env, i32)
+DEF_HELPER_FLAGS_1(set_rod_rounding_mode, TCG_CALL_NO_WG, void, env)
/* Floating Point - fused */
DEF_HELPER_FLAGS_4(fmadd_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index 469cc418c4e..6a80c067706 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -43,6 +43,7 @@ enum {
RISCV_FRM_RUP = 3, /* Round Up */
RISCV_FRM_RMM = 4, /* Round to Nearest, ties to Max Magnitude */
RISCV_FRM_DYN = 7, /* Dynamic rounding mode */
+ RISCV_FRM_ROD = 8, /* Round to Odd */
};
static inline uint64_t nanbox_s(float32 f)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index d9a794d71e8..b9da55c75a8 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -30,6 +30,7 @@
#include "exec/log.h"
#include "instmap.h"
+#include "internals.h"
/* global register indices */
static TCGv cpu_gpr[32], cpu_pc, cpu_vl;
@@ -585,6 +586,10 @@ static void gen_set_rm(DisasContext *ctx, int rm)
return;
}
ctx->frm = rm;
+ if (rm == RISCV_FRM_ROD) {
+ gen_helper_set_rod_rounding_mode(cpu_env);
+ return;
+ }
t0 = tcg_const_i32(rm);
gen_helper_set_rounding_mode(cpu_env, t0);
tcg_temp_free_i32(t0);
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 63/75] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (61 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 62/75] target/riscv: add "set round to odd" rounding mode helper function frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 64/75] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits frank.chang
` (11 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 22 +++++-----
target/riscv/insn32.decode | 15 ++++---
target/riscv/insn_trans/trans_rvv.c.inc | 58 +++++++++++++++++++++----
target/riscv/vector_helper.c | 45 ++++++++++---------
4 files changed, 96 insertions(+), 44 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 1d52936c399..6eb4033d654 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -979,16 +979,18 @@ DEF_HELPER_5(vfwcvt_f_x_v_w, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_f_f_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfwcvt_f_f_v_w, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_xu_f_v_h, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_xu_f_v_w, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_x_f_v_h, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_x_f_v_w, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_f_xu_v_h, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_f_xu_v_w, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_f_x_v_h, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_f_x_v_w, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_f_f_v_h, void, ptr, ptr, ptr, env, i32)
-DEF_HELPER_5(vfncvt_f_f_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_xu_f_w_b, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_xu_f_w_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_xu_f_w_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_x_f_w_b, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_x_f_w_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_x_f_w_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_f_xu_w_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_f_xu_w_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_f_x_w_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_f_x_w_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_f_f_w_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfncvt_f_f_w_w, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vredsum_vs_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 34bb062c200..f670c1282d8 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -575,11 +575,16 @@ vfwcvt_f_x_v 010010 . ..... 01011 001 ..... 1010111 @r2_vm
vfwcvt_f_f_v 010010 . ..... 01100 001 ..... 1010111 @r2_vm
vfwcvt_rtz_xu_f_v 010010 . ..... 01110 001 ..... 1010111 @r2_vm
vfwcvt_rtz_x_f_v 010010 . ..... 01111 001 ..... 1010111 @r2_vm
-vfncvt_xu_f_v 100010 . ..... 10000 001 ..... 1010111 @r2_vm
-vfncvt_x_f_v 100010 . ..... 10001 001 ..... 1010111 @r2_vm
-vfncvt_f_xu_v 100010 . ..... 10010 001 ..... 1010111 @r2_vm
-vfncvt_f_x_v 100010 . ..... 10011 001 ..... 1010111 @r2_vm
-vfncvt_f_f_v 100010 . ..... 10100 001 ..... 1010111 @r2_vm
+
+vfncvt_xu_f_w 010010 . ..... 10000 001 ..... 1010111 @r2_vm
+vfncvt_x_f_w 010010 . ..... 10001 001 ..... 1010111 @r2_vm
+vfncvt_f_xu_w 010010 . ..... 10010 001 ..... 1010111 @r2_vm
+vfncvt_f_x_w 010010 . ..... 10011 001 ..... 1010111 @r2_vm
+vfncvt_f_f_w 010010 . ..... 10100 001 ..... 1010111 @r2_vm
+vfncvt_rod_f_f_w 010010 . ..... 10101 001 ..... 1010111 @r2_vm
+vfncvt_rtz_xu_f_w 010010 . ..... 10110 001 ..... 1010111 @r2_vm
+vfncvt_rtz_x_f_w 010010 . ..... 10111 001 ..... 1010111 @r2_vm
+
vredsum_vs 000000 . ..... ..... 010 ..... 1010111 @r_vm
vredand_vs 000001 . ..... ..... 010 ..... 1010111 @r_vm
vredor_vs 000010 . ..... ..... 010 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index b134a883bb2..6f5c48db0e6 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2853,17 +2853,17 @@ static bool opfv_narrow_check(DisasContext *s, arg_rmr *a)
vext_check_sd(s, a->rd, a->rs2, a->vm);
}
-#define GEN_OPFV_NARROW_TRANS(NAME) \
+#define GEN_OPFV_NARROW_TRANS(NAME, HELPER, FRM) \
static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
{ \
if (opfv_narrow_check(s, a)) { \
uint32_t data = 0; \
static gen_helper_gvec_3_ptr * const fns[2] = { \
- gen_helper_##NAME##_h, \
- gen_helper_##NAME##_w, \
+ gen_helper_##HELPER##_h, \
+ gen_helper_##HELPER##_w, \
}; \
TCGLabel *over = gen_new_label(); \
- gen_set_rm(s, RISCV_FRM_DYN); \
+ gen_set_rm(s, FRM); \
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -2878,11 +2878,51 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
return false; \
}
-GEN_OPFV_NARROW_TRANS(vfncvt_xu_f_v)
-GEN_OPFV_NARROW_TRANS(vfncvt_x_f_v)
-GEN_OPFV_NARROW_TRANS(vfncvt_f_xu_v)
-GEN_OPFV_NARROW_TRANS(vfncvt_f_x_v)
-GEN_OPFV_NARROW_TRANS(vfncvt_f_f_v)
+GEN_OPFV_NARROW_TRANS(vfncvt_f_xu_w, vfncvt_f_xu_w, RISCV_FRM_DYN)
+GEN_OPFV_NARROW_TRANS(vfncvt_f_x_w, vfncvt_f_x_w, RISCV_FRM_DYN)
+GEN_OPFV_NARROW_TRANS(vfncvt_f_f_w, vfncvt_f_f_w, RISCV_FRM_DYN)
+/* Reuse the helper function from vfncvt.f.f.w */
+GEN_OPFV_NARROW_TRANS(vfncvt_rod_f_f_w, vfncvt_f_f_w, RISCV_FRM_ROD)
+
+static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a)
+{
+ return require_rvv(s) &&
+ require_scale_rvf(s) &&
+ vext_check_isa_ill(s) &&
+ /* OPFV narrowing instructions ignore vs1 check */
+ vext_check_sd(s, a->rd, a->rs2, a->vm);
+}
+
+#define GEN_OPXFV_NARROW_TRANS(NAME, HELPER, FRM) \
+static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
+{ \
+ if (opxfv_narrow_check(s, a)) { \
+ uint32_t data = 0; \
+ static gen_helper_gvec_3_ptr * const fns[3] = { \
+ gen_helper_##HELPER##_b, \
+ gen_helper_##HELPER##_h, \
+ gen_helper_##HELPER##_w, \
+ }; \
+ TCGLabel *over = gen_new_label(); \
+ gen_set_rm(s, FRM); \
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ \
+ data = FIELD_DP32(data, VDATA, VM, a->vm); \
+ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
+ vreg_ofs(s, a->rs2), cpu_env, 0, \
+ s->vlen / 8, data, fns[s->sew]); \
+ mark_vs_dirty(s); \
+ gen_set_label(over); \
+ return true; \
+ } \
+ return false; \
+}
+
+GEN_OPXFV_NARROW_TRANS(vfncvt_xu_f_w, vfncvt_xu_f_w, RISCV_FRM_DYN)
+GEN_OPXFV_NARROW_TRANS(vfncvt_x_f_w, vfncvt_x_f_w, RISCV_FRM_DYN)
+/* Reuse the helper functions from vfncvt.xu.f.w and vfncvt.x.f.w */
+GEN_OPXFV_NARROW_TRANS(vfncvt_rtz_xu_f_w, vfncvt_xu_f_w, RISCV_FRM_RTZ)
+GEN_OPXFV_NARROW_TRANS(vfncvt_rtz_x_f_w, vfncvt_x_f_w, RISCV_FRM_RTZ)
/*
*** Vector Reduction Operations
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index e8de460b29b..8d389af4b78 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4029,31 +4029,36 @@ GEN_VEXT_V_ENV(vfwcvt_f_f_v_w, 4, 8)
/* Narrowing Floating-Point/Integer Type-Convert Instructions */
/* (TD, T2, TX2) */
+#define NOP_UU_B uint8_t, uint16_t, uint32_t
#define NOP_UU_H uint16_t, uint32_t, uint32_t
#define NOP_UU_W uint32_t, uint64_t, uint64_t
/* vfncvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer. */
-RVVCALL(OPFVV1, vfncvt_xu_f_v_h, NOP_UU_H, H2, H4, float32_to_uint16)
-RVVCALL(OPFVV1, vfncvt_xu_f_v_w, NOP_UU_W, H4, H8, float64_to_uint32)
-GEN_VEXT_V_ENV(vfncvt_xu_f_v_h, 2, 2)
-GEN_VEXT_V_ENV(vfncvt_xu_f_v_w, 4, 4)
+RVVCALL(OPFVV1, vfncvt_xu_f_w_b, NOP_UU_B, H1, H2, float16_to_uint8)
+RVVCALL(OPFVV1, vfncvt_xu_f_w_h, NOP_UU_H, H2, H4, float32_to_uint16)
+RVVCALL(OPFVV1, vfncvt_xu_f_w_w, NOP_UU_W, H4, H8, float64_to_uint32)
+GEN_VEXT_V_ENV(vfncvt_xu_f_w_b, 1, 1)
+GEN_VEXT_V_ENV(vfncvt_xu_f_w_h, 2, 2)
+GEN_VEXT_V_ENV(vfncvt_xu_f_w_w, 4, 4)
/* vfncvt.x.f.v vd, vs2, vm # Convert double-width float to signed integer. */
-RVVCALL(OPFVV1, vfncvt_x_f_v_h, NOP_UU_H, H2, H4, float32_to_int16)
-RVVCALL(OPFVV1, vfncvt_x_f_v_w, NOP_UU_W, H4, H8, float64_to_int32)
-GEN_VEXT_V_ENV(vfncvt_x_f_v_h, 2, 2)
-GEN_VEXT_V_ENV(vfncvt_x_f_v_w, 4, 4)
+RVVCALL(OPFVV1, vfncvt_x_f_w_b, NOP_UU_B, H1, H2, float16_to_int8)
+RVVCALL(OPFVV1, vfncvt_x_f_w_h, NOP_UU_H, H2, H4, float32_to_int16)
+RVVCALL(OPFVV1, vfncvt_x_f_w_w, NOP_UU_W, H4, H8, float64_to_int32)
+GEN_VEXT_V_ENV(vfncvt_x_f_w_b, 1, 1)
+GEN_VEXT_V_ENV(vfncvt_x_f_w_h, 2, 2)
+GEN_VEXT_V_ENV(vfncvt_x_f_w_w, 4, 4)
/* vfncvt.f.xu.v vd, vs2, vm # Convert double-width unsigned integer to float */
-RVVCALL(OPFVV1, vfncvt_f_xu_v_h, NOP_UU_H, H2, H4, uint32_to_float16)
-RVVCALL(OPFVV1, vfncvt_f_xu_v_w, NOP_UU_W, H4, H8, uint64_to_float32)
-GEN_VEXT_V_ENV(vfncvt_f_xu_v_h, 2, 2)
-GEN_VEXT_V_ENV(vfncvt_f_xu_v_w, 4, 4)
+RVVCALL(OPFVV1, vfncvt_f_xu_w_h, NOP_UU_H, H2, H4, uint32_to_float16)
+RVVCALL(OPFVV1, vfncvt_f_xu_w_w, NOP_UU_W, H4, H8, uint64_to_float32)
+GEN_VEXT_V_ENV(vfncvt_f_xu_w_h, 2, 2)
+GEN_VEXT_V_ENV(vfncvt_f_xu_w_w, 4, 4)
/* vfncvt.f.x.v vd, vs2, vm # Convert double-width integer to float. */
-RVVCALL(OPFVV1, vfncvt_f_x_v_h, NOP_UU_H, H2, H4, int32_to_float16)
-RVVCALL(OPFVV1, vfncvt_f_x_v_w, NOP_UU_W, H4, H8, int64_to_float32)
-GEN_VEXT_V_ENV(vfncvt_f_x_v_h, 2, 2)
-GEN_VEXT_V_ENV(vfncvt_f_x_v_w, 4, 4)
+RVVCALL(OPFVV1, vfncvt_f_x_w_h, NOP_UU_H, H2, H4, int32_to_float16)
+RVVCALL(OPFVV1, vfncvt_f_x_w_w, NOP_UU_W, H4, H8, int64_to_float32)
+GEN_VEXT_V_ENV(vfncvt_f_x_w_h, 2, 2)
+GEN_VEXT_V_ENV(vfncvt_f_x_w_w, 4, 4)
/* vfncvt.f.f.v vd, vs2, vm # Convert double float to single-width float. */
static uint16_t vfncvtffv16(uint32_t a, float_status *s)
@@ -4061,10 +4066,10 @@ static uint16_t vfncvtffv16(uint32_t a, float_status *s)
return float32_to_float16(a, true, s);
}
-RVVCALL(OPFVV1, vfncvt_f_f_v_h, NOP_UU_H, H2, H4, vfncvtffv16)
-RVVCALL(OPFVV1, vfncvt_f_f_v_w, NOP_UU_W, H4, H8, float64_to_float32)
-GEN_VEXT_V_ENV(vfncvt_f_f_v_h, 2, 2)
-GEN_VEXT_V_ENV(vfncvt_f_f_v_w, 4, 4)
+RVVCALL(OPFVV1, vfncvt_f_f_w_h, NOP_UU_H, H2, H4, vfncvtffv16)
+RVVCALL(OPFVV1, vfncvt_f_f_w_w, NOP_UU_W, H4, H8, float64_to_float32)
+GEN_VEXT_V_ENV(vfncvt_f_f_w_h, 2, 2)
+GEN_VEXT_V_ENV(vfncvt_f_f_w_w, 4, 4)
/*
*** Vector Reduction Operations
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 64/75] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (62 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 63/75] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 65/75] target/riscv: rvv-1.0: implement vstart CSR frank.chang
` (10 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
--
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu.h | 2 +-
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
target/riscv/vector_helper.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 367b182735f..ad2497229db 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -103,7 +103,7 @@ typedef struct CPURISCVState CPURISCVState;
#include "pmp.h"
-#define RV_VLEN_MAX 256
+#define RV_VLEN_MAX 1024
FIELD(VTYPE, VLMUL, 0, 3)
FIELD(VTYPE, VSEW, 3, 3)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 6f5c48db0e6..1f6cd7f97c6 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -613,8 +613,8 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
base = tcg_temp_new();
/*
- * As simd_desc supports at most 256 bytes, and in this implementation,
- * the max vector group length is 2048 bytes. So split it into two parts.
+ * As simd_desc supports at most 2048 bytes, and in this implementation,
+ * the max vector group length is 4096 bytes. So split it into two parts.
*
* The first part is vlen in bytes, encoded in maxsz of simd_desc.
* The second part is lmul, encoded in data of simd_desc.
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 8d389af4b78..16331939b64 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -129,7 +129,7 @@ static uint32_t vext_wd(uint32_t desc)
static inline uint32_t vext_max_elems(uint32_t desc, uint32_t esz)
{
/*
- * As simd_desc support at most 256 bytes, the max vlen is 256 bits.
+ * As simd_desc support at most 2048 bytes, the max vlen is 1024 bits.
* so vlen in bytes (vlenb) is encoded as maxsz.
*/
uint32_t vlenb = simd_maxsz(desc);
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 65/75] target/riscv: rvv-1.0: implement vstart CSR
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (63 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 64/75] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 66/75] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid frank.chang
` (9 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
* Update and check vstart value for vector instructions.
* Add whole register move instruction helper functions as we have to
call helper function for case where vstart is not zero.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
--
Perhaps we can remove the probe functions in vector_helper.c to align with
the hardware's behavior, which raise the memory access exceptions and
update vstart value at the exact processing vector element.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/csr.c | 6 +-
target/riscv/helper.h | 5 +
target/riscv/insn_trans/trans_rvv.c.inc | 73 ++++++---
target/riscv/translate.c | 6 +-
target/riscv/vector_helper.c | 201 +++++++++++++++++-------
5 files changed, 206 insertions(+), 85 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index a6a535f7e33..aa76da9e185 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -334,7 +334,11 @@ static int write_vstart(CPURISCVState *env, int csrno, target_ulong val)
env->mstatus |= MSTATUS_VS;
#endif
- env->vstart = val;
+ /*
+ * The vstart CSR is defined to have only enough writable bits
+ * to hold the largest element index, i.e. lg2(VLEN) bits.
+ */
+ env->vstart = val & ~(~0ULL << ctzl(env_archcpu(env)->cfg.vlen));
return 0;
}
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 6eb4033d654..78f330b949e 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1114,6 +1114,11 @@ DEF_HELPER_6(vcompress_vm_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vcompress_vm_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vcompress_vm_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_4(vmv1r_v, void, ptr, ptr, env, i32)
+DEF_HELPER_4(vmv2r_v, void, ptr, ptr, env, i32)
+DEF_HELPER_4(vmv4r_v, void, ptr, ptr, env, i32)
+DEF_HELPER_4(vmv8r_v, void, ptr, ptr, env, i32)
+
DEF_HELPER_5(vzext_vf2_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vzext_vf2_w, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vzext_vf2_d, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 1f6cd7f97c6..03245f67c4b 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3014,7 +3014,8 @@ GEN_MM_TRANS(vmxnor_mm)
static bool trans_vpopc_m(DisasContext *s, arg_rmr *a)
{
if (require_rvv(s) &&
- vext_check_isa_ill(s)) {
+ vext_check_isa_ill(s) &&
+ s->vstart == 0) {
TCGv_ptr src2, mask;
TCGv dst;
TCGv_i32 desc;
@@ -3047,7 +3048,8 @@ static bool trans_vpopc_m(DisasContext *s, arg_rmr *a)
static bool trans_vfirst_m(DisasContext *s, arg_rmr *a)
{
if (require_rvv(s) &&
- vext_check_isa_ill(s)) {
+ vext_check_isa_ill(s) &&
+ s->vstart == 0) {
TCGv_ptr src2, mask;
TCGv dst;
TCGv_i32 desc;
@@ -3084,7 +3086,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
if (require_rvv(s) && \
vext_check_isa_ill(s) && \
require_vm(a->vm, a->rd) && \
- (a->rd != a->rs2)) { \
+ (a->rd != a->rs2) && \
+ (s->vstart == 0)) { \
uint32_t data = 0; \
gen_helper_gvec_3_ptr *fn = gen_helper_##NAME; \
TCGLabel *over = gen_new_label(); \
@@ -3119,7 +3122,8 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
vext_check_isa_ill(s) &&
!is_overlapped(a->rd, 1 << MAX(s->lmul, 0), a->rs2, 1) &&
require_vm(a->vm, a->rd) &&
- require_align(a->rd, s->lmul)) {
+ require_align(a->rd, s->lmul) &&
+ (s->vstart == 0)) {
uint32_t data = 0;
TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
@@ -3341,6 +3345,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
t1 = tcg_temp_new_i64();
s1 = tcg_temp_new();
@@ -3396,8 +3401,9 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
TCGv_i64 t1;
TCGLabel *over = gen_new_label();
- /* if vl == 0, skip vector register write back */
+ /* if vl == 0 or vstart >= vl, skip vector register write back */
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
/* NaN-box f[rs1] */
t1 = tcg_temp_new_i64();
@@ -3563,7 +3569,8 @@ static bool vcompress_vm_check(DisasContext *s, arg_r *a)
require_align(a->rd, s->lmul) &&
require_align(a->rs2, s->lmul) &&
(a->rd != a->rs2) &&
- require_noover(a->rd, s->lmul, a->rs1, 0);
+ require_noover(a->rd, s->lmul, a->rs1, 0) &&
+ (s->vstart == 0);
}
static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
@@ -3592,26 +3599,40 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
* Whole Vector Register Move Instructions ignore vtype and vl setting.
* Thus, we don't need to check vill bit. (Section 17.6)
*/
-#define GEN_VMV_WHOLE_TRANS(NAME, LEN) \
-static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
-{ \
- if (require_rvv(s) && \
- QEMU_IS_ALIGNED(a->rd, LEN) && \
- QEMU_IS_ALIGNED(a->rs2, LEN)) { \
- /* EEW = 8 */ \
- tcg_gen_gvec_mov(MO_8, vreg_ofs(s, a->rd), \
- vreg_ofs(s, a->rs2), \
- s->vlen / 8 * LEN, s->vlen / 8 * LEN); \
- mark_vs_dirty(s); \
- return true; \
- } \
- return false; \
-}
-
-GEN_VMV_WHOLE_TRANS(vmv1r_v, 1)
-GEN_VMV_WHOLE_TRANS(vmv2r_v, 2)
-GEN_VMV_WHOLE_TRANS(vmv4r_v, 4)
-GEN_VMV_WHOLE_TRANS(vmv8r_v, 8)
+#define GEN_VMV_WHOLE_TRANS(NAME, LEN, SEQ) \
+static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
+{ \
+ if (require_rvv(s) && \
+ QEMU_IS_ALIGNED(a->rd, LEN) && \
+ QEMU_IS_ALIGNED(a->rs2, LEN)) { \
+ uint32_t maxsz = (s->vlen >> 3) * LEN; \
+ if (s->vstart == 0) { \
+ /* EEW = 8 */ \
+ tcg_gen_gvec_mov(MO_8, vreg_ofs(s, a->rd), \
+ vreg_ofs(s, a->rs2), maxsz, maxsz); \
+ mark_vs_dirty(s); \
+ } else { \
+ TCGLabel *over = gen_new_label(); \
+ tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, maxsz, over); \
+ \
+ static gen_helper_gvec_2_ptr * const fns[4] = { \
+ gen_helper_vmv1r_v, gen_helper_vmv2r_v, \
+ gen_helper_vmv4r_v, gen_helper_vmv8r_v, \
+ }; \
+ tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), \
+ cpu_env, 0, maxsz, 0, fns[SEQ]); \
+ mark_vs_dirty(s); \
+ gen_set_label(over); \
+ } \
+ return true; \
+ } \
+ return false; \
+}
+
+GEN_VMV_WHOLE_TRANS(vmv1r_v, 1, 0)
+GEN_VMV_WHOLE_TRANS(vmv2r_v, 2, 1)
+GEN_VMV_WHOLE_TRANS(vmv4r_v, 4, 2)
+GEN_VMV_WHOLE_TRANS(vmv8r_v, 8, 3)
static bool int_ext_check(DisasContext *s, arg_rmr *a, uint8_t div)
{
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index b9da55c75a8..5590f8d3c7c 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -33,7 +33,7 @@
#include "internals.h"
/* global register indices */
-static TCGv cpu_gpr[32], cpu_pc, cpu_vl;
+static TCGv cpu_gpr[32], cpu_pc, cpu_vl, cpu_vstart;
static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
static TCGv load_res;
static TCGv load_val;
@@ -76,6 +76,7 @@ typedef struct DisasContext {
int8_t lmul;
uint8_t sew;
uint16_t vlen;
+ target_ulong vstart;
bool vl_eq_vlmax;
CPUState *cs;
} DisasContext;
@@ -881,6 +882,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);
ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3);
+ ctx->vstart = env->vstart;
ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
ctx->cs = cs;
}
@@ -998,6 +1000,8 @@ void riscv_translate_init(void)
cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc");
cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl");
+ cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart),
+ "vstart");
load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res),
"load_res");
load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val),
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 16331939b64..efa32565d9a 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -232,14 +232,14 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
uint32_t max_elems = vext_max_elems(desc, esz);
/* probe every access*/
- for (i = 0; i < env->vl; i++) {
+ for (i = env->vstart; i < env->vl; i++) {
if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
probe_pages(env, base + stride * i, nf << esz, ra, access_type);
}
/* do real access */
- for (i = 0; i < env->vl; i++) {
+ for (i = env->vstart; i < env->vl; i++) {
k = 0;
if (!vm && !vext_elem_mask(v0, i)) {
continue;
@@ -249,7 +249,9 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base,
ldst_elem(env, addr, i + k * max_elems, vd, ra);
k++;
}
+ env->vstart = i;
}
+ env->vstart = 0;
}
#define GEN_VEXT_LD_STRIDE(NAME, ETYPE, LOAD_FN) \
@@ -299,14 +301,16 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
/* probe every access */
probe_pages(env, base, env->vl * (nf << esz), ra, access_type);
/* load bytes from guest memory */
- for (i = 0; i < env->vl; i++) {
+ for (i = env->vstart; i < env->vl; i++) {
k = 0;
while (k < nf) {
target_ulong addr = base + ((i * nf + k) << esz);
ldst_elem(env, addr, i + k * max_elems, vd, ra);
k++;
}
+ env->vstart = i;
}
+ env->vstart = 0;
}
/*
@@ -387,7 +391,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
uint32_t max_elems = vext_max_elems(desc, esz);
/* probe every access*/
- for (i = 0; i < env->vl; i++) {
+ for (i = env->vstart; i < env->vl; i++) {
if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
@@ -395,7 +399,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
access_type);
}
/* load bytes from guest memory */
- for (i = 0; i < env->vl; i++) {
+ for (i = env->vstart; i < env->vl; i++) {
k = 0;
if (!vm && !vext_elem_mask(v0, i)) {
continue;
@@ -405,7 +409,9 @@ vext_ldst_index(void *vd, void *v0, target_ulong base,
ldst_elem(env, addr, i + k * max_elems, vd, ra);
k++;
}
+ env->vstart = i;
}
+ env->vstart = 0;
}
#define GEN_VEXT_LD_INDEX(NAME, ETYPE, INDEX_FN, LOAD_FN) \
@@ -476,7 +482,7 @@ vext_ldff(void *vd, void *v0, target_ulong base,
target_ulong addr, offset, remain;
/* probe every access*/
- for (i = 0; i < env->vl; i++) {
+ for (i = env->vstart; i < env->vl; i++) {
if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
@@ -516,7 +522,7 @@ ProbeSuccess:
if (vl != 0) {
env->vl = vl;
}
- for (i = 0; i < env->vl; i++) {
+ for (i = env->vstart; i < env->vl; i++) {
k = 0;
if (!vm && !vext_elem_mask(v0, i)) {
continue;
@@ -527,6 +533,7 @@ ProbeSuccess:
k++;
}
}
+ env->vstart = 0;
}
#define GEN_VEXT_LDFF(NAME, ETYPE, LOAD_FN) \
@@ -550,21 +557,37 @@ vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
vext_ldst_elem_fn *ldst_elem, uint32_t esz, uintptr_t ra,
MMUAccessType access_type)
{
- uint32_t i, k;
+ uint32_t i, k, off, pos;
uint32_t nf = vext_nf(desc);
uint32_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
uint32_t max_elems = vlenb >> esz;
/* probe every access */
- probe_pages(env, base, vlenb * nf, ra, access_type);
+ probe_pages(env, base, max_elems * nf, ra, access_type);
- /* load bytes from guest memory */
- for (k = 0; k < nf; k++) {
+ k = env->vstart / max_elems;
+ off = env->vstart % max_elems;
+
+ if (off) {
+ /* load/store rest of elements of current segment pointed by vstart */
+ for (pos = off; pos < max_elems; pos++) {
+ target_ulong addr = base + ((pos + k * max_elems) << esz);
+ ldst_elem(env, addr, pos + k * max_elems, vd, ra);
+ env->vstart++;
+ }
+ k++;
+ }
+
+ /* load/store elements for rest of segments */
+ for (; k < nf; k++) {
for (i = 0; i < max_elems; i++) {
target_ulong addr = base + ((i + k * max_elems) << esz);
ldst_elem(env, addr, i + k * max_elems, vd, ra);
+ env->vstart++;
}
}
+
+ env->vstart = 0;
}
#define GEN_VEXT_LD_WHOLE(NAME, ETYPE, LOAD_FN) \
@@ -725,20 +748,21 @@ vext_amo_noatomic(void *vs3, void *v0, target_ulong base,
uint32_t wd = vext_wd(desc);
uint32_t vm = vext_vm(desc);
- for (i = 0; i < env->vl; i++) {
+ for (i = env->vstart; i < env->vl; i++) {
if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
probe_pages(env, get_index_addr(base, i, vs2), esz, ra, MMU_DATA_LOAD);
probe_pages(env, get_index_addr(base, i, vs2), esz, ra, MMU_DATA_STORE);
}
- for (i = 0; i < env->vl; i++) {
+ for (i = env->vstart; i < env->vl; i++) {
if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
addr = get_index_addr(base, i, vs2);
noatomic_op(vs3, addr, wd, i, env, ra);
}
+ env->vstart = 0;
}
#define GEN_VEXT_AMO(NAME, ETYPE, INDEX_FN) \
@@ -895,12 +919,13 @@ static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2,
uint32_t vl = env->vl;
uint32_t i;
- for (i = 0; i < vl; i++) {
+ for (i = env->vstart; i < vl; i++) {
if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
fn(vd, vs1, vs2, i);
}
+ env->vstart = 0;
}
/* generate the helpers for OPIVV */
@@ -957,12 +982,13 @@ static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2,
uint32_t vl = env->vl;
uint32_t i;
- for (i = 0; i < vl; i++) {
+ for (i = env->vstart; i < vl; i++) {
if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
fn(vd, s1, vs2, i);
}
+ env->vstart = 0;
}
/* generate the helpers for OPIVX */
@@ -1150,13 +1176,14 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
uint32_t vl = env->vl; \
uint32_t i; \
\
- for (i = 0; i < vl; i++) { \
+ for (i = env->vstart; i < vl; i++) { \
ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
ETYPE carry = vext_elem_mask(v0, i); \
\
*((ETYPE *)vd + H(i)) = DO_OP(s2, s1, carry); \
} \
+ env->vstart = 0; \
}
GEN_VEXT_VADC_VVM(vadc_vvm_b, uint8_t, H1, DO_VADC)
@@ -1176,12 +1203,13 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
uint32_t vl = env->vl; \
uint32_t i; \
\
- for (i = 0; i < vl; i++) { \
+ for (i = env->vstart; i < vl; i++) { \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
ETYPE carry = vext_elem_mask(v0, i); \
\
*((ETYPE *)vd + H(i)) = DO_OP(s2, (ETYPE)(target_long)s1, carry);\
} \
+ env->vstart = 0; \
}
GEN_VEXT_VADC_VXM(vadc_vxm_b, uint8_t, H1, DO_VADC)
@@ -1206,12 +1234,13 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
uint32_t vm = vext_vm(desc); \
uint32_t i; \
\
- for (i = 0; i < vl; i++) { \
+ for (i = env->vstart; i < vl; i++) { \
ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
ETYPE carry = !vm && vext_elem_mask(v0, i); \
vext_set_elem_mask(vd, i, DO_OP(s2, s1, carry)); \
} \
+ env->vstart = 0; \
}
GEN_VEXT_VMADC_VVM(vmadc_vvm_b, uint8_t, H1, DO_MADC)
@@ -1232,12 +1261,13 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
uint32_t vm = vext_vm(desc); \
uint32_t i; \
\
- for (i = 0; i < vl; i++) { \
+ for (i = env->vstart; i < vl; i++) { \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
ETYPE carry = !vm && vext_elem_mask(v0, i); \
vext_set_elem_mask(vd, i, \
DO_OP(s2, (ETYPE)(target_long)s1, carry)); \
} \
+ env->vstart = 0; \
}
GEN_VEXT_VMADC_VXM(vmadc_vxm_b, uint8_t, H1, DO_MADC)
@@ -1314,7 +1344,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
uint32_t vl = env->vl; \
uint32_t i; \
\
- for (i = 0; i < vl; i++) { \
+ for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
@@ -1322,6 +1352,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
*((TS1 *)vd + HS1(i)) = OP(s2, s1 & MASK); \
} \
+ env->vstart = 0; \
}
GEN_VEXT_SHIFT_VV(vsll_vv_b, uint8_t, uint8_t, H1, H1, DO_SLL, 0x7)
@@ -1348,13 +1379,14 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
uint32_t vl = env->vl; \
uint32_t i; \
\
- for (i = 0; i < vl; i++) { \
+ for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
*((TD *)vd + HD(i)) = OP(s2, s1 & MASK); \
} \
+ env->vstart = 0; \
}
GEN_VEXT_SHIFT_VX(vsll_vx_b, uint8_t, int8_t, H1, H1, DO_SLL, 0x7)
@@ -1401,7 +1433,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
uint32_t vl = env->vl; \
uint32_t i; \
\
- for (i = 0; i < vl; i++) { \
+ for (i = env->vstart; i < vl; i++) { \
ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
if (!vm && !vext_elem_mask(v0, i)) { \
@@ -1409,6 +1441,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
} \
vext_set_elem_mask(vd, i, DO_OP(s2, s1)); \
} \
+ env->vstart = 0; \
}
GEN_VEXT_CMP_VV(vmseq_vv_b, uint8_t, H1, DO_MSEQ)
@@ -1449,7 +1482,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
uint32_t vl = env->vl; \
uint32_t i; \
\
- for (i = 0; i < vl; i++) { \
+ for (i = env->vstart; i < vl; i++) { \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
@@ -1457,6 +1490,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
vext_set_elem_mask(vd, i, \
DO_OP(s2, (ETYPE)(target_long)s1)); \
} \
+ env->vstart = 0; \
}
GEN_VEXT_CMP_VX(vmseq_vx_b, uint8_t, H1, DO_MSEQ)
@@ -1979,10 +2013,11 @@ void HELPER(NAME)(void *vd, void *vs1, CPURISCVState *env, \
uint32_t vl = env->vl; \
uint32_t i; \
\
- for (i = 0; i < vl; i++) { \
+ for (i = env->vstart; i < vl; i++) { \
ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
*((ETYPE *)vd + H(i)) = s1; \
} \
+ env->vstart = 0; \
}
GEN_VEXT_VMV_VV(vmv_v_v_b, int8_t, H1)
@@ -1997,9 +2032,10 @@ void HELPER(NAME)(void *vd, uint64_t s1, CPURISCVState *env, \
uint32_t vl = env->vl; \
uint32_t i; \
\
- for (i = 0; i < vl; i++) { \
+ for (i = env->vstart; i < vl; i++) { \
*((ETYPE *)vd + H(i)) = (ETYPE)s1; \
} \
+ env->vstart = 0; \
}
GEN_VEXT_VMV_VX(vmv_v_x_b, int8_t, H1)
@@ -2014,10 +2050,11 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
uint32_t vl = env->vl; \
uint32_t i; \
\
- for (i = 0; i < vl; i++) { \
+ for (i = env->vstart; i < vl; i++) { \
ETYPE *vt = (!vext_elem_mask(v0, i) ? vs2 : vs1); \
*((ETYPE *)vd + H(i)) = *(vt + H(i)); \
} \
+ env->vstart = 0; \
}
GEN_VEXT_VMERGE_VV(vmerge_vvm_b, int8_t, H1)
@@ -2032,12 +2069,13 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \
uint32_t vl = env->vl; \
uint32_t i; \
\
- for (i = 0; i < vl; i++) { \
+ for (i = env->vstart; i < vl; i++) { \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
ETYPE d = (!vext_elem_mask(v0, i) ? s2 : \
(ETYPE)(target_long)s1); \
*((ETYPE *)vd + H(i)) = d; \
} \
+ env->vstart = 0; \
}
GEN_VEXT_VMERGE_VX(vmerge_vxm_b, int8_t, H1)
@@ -2074,12 +2112,13 @@ vext_vv_rm_1(void *vd, void *v0, void *vs1, void *vs2,
uint32_t vl, uint32_t vm, int vxrm,
opivv2_rm_fn *fn)
{
- for (uint32_t i = 0; i < vl; i++) {
+ for (uint32_t i = env->vstart; i < vl; i++) {
if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
fn(vd, vs1, vs2, i, env, vxrm);
}
+ env->vstart = 0;
}
static inline void
@@ -2190,12 +2229,13 @@ vext_vx_rm_1(void *vd, void *v0, target_long s1, void *vs2,
uint32_t vl, uint32_t vm, int vxrm,
opivx2_rm_fn *fn)
{
- for (uint32_t i = 0; i < vl; i++) {
+ for (uint32_t i = env->vstart; i < vl; i++) {
if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
fn(vd, s1, vs2, i, env, vxrm);
}
+ env->vstart = 0;
}
static inline void
@@ -2977,12 +3017,13 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
uint32_t vl = env->vl; \
uint32_t i; \
\
- for (i = 0; i < vl; i++) { \
+ for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
do_##NAME(vd, vs1, vs2, i, env); \
} \
+ env->vstart = 0; \
}
RVVCALL(OPFVV2, vfadd_vv_h, OP_UUU_H, H2, H2, H2, float16_add)
@@ -3009,12 +3050,13 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, \
uint32_t vl = env->vl; \
uint32_t i; \
\
- for (i = 0; i < vl; i++) { \
+ for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
do_##NAME(vd, s1, vs2, i, env); \
} \
+ env->vstart = 0; \
}
RVVCALL(OPFVF2, vfadd_vf_h, OP_UUU_H, H2, H2, float16_add)
@@ -3580,12 +3622,13 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \
if (vl == 0) { \
return; \
} \
- for (i = 0; i < vl; i++) { \
+ for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
do_##NAME(vd, vs2, i, env); \
} \
+ env->vstart = 0; \
}
RVVCALL(OPFVV1, vfsqrt_v_h, OP_UU_H, H2, H2, float16_sqrt)
@@ -3716,7 +3759,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
uint32_t vl = env->vl; \
uint32_t i; \
\
- for (i = 0; i < vl; i++) { \
+ for (i = env->vstart; i < vl; i++) { \
ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
if (!vm && !vext_elem_mask(v0, i)) { \
@@ -3725,6 +3768,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
vext_set_elem_mask(vd, i, \
DO_OP(s2, s1, &env->fp_status)); \
} \
+ env->vstart = 0; \
}
GEN_VEXT_CMP_VV_ENV(vmfeq_vv_h, uint16_t, H2, float16_eq_quiet)
@@ -3739,7 +3783,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
uint32_t vl = env->vl; \
uint32_t i; \
\
- for (i = 0; i < vl; i++) { \
+ for (i = env->vstart; i < vl; i++) { \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
@@ -3747,6 +3791,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
vext_set_elem_mask(vd, i, \
DO_OP(s2, (ETYPE)s1, &env->fp_status)); \
} \
+ env->vstart = 0; \
}
GEN_VEXT_CMP_VF(vmfeq_vf_h, uint16_t, H2, float16_eq_quiet)
@@ -3855,12 +3900,13 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \
uint32_t vl = env->vl; \
uint32_t i; \
\
- for (i = 0; i < vl; i++) { \
+ for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
do_##NAME(vd, vs2, i); \
} \
+ env->vstart = 0; \
}
target_ulong fclass_h(uint64_t frs1)
@@ -3936,11 +3982,12 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
uint32_t vl = env->vl; \
uint32_t i; \
\
- for (i = 0; i < vl; i++) { \
+ for (i = env->vstart; i < vl; i++) { \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
*((ETYPE *)vd + H(i)) \
= (!vm && !vext_elem_mask(v0, i) ? s2 : s1); \
} \
+ env->vstart = 0; \
}
GEN_VFMERGE_VF(vfmerge_vfm_h, int16_t, H2)
@@ -4084,7 +4131,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
uint32_t i; \
TD s1 = *((TD *)vs1 + HD(0)); \
\
- for (i = 0; i < vl; i++) { \
+ for (i = env->vstart; i < vl; i++) { \
TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
@@ -4092,6 +4139,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
s1 = OP(s1, (TD)s2); \
} \
*((TD *)vd + HD(0)) = s1; \
+ env->vstart = 0; \
}
/* vd[0] = sum(vs1[0], vs2[*]) */
@@ -4164,7 +4212,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
uint32_t i; \
TD s1 = *((TD *)vs1 + HD(0)); \
\
- for (i = 0; i < vl; i++) { \
+ for (i = env->vstart; i < vl; i++) { \
TS2 s2 = *((TS2 *)vs2 + HS2(i)); \
if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
@@ -4172,6 +4220,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
s1 = OP(s1, (TD)s2, &env->fp_status); \
} \
*((TD *)vd + HD(0)) = s1; \
+ env->vstart = 0; \
}
/* Unordered sum */
@@ -4199,7 +4248,7 @@ void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1,
uint32_t i;
uint32_t s1 = *((uint32_t *)vs1 + H4(0));
- for (i = 0; i < vl; i++) {
+ for (i = env->vstart; i < vl; i++) {
uint16_t s2 = *((uint16_t *)vs2 + H2(i));
if (!vm && !vext_elem_mask(v0, i)) {
continue;
@@ -4208,6 +4257,7 @@ void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1,
&env->fp_status);
}
*((uint32_t *)vd + H4(0)) = s1;
+ env->vstart = 0;
}
void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1,
@@ -4218,7 +4268,7 @@ void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1,
uint32_t i;
uint64_t s1 = *((uint64_t *)vs1);
- for (i = 0; i < vl; i++) {
+ for (i = env->vstart; i < vl; i++) {
uint32_t s2 = *((uint32_t *)vs2 + H4(i));
if (!vm && !vext_elem_mask(v0, i)) {
continue;
@@ -4227,6 +4277,7 @@ void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1,
&env->fp_status);
}
*((uint64_t *)vd) = s1;
+ env->vstart = 0;
}
/*
@@ -4242,11 +4293,12 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \
uint32_t i; \
int a, b; \
\
- for (i = 0; i < vl; i++) { \
+ for (i = env->vstart; i < vl; i++) { \
a = vext_elem_mask(vs1, i); \
b = vext_elem_mask(vs2, i); \
vext_set_elem_mask(vd, i, OP(b, a)); \
} \
+ env->vstart = 0; \
}
#define DO_NAND(N, M) (!(N & M))
@@ -4273,13 +4325,14 @@ target_ulong HELPER(vpopc_m)(void *v0, void *vs2, CPURISCVState *env,
uint32_t vl = env->vl;
int i;
- for (i = 0; i < vl; i++) {
+ for (i = env->vstart; i < vl; i++) {
if (vm || vext_elem_mask(v0, i)) {
if (vext_elem_mask(vs2, i)) {
cnt++;
}
}
}
+ env->vstart = 0;
return cnt;
}
@@ -4291,13 +4344,14 @@ target_ulong HELPER(vfirst_m)(void *v0, void *vs2, CPURISCVState *env,
uint32_t vl = env->vl;
int i;
- for (i = 0; i < vl; i++) {
+ for (i = env->vstart; i < vl; i++) {
if (vm || vext_elem_mask(v0, i)) {
if (vext_elem_mask(vs2, i)) {
return i;
}
}
}
+ env->vstart = 0;
return -1LL;
}
@@ -4315,7 +4369,7 @@ static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env,
int i;
bool first_mask_bit = false;
- for (i = 0; i < vl; i++) {
+ for (i = env->vstart; i < vl; i++) {
if (!vm && !vext_elem_mask(v0, i)) {
continue;
}
@@ -4339,6 +4393,7 @@ static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env,
}
}
}
+ env->vstart = 0;
}
void HELPER(vmsbf_m)(void *vd, void *v0, void *vs2, CPURISCVState *env,
@@ -4369,7 +4424,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, CPURISCVState *env, \
uint32_t sum = 0; \
int i; \
\
- for (i = 0; i < vl; i++) { \
+ for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
@@ -4378,6 +4433,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, CPURISCVState *env, \
sum++; \
} \
} \
+ env->vstart = 0; \
}
GEN_VEXT_VIOTA_M(viota_m_b, uint8_t, H1)
@@ -4393,12 +4449,13 @@ void HELPER(NAME)(void *vd, void *v0, CPURISCVState *env, uint32_t desc) \
uint32_t vl = env->vl; \
int i; \
\
- for (i = 0; i < vl; i++) { \
+ for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
*((ETYPE *)vd + H(i)) = i; \
} \
+ env->vstart = 0; \
}
GEN_VEXT_VID_V(vid_v_b, uint8_t, H1)
@@ -4417,9 +4474,10 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
{ \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
- target_ulong offset = s1, i; \
+ target_ulong offset = s1, i_min, i; \
\
- for (i = offset; i < vl; i++) { \
+ i_min = MAX(env->vstart, offset); \
+ for (i = i_min; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
@@ -4442,8 +4500,8 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
uint32_t vl = env->vl; \
target_ulong i_max, i; \
\
- i_max = MIN(s1 < vlmax ? vlmax - s1 : 0, vl); \
- for (i = 0; i < i_max; ++i) { \
+ i_max = MAX(MIN(s1 < vlmax ? vlmax - s1 : 0, vl), env->vstart); \
+ for (i = env->vstart; i < i_max; ++i) { \
if (vm || vext_elem_mask(v0, i)) { \
*((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i + s1)); \
} \
@@ -4454,6 +4512,8 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
*((ETYPE *)vd + H(i)) = 0; \
} \
} \
+ \
+ env->vstart = 0; \
}
/* vslidedown.vx vd, vs2, rs1, vm # vd[i] = vs2[i+rs1] */
@@ -4471,7 +4531,7 @@ static void vslide1up_##ESZ(void *vd, void *v0, target_ulong s1, void *vs2, \
uint32_t vl = env->vl; \
uint32_t i; \
\
- for (i = 0; i < vl; i++) { \
+ for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
@@ -4481,6 +4541,7 @@ static void vslide1up_##ESZ(void *vd, void *v0, target_ulong s1, void *vs2, \
*((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - 1)); \
} \
} \
+ env->vstart = 0; \
}
GEN_VEXT_VSLIE1UP(8, H1)
@@ -4510,7 +4571,7 @@ static void vslide1down_##ESZ(void *vd, void *v0, target_ulong s1, void *vs2, \
uint32_t vl = env->vl; \
uint32_t i; \
\
- for (i = 0; i < vl; i++) { \
+ for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
@@ -4520,6 +4581,7 @@ static void vslide1down_##ESZ(void *vd, void *v0, target_ulong s1, void *vs2, \
*((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i + 1)); \
} \
} \
+ env->vstart = 0; \
}
GEN_VEXT_VSLIDE1DOWN(8, H1)
@@ -4570,12 +4632,12 @@ GEN_VEXT_VFSLIDE1DOWN_VF(vfslide1down_vf_d, 64)
void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
CPURISCVState *env, uint32_t desc) \
{ \
- uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(TS1))); \
+ uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(TS2))); \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t index, i; \
\
- for (i = 0; i < vl; i++) { \
+ for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
@@ -4586,6 +4648,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
*((TS2 *)vd + HS2(i)) = *((TS2 *)vs2 + HS2(index)); \
} \
} \
+ env->vstart = 0; \
}
/* vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]]; */
@@ -4608,7 +4671,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
uint32_t vl = env->vl; \
uint32_t index = s1, i; \
\
- for (i = 0; i < vl; i++) { \
+ for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
@@ -4618,6 +4681,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
*((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(index)); \
} \
} \
+ env->vstart = 0; \
}
/* vd[i] = (x[rs1] >= VLMAX) ? 0 : vs2[rs1] */
@@ -4634,13 +4698,14 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \
uint32_t vl = env->vl; \
uint32_t num = 0, i; \
\
- for (i = 0; i < vl; i++) { \
+ for (i = env->vstart; i < vl; i++) { \
if (!vext_elem_mask(vs1, i)) { \
continue; \
} \
*((ETYPE *)vd + H(num)) = *((ETYPE *)vs2 + H(i)); \
num++; \
} \
+ env->vstart = 0; \
}
/* Compress into vd elements of vs2 where vs1 is enabled */
@@ -4649,6 +4714,27 @@ GEN_VEXT_VCOMPRESS_VM(vcompress_vm_h, uint16_t, H2)
GEN_VEXT_VCOMPRESS_VM(vcompress_vm_w, uint32_t, H4)
GEN_VEXT_VCOMPRESS_VM(vcompress_vm_d, uint64_t, H8)
+/* Vector Whole Register Move */
+#define GEN_VEXT_VMV_WHOLE(NAME, LEN) \
+void HELPER(NAME)(void *vd, void *vs2, CPURISCVState *env, \
+ uint32_t desc) \
+{ \
+ /* EEW = 8 */ \
+ uint32_t maxsz = simd_maxsz(desc); \
+ uint32_t i = env->vstart; \
+ \
+ memcpy((uint8_t *)vd + H1(i), \
+ (uint8_t *)vs2 + H1(i), \
+ maxsz - env->vstart); \
+ \
+ env->vstart = 0; \
+}
+
+GEN_VEXT_VMV_WHOLE(vmv1r_v, 1)
+GEN_VEXT_VMV_WHOLE(vmv2r_v, 2)
+GEN_VEXT_VMV_WHOLE(vmv4r_v, 4)
+GEN_VEXT_VMV_WHOLE(vmv8r_v, 8)
+
/* Vector Integer Extension */
#define GEN_VEXT_INT_EXT(NAME, ETYPE, DTYPE, HD, HS1) \
void HELPER(NAME)(void *vd, void *v0, void *vs2, \
@@ -4658,12 +4744,13 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \
uint32_t vm = vext_vm(desc); \
uint32_t i; \
\
- for (i = 0; i < vl; i++) { \
+ for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
continue; \
} \
*((ETYPE *)vd + HD(i)) = *((DTYPE *)vs2 + HS1(i)); \
} \
+ env->vstart = 0; \
}
GEN_VEXT_INT_EXT(vzext_vf2_h, uint16_t, uint8_t, H2, H1)
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 66/75] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (64 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 65/75] target/riscv: rvv-1.0: implement vstart CSR frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 67/75] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs frank.chang
` (8 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
If the frm field contains an invalid rounding mode (101-111),
attempting to execute any vector floating-point instruction, even
those that do not depend on the rounding mode, will raise an illegal
instruction exception.
Call gen_set_rm() with DYN rounding mode to check and trigger illegal
instruction exception if frm field contains invalid value at run-time
for vector floating-point instructions.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 03245f67c4b..2a3a437168f 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2605,6 +2605,10 @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
int rm)
{
if (checkfn(s, a)) {
+ if (rm != RISCV_FRM_DYN) {
+ gen_set_rm(s, RISCV_FRM_DYN);
+ }
+
uint32_t data = 0;
TCGLabel *over = gen_new_label();
gen_set_rm(s, rm);
@@ -2690,6 +2694,8 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
require_rvf(s) &&
vext_check_isa_ill(s) &&
require_align(a->rd, s->lmul)) {
+ gen_set_rm(s, RISCV_FRM_DYN);
+
TCGv_i64 t1;
if (s->vl_eq_vlmax) {
@@ -2772,6 +2778,10 @@ static bool opfv_widen_check(DisasContext *s, arg_rmr *a)
static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
{ \
if (opfv_widen_check(s, a)) { \
+ if (FRM != RISCV_FRM_DYN) { \
+ gen_set_rm(s, RISCV_FRM_DYN); \
+ } \
+ \
uint32_t data = 0; \
static gen_helper_gvec_3_ptr * const fns[2] = { \
gen_helper_##HELPER##_h, \
@@ -2857,6 +2867,10 @@ static bool opfv_narrow_check(DisasContext *s, arg_rmr *a)
static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
{ \
if (opfv_narrow_check(s, a)) { \
+ if (FRM != RISCV_FRM_DYN) { \
+ gen_set_rm(s, RISCV_FRM_DYN); \
+ } \
+ \
uint32_t data = 0; \
static gen_helper_gvec_3_ptr * const fns[2] = { \
gen_helper_##HELPER##_h, \
@@ -2897,6 +2911,10 @@ static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a)
static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
{ \
if (opxfv_narrow_check(s, a)) { \
+ if (FRM != RISCV_FRM_DYN) { \
+ gen_set_rm(s, RISCV_FRM_DYN); \
+ } \
+ \
uint32_t data = 0; \
static gen_helper_gvec_3_ptr * const fns[3] = { \
gen_helper_##HELPER##_b, \
@@ -3372,6 +3390,8 @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a)
if (require_rvv(s) &&
require_rvf(s) &&
vext_check_isa_ill(s)) {
+ gen_set_rm(s, RISCV_FRM_DYN);
+
unsigned int ofs = (8 << s->sew);
unsigned int len = 64 - ofs;
TCGv_i64 t_nan;
@@ -3397,6 +3417,8 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
if (require_rvv(s) &&
require_rvf(s) &&
vext_check_isa_ill(s)) {
+ gen_set_rm(s, RISCV_FRM_DYN);
+
/* The instructions ignore LMUL and vector register group. */
TCGv_i64 t1;
TCGLabel *over = gen_new_label();
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 67/75] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (65 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 66/75] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 68/75] target/riscv: gdb: support vector registers for rv64 & rv32 frank.chang
` (7 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Alistair Francis, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index aa76da9e185..e0f1106d909 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -293,7 +293,7 @@ static int write_vxrm(CPURISCVState *env, int csrno, target_ulong val)
if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
return -RISCV_EXCP_ILLEGAL_INST;
}
- env->mstatus |= MSTATUS_VS;
+ env->mstatus |= MSTATUS_VS | MSTATUS_SD;
#endif
env->vxrm = val;
@@ -312,7 +312,7 @@ static int write_vxsat(CPURISCVState *env, int csrno, target_ulong val)
if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
return -RISCV_EXCP_ILLEGAL_INST;
}
- env->mstatus |= MSTATUS_VS;
+ env->mstatus |= MSTATUS_VS | MSTATUS_SD;
#endif
env->vxsat = val;
@@ -331,7 +331,7 @@ static int write_vstart(CPURISCVState *env, int csrno, target_ulong val)
if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
return -RISCV_EXCP_ILLEGAL_INST;
}
- env->mstatus |= MSTATUS_VS;
+ env->mstatus |= MSTATUS_VS | MSTATUS_SD;
#endif
/*
@@ -354,7 +354,7 @@ static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val)
if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
return -RISCV_EXCP_ILLEGAL_INST;
}
- env->mstatus |= MSTATUS_VS;
+ env->mstatus |= MSTATUS_VS | MSTATUS_SD;
#endif
env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT;
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 68/75] target/riscv: gdb: support vector registers for rv64 & rv32
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (66 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 67/75] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 69/75] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction frank.chang
` (6 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Alistair Francis, Sagar Karandikar, Frank Chang,
Bastian Koppelmann, Hsiangkai Wang, Palmer Dabbelt, Greentime Hu
From: Hsiangkai Wang <kai.wang@sifive.com>
Signed-off-by: Hsiangkai Wang <kai.wang@sifive.com>
Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu.c | 2 +
target/riscv/cpu.h | 1 +
target/riscv/gdbstub.c | 184 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 187 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d95165b3acb..a110b6ead9b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -575,6 +575,8 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
if (strcmp(xmlname, "riscv-csr.xml") == 0) {
return cpu->dyn_csr_xml;
+ } else if (strcmp(xmlname, "riscv-vector.xml") == 0) {
+ return cpu->dyn_vreg_xml;
}
return NULL;
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index ad2497229db..f324949beb1 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -275,6 +275,7 @@ struct RISCVCPU {
CPURISCVState env;
char *dyn_csr_xml;
+ char *dyn_vreg_xml;
/* Configuration Settings */
struct {
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 5f96b7ea2a9..dd883612c77 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -20,6 +20,32 @@
#include "exec/gdbstub.h"
#include "cpu.h"
+struct TypeSize {
+ const char *gdb_type;
+ const char *id;
+ int size;
+ const char suffix;
+};
+
+static const struct TypeSize vec_lanes[] = {
+ /* quads */
+ { "uint128", "quads", 128, 'q' },
+ /* 64 bit */
+ { "uint64", "longs", 64, 'l' },
+ /* 32 bit */
+ { "uint32", "words", 32, 'w' },
+ /* 16 bit */
+ { "uint16", "shorts", 16, 's' },
+ /*
+ * TODO: currently there is no reliable way of telling
+ * if the remote gdb actually understands ieee_half so
+ * we don't expose it in the target description for now.
+ * { "ieee_half", 16, 'h', 'f' },
+ */
+ /* bytes */
+ { "uint8", "bytes", 8, 'b' },
+};
+
int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
RISCVCPU *cpu = RISCV_CPU(cs);
@@ -101,6 +127,96 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
return 0;
}
+/*
+ * Convert register index number passed by GDB to the correspond
+ * vector CSR number. Vector CSRs are defined after vector registers
+ * in dynamic generated riscv-vector.xml, thus the starting register index
+ * of vector CSRs is 32.
+ * Return 0 if register index number is out of range.
+ */
+static int riscv_gdb_vector_csrno(int num_regs)
+{
+ /*
+ * The order of vector CSRs in the switch case
+ * should match with the order defined in csr_ops[].
+ */
+ switch (num_regs) {
+ case 32:
+ return CSR_VSTART;
+ case 33:
+ return CSR_VXSAT;
+ case 34:
+ return CSR_VXRM;
+ case 35:
+ return CSR_VCSR;
+ case 36:
+ return CSR_VL;
+ case 37:
+ return CSR_VTYPE;
+ case 38:
+ return CSR_VLENB;
+ default:
+ /* Unknown register. */
+ return 0;
+ }
+}
+
+static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n)
+{
+ uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
+ if (n < 32) {
+ int i;
+ int cnt = 0;
+ for (i = 0; i < vlenb; i += 8) {
+ cnt += gdb_get_reg64(buf,
+ env->vreg[(n * vlenb + i) / 8]);
+ }
+ return cnt;
+ }
+
+ int csrno = riscv_gdb_vector_csrno(n);
+
+ if (!csrno) {
+ return 0;
+ }
+
+ target_ulong val = 0;
+ int result = riscv_csrrw_debug(env, csrno, &val, 0, 0);
+
+ if (result == 0) {
+ return gdb_get_regl(buf, val);
+ }
+
+ return 0;
+}
+
+static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int n)
+{
+ uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
+ if (n < 32) {
+ int i;
+ for (i = 0; i < vlenb; i += 8) {
+ env->vreg[(n * vlenb + i) / 8] = ldq_p(mem_buf + i);
+ }
+ return vlenb;
+ }
+
+ int csrno = riscv_gdb_vector_csrno(n);
+
+ if (!csrno) {
+ return 0;
+ }
+
+ target_ulong val = ldtul_p(mem_buf);
+ int result = riscv_csrrw_debug(env, csrno, NULL, val, -1);
+
+ if (result == 0) {
+ return sizeof(target_ulong);
+ }
+
+ return 0;
+}
+
static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n)
{
if (n < CSR_TABLE_SIZE) {
@@ -187,6 +303,68 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg)
return CSR_TABLE_SIZE;
}
+static int ricsv_gen_dynamic_vector_xml(CPUState *cs, int base_reg)
+{
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ GString *s = g_string_new(NULL);
+ g_autoptr(GString) ts = g_string_new("");
+ int reg_width = cpu->cfg.vlen;
+ int num_regs = 0;
+ int i;
+
+ g_string_printf(s, "<?xml version=\"1.0\"?>");
+ g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
+ g_string_append_printf(s, "<feature name=\"org.gnu.gdb.riscv.vector\">");
+
+ /* First define types and totals in a whole VL */
+ for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
+ int count = reg_width / vec_lanes[i].size;
+ g_string_printf(ts, "%s", vec_lanes[i].id);
+ g_string_append_printf(s,
+ "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
+ ts->str, vec_lanes[i].gdb_type, count);
+ }
+
+ /* Define unions */
+ g_string_append_printf(s, "<union id=\"riscv_vector\">");
+ for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
+ g_string_append_printf(s, "<field name=\"%c\" type=\"%s\"/>",
+ vec_lanes[i].suffix,
+ vec_lanes[i].id);
+ }
+ g_string_append(s, "</union>");
+
+ /* Define vector registers */
+ for (i = 0; i < 32; i++) {
+ g_string_append_printf(s,
+ "<reg name=\"v%d\" bitsize=\"%d\""
+ " regnum=\"%d\" group=\"vector\""
+ " type=\"riscv_vector\"/>",
+ i, reg_width, base_reg++);
+ num_regs++;
+ }
+
+ /* Define vector CSRs */
+ const char *vector_csrs[7] = {
+ "vstart", "vxsat", "vxrm", "vcsr",
+ "vl", "vtype", "vlenb"
+ };
+
+ for (i = 0; i < 7; i++) {
+ g_string_append_printf(s,
+ "<reg name=\"%s\" bitsize=\"%d\""
+ " regnum=\"%d\" group=\"vector\""
+ " type=\"int\"/>",
+ vector_csrs[i], TARGET_LONG_BITS, base_reg++);
+ num_regs++;
+ }
+
+ g_string_append_printf(s, "</feature>");
+
+ cpu->dyn_vreg_xml = g_string_free(s, false);
+ return num_regs;
+}
+
void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
{
RISCVCPU *cpu = RISCV_CPU(cs);
@@ -198,6 +376,12 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
36, "riscv-32bit-fpu.xml", 0);
}
+ if (env->misa & RVV) {
+ gdb_register_coprocessor(cs, riscv_gdb_get_vector, riscv_gdb_set_vector,
+ ricsv_gen_dynamic_vector_xml(cs,
+ cs->gdb_num_regs),
+ "riscv-vector.xml", 0);
+ }
#if defined(TARGET_RISCV32)
gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
1, "riscv-32bit-virtual.xml", 0);
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 69/75] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (67 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 68/75] target/riscv: gdb: support vector registers for rv64 & rv32 frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 70/75] target/riscv: rvv-1.0: floating-point reciprocal " frank.chang
` (5 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Implement the floating-point reciprocal square-root estimate to 7 bits
instruction.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 4 +
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
target/riscv/vector_helper.c | 183 ++++++++++++++++++++++++
4 files changed, 189 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 78f330b949e..1be95ebd0aa 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -882,6 +882,10 @@ DEF_HELPER_5(vfsqrt_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfsqrt_v_w, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfsqrt_v_d, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfrsqrt7_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfrsqrt7_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfrsqrt7_v_d, void, ptr, ptr, ptr, env, i32)
+
DEF_HELPER_6(vfmin_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfmin_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfmin_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index f670c1282d8..c1e896f6b84 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -535,6 +535,7 @@ vfwmsac_vf 111110 . ..... ..... 101 ..... 1010111 @r_vm
vfwnmsac_vv 111111 . ..... ..... 001 ..... 1010111 @r_vm
vfwnmsac_vf 111111 . ..... ..... 101 ..... 1010111 @r_vm
vfsqrt_v 010011 . ..... 00000 001 ..... 1010111 @r2_vm
+vfrsqrt7_v 010011 . ..... 00100 001 ..... 1010111 @r2_vm
vfmin_vv 000100 . ..... ..... 001 ..... 1010111 @r_vm
vfmin_vf 000100 . ..... ..... 101 ..... 1010111 @r_vm
vfmax_vv 000110 . ..... ..... 001 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 2a3a437168f..ca290469e23 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2638,6 +2638,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
}
GEN_OPFV_TRANS(vfsqrt_v, opfv_check, RISCV_FRM_DYN)
+GEN_OPFV_TRANS(vfrsqrt7_v, opfv_check, RISCV_FRM_DYN)
/* Vector Floating-Point MIN/MAX Instructions */
GEN_OPFVV_TRANS(vfmin_vv, opfvv_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index efa32565d9a..471b07f4388 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -18,6 +18,7 @@
#include "qemu/osdep.h"
#include "qemu/host-utils.h"
+#include "qemu/bitops.h"
#include "cpu.h"
#include "exec/memop.h"
#include "exec/exec-all.h"
@@ -3638,6 +3639,188 @@ GEN_VEXT_V_ENV(vfsqrt_v_h, 2, 2)
GEN_VEXT_V_ENV(vfsqrt_v_w, 4, 4)
GEN_VEXT_V_ENV(vfsqrt_v_d, 8, 8)
+/*
+ * Vector Floating-Point Reciprocal Square-Root Estimate Instruction
+ *
+ * Adapted from riscv-v-spec recip.cc:
+ * https://github.com/riscv/riscv-v-spec/blob/master/recip.cc
+ */
+static uint64_t frsqrt7(uint64_t f, int exp_size, int frac_size)
+{
+ bool sign = extract64(f, frac_size + exp_size, 1);
+ uint64_t exp = extract64(f, frac_size, exp_size);
+ uint64_t frac = extract64(f, 0, frac_size);
+
+ const uint8_t lookup_table[] = {
+ 52, 51, 50, 48, 47, 46, 44, 43,
+ 42, 41, 40, 39, 38, 36, 35, 34,
+ 33, 32, 31, 30, 30, 29, 28, 27,
+ 26, 25, 24, 23, 23, 22, 21, 20,
+ 19, 19, 18, 17, 16, 16, 15, 14,
+ 14, 13, 12, 12, 11, 10, 10, 9,
+ 9, 8, 7, 7, 6, 6, 5, 4,
+ 4, 3, 3, 2, 2, 1, 1, 0,
+ 127, 125, 123, 121, 119, 118, 116, 114,
+ 113, 111, 109, 108, 106, 105, 103, 102,
+ 100, 99, 97, 96, 95, 93, 92, 91,
+ 90, 88, 87, 86, 85, 84, 83, 82,
+ 80, 79, 78, 77, 76, 75, 74, 73,
+ 72, 71, 70, 70, 69, 68, 67, 66,
+ 65, 64, 63, 63, 62, 61, 60, 59,
+ 59, 58, 57, 56, 56, 55, 54, 53
+ };
+ const int precision = 7;
+
+ if (exp == 0 && frac != 0) { /* subnormal */
+ /* Normalize the subnormal. */
+ while (extract64(frac, frac_size - 1, 1) == 0) {
+ exp--;
+ frac <<= 1;
+ }
+
+ frac = (frac << 1) & MAKE_64BIT_MASK(0, frac_size);
+ }
+
+ int idx = ((exp & 1) << (precision - 1)) |
+ (frac >> (frac_size - precision + 1));
+ uint64_t out_frac = (uint64_t)(lookup_table[idx]) <<
+ (frac_size - precision);
+ uint64_t out_exp = (3 * MAKE_64BIT_MASK(0, exp_size - 1) + ~exp) / 2;
+
+ uint64_t val = 0;
+ val = deposit64(val, 0, frac_size, out_frac);
+ val = deposit64(val, frac_size, exp_size, out_exp);
+ val = deposit64(val, frac_size + exp_size, 1, sign);
+ return val;
+}
+
+static float16 frsqrt7_h(float16 f, float_status *s)
+{
+ int exp_size = 5, frac_size = 10;
+ bool sign = float16_is_neg(f);
+
+ /*
+ * frsqrt7(sNaN) = canonical NaN
+ * frsqrt7(-inf) = canonical NaN
+ * frsqrt7(-normal) = canonical NaN
+ * frsqrt7(-subnormal) = canonical NaN
+ */
+ if (float16_is_signaling_nan(f, s) ||
+ (float16_is_infinity(f) && sign) ||
+ (float16_is_normal(f) && sign) ||
+ (float16_is_zero_or_denormal(f) && !float16_is_zero(f) && sign)) {
+ s->float_exception_flags |= float_flag_invalid;
+ return float16_default_nan(s);
+ }
+
+ /* frsqrt7(qNaN) = canonical NaN */
+ if (float16_is_quiet_nan(f, s)) {
+ return float16_default_nan(s);
+ }
+
+ /* frsqrt7(+-0) = +-inf */
+ if (float16_is_zero(f)) {
+ s->float_exception_flags |= float_flag_divbyzero;
+ return float16_set_sign(float16_infinity, sign);
+ }
+
+ /* frsqrt7(+inf) = +0 */
+ if (float16_is_infinity(f) && !sign) {
+ return float16_set_sign(float16_zero, sign);
+ }
+
+ /* +normal, +subnormal */
+ uint64_t val = frsqrt7(f, exp_size, frac_size);
+ return make_float16(val);
+}
+
+static float32 frsqrt7_s(float32 f, float_status *s)
+{
+ int exp_size = 8, frac_size = 23;
+ bool sign = float32_is_neg(f);
+
+ /*
+ * frsqrt7(sNaN) = canonical NaN
+ * frsqrt7(-inf) = canonical NaN
+ * frsqrt7(-normal) = canonical NaN
+ * frsqrt7(-subnormal) = canonical NaN
+ */
+ if (float32_is_signaling_nan(f, s) ||
+ (float32_is_infinity(f) && sign) ||
+ (float32_is_normal(f) && sign) ||
+ (float32_is_zero_or_denormal(f) && !float32_is_zero(f) && sign)) {
+ s->float_exception_flags |= float_flag_invalid;
+ return float32_default_nan(s);
+ }
+
+ /* frsqrt7(qNaN) = canonical NaN */
+ if (float32_is_quiet_nan(f, s)) {
+ return float32_default_nan(s);
+ }
+
+ /* frsqrt7(+-0) = +-inf */
+ if (float32_is_zero(f)) {
+ s->float_exception_flags |= float_flag_divbyzero;
+ return float32_set_sign(float32_infinity, sign);
+ }
+
+ /* frsqrt7(+inf) = +0 */
+ if (float32_is_infinity(f) && !sign) {
+ return float32_set_sign(float32_zero, sign);
+ }
+
+ /* +normal, +subnormal */
+ uint64_t val = frsqrt7(f, exp_size, frac_size);
+ return make_float32(val);
+}
+
+static float64 frsqrt7_d(float64 f, float_status *s)
+{
+ int exp_size = 11, frac_size = 52;
+ bool sign = float64_is_neg(f);
+
+ /*
+ * frsqrt7(sNaN) = canonical NaN
+ * frsqrt7(-inf) = canonical NaN
+ * frsqrt7(-normal) = canonical NaN
+ * frsqrt7(-subnormal) = canonical NaN
+ */
+ if (float64_is_signaling_nan(f, s) ||
+ (float64_is_infinity(f) && sign) ||
+ (float64_is_normal(f) && sign) ||
+ (float64_is_zero_or_denormal(f) && !float64_is_zero(f) && sign)) {
+ s->float_exception_flags |= float_flag_invalid;
+ return float64_default_nan(s);
+ }
+
+ /* frsqrt7(qNaN) = canonical NaN */
+ if (float64_is_quiet_nan(f, s)) {
+ return float64_default_nan(s);
+ }
+
+ /* frsqrt7(+-0) = +-inf */
+ if (float64_is_zero(f)) {
+ s->float_exception_flags |= float_flag_divbyzero;
+ return float64_set_sign(float64_infinity, sign);
+ }
+
+ /* frsqrt7(+inf) = +0 */
+ if (float64_is_infinity(f) && !sign) {
+ return float64_set_sign(float64_zero, sign);
+ }
+
+ /* +normal, +subnormal */
+ uint64_t val = frsqrt7(f, exp_size, frac_size);
+ return make_float64(val);
+}
+
+RVVCALL(OPFVV1, vfrsqrt7_v_h, OP_UU_H, H2, H2, frsqrt7_h)
+RVVCALL(OPFVV1, vfrsqrt7_v_w, OP_UU_W, H4, H4, frsqrt7_s)
+RVVCALL(OPFVV1, vfrsqrt7_v_d, OP_UU_D, H8, H8, frsqrt7_d)
+GEN_VEXT_V_ENV(vfrsqrt7_v_h, 2, 2)
+GEN_VEXT_V_ENV(vfrsqrt7_v_w, 4, 4)
+GEN_VEXT_V_ENV(vfrsqrt7_v_d, 8, 8)
+
/* Vector Floating-Point MIN/MAX Instructions */
RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minnum_noprop)
RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minnum_noprop)
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 70/75] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (68 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 69/75] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 71/75] target/riscv: set mstatus.SD bit when writing fp CSRs frank.chang
` (4 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Implement the floating-point reciprocal estimate to 7 bits instruction.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 4 +
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
target/riscv/vector_helper.c | 191 ++++++++++++++++++++++++
4 files changed, 197 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 1be95ebd0aa..6dffd9be45d 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -886,6 +886,10 @@ DEF_HELPER_5(vfrsqrt7_v_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfrsqrt7_v_w, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfrsqrt7_v_d, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfrec7_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfrec7_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfrec7_v_d, void, ptr, ptr, ptr, env, i32)
+
DEF_HELPER_6(vfmin_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfmin_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfmin_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index c1e896f6b84..916367703f1 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -536,6 +536,7 @@ vfwnmsac_vv 111111 . ..... ..... 001 ..... 1010111 @r_vm
vfwnmsac_vf 111111 . ..... ..... 101 ..... 1010111 @r_vm
vfsqrt_v 010011 . ..... 00000 001 ..... 1010111 @r2_vm
vfrsqrt7_v 010011 . ..... 00100 001 ..... 1010111 @r2_vm
+vfrec7_v 010011 . ..... 00101 001 ..... 1010111 @r2_vm
vfmin_vv 000100 . ..... ..... 001 ..... 1010111 @r_vm
vfmin_vf 000100 . ..... ..... 101 ..... 1010111 @r_vm
vfmax_vv 000110 . ..... ..... 001 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index ca290469e23..120b32367e5 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2639,6 +2639,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
GEN_OPFV_TRANS(vfsqrt_v, opfv_check, RISCV_FRM_DYN)
GEN_OPFV_TRANS(vfrsqrt7_v, opfv_check, RISCV_FRM_DYN)
+GEN_OPFV_TRANS(vfrec7_v, opfv_check, RISCV_FRM_DYN)
/* Vector Floating-Point MIN/MAX Instructions */
GEN_OPFVV_TRANS(vfmin_vv, opfvv_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 471b07f4388..fc6834c1ec4 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -3821,6 +3821,197 @@ GEN_VEXT_V_ENV(vfrsqrt7_v_h, 2, 2)
GEN_VEXT_V_ENV(vfrsqrt7_v_w, 4, 4)
GEN_VEXT_V_ENV(vfrsqrt7_v_d, 8, 8)
+/*
+ * Vector Floating-Point Reciprocal Estimate Instruction
+ *
+ * Adapted from riscv-v-spec recip.cc:
+ * https://github.com/riscv/riscv-v-spec/blob/master/recip.cc
+ */
+static uint64_t frec7(uint64_t f, int exp_size, int frac_size,
+ float_status *s)
+{
+ bool sign = extract64(f, frac_size + exp_size, 1);
+ uint64_t exp = extract64(f, frac_size, exp_size);
+ uint64_t frac = extract64(f, 0, frac_size);
+
+ const uint8_t lookup_table[] = {
+ 127, 125, 123, 121, 119, 117, 116, 114,
+ 112, 110, 109, 107, 105, 104, 102, 100,
+ 99, 97, 96, 94, 93, 91, 90, 88,
+ 87, 85, 84, 83, 81, 80, 79, 77,
+ 76, 75, 74, 72, 71, 70, 69, 68,
+ 66, 65, 64, 63, 62, 61, 60, 59,
+ 58, 57, 56, 55, 54, 53, 52, 51,
+ 50, 49, 48, 47, 46, 45, 44, 43,
+ 42, 41, 40, 40, 39, 38, 37, 36,
+ 35, 35, 34, 33, 32, 31, 31, 30,
+ 29, 28, 28, 27, 26, 25, 25, 24,
+ 23, 23, 22, 21, 21, 20, 19, 19,
+ 18, 17, 17, 16, 15, 15, 14, 14,
+ 13, 12, 12, 11, 11, 10, 9, 9,
+ 8, 8, 7, 7, 6, 5, 5, 4,
+ 4, 3, 3, 2, 2, 1, 1, 0
+ };
+ const int precision = 7;
+
+ if (exp == 0 && frac != 0) { /* subnormal */
+ /* Normalize the subnormal. */
+ while (extract64(frac, frac_size - 1, 1) == 0) {
+ exp--;
+ frac <<= 1;
+ }
+
+ frac = (frac << 1) & MAKE_64BIT_MASK(0, frac_size);
+
+ if (exp != 0 && exp != UINT64_MAX) {
+ /*
+ * Overflow to inf or max value of same sign,
+ * depending on sign and rounding mode.
+ */
+ s->float_exception_flags |= (float_flag_inexact |
+ float_flag_overflow);
+
+ if ((s->float_rounding_mode == float_round_to_zero) ||
+ ((s->float_rounding_mode == float_round_down) && !sign) ||
+ ((s->float_rounding_mode == float_round_up) && sign)) {
+ /* Return greatest/negative finite value. */
+ return (sign << (exp_size + frac_size)) |
+ (MAKE_64BIT_MASK(frac_size, exp_size) - 1);
+ } else {
+ /* Return +-inf. */
+ return (sign << (exp_size + frac_size)) |
+ MAKE_64BIT_MASK(frac_size, exp_size);
+ }
+ }
+ }
+
+ int idx = frac >> (frac_size - precision);
+ uint64_t out_frac = (uint64_t)(lookup_table[idx]) <<
+ (frac_size - precision);
+ uint64_t out_exp = 2 * MAKE_64BIT_MASK(0, exp_size - 1) + ~exp;
+
+ if (out_exp == 0 || out_exp == UINT64_MAX) {
+ /*
+ * The result is subnormal, but don't raise the underflow exception,
+ * because there's no additional loss of precision.
+ */
+ out_frac = (out_frac >> 1) | MAKE_64BIT_MASK(frac_size - 1, 1);
+ if (out_exp == UINT64_MAX) {
+ out_frac >>= 1;
+ out_exp = 0;
+ }
+ }
+
+ uint64_t val = 0;
+ val = deposit64(val, 0, frac_size, out_frac);
+ val = deposit64(val, frac_size, exp_size, out_exp);
+ val = deposit64(val, frac_size + exp_size, 1, sign);
+ return val;
+}
+
+static float16 frec7_h(float16 f, float_status *s)
+{
+ int exp_size = 5, frac_size = 10;
+ bool sign = float16_is_neg(f);
+
+ /* frec7(+-inf) = +-0 */
+ if (float16_is_infinity(f)) {
+ return float16_set_sign(float16_zero, sign);
+ }
+
+ /* frec7(+-0) = +-inf */
+ if (float16_is_zero(f)) {
+ s->float_exception_flags |= float_flag_divbyzero;
+ return float16_set_sign(float16_infinity, sign);
+ }
+
+ /* frec7(sNaN) = canonical NaN */
+ if (float16_is_signaling_nan(f, s)) {
+ s->float_exception_flags |= float_flag_invalid;
+ return float16_default_nan(s);
+ }
+
+ /* frec7(qNaN) = canonical NaN */
+ if (float16_is_quiet_nan(f, s)) {
+ return float16_default_nan(s);
+ }
+
+ /* +-normal, +-subnormal */
+ uint64_t val = frec7(f, exp_size, frac_size, s);
+ return make_float16(val);
+}
+
+static float32 frec7_s(float32 f, float_status *s)
+{
+ int exp_size = 8, frac_size = 23;
+ bool sign = float32_is_neg(f);
+
+ /* frec7(+-inf) = +-0 */
+ if (float32_is_infinity(f)) {
+ return float32_set_sign(float32_zero, sign);
+ }
+
+ /* frec7(+-0) = +-inf */
+ if (float32_is_zero(f)) {
+ s->float_exception_flags |= float_flag_divbyzero;
+ return float32_set_sign(float32_infinity, sign);
+ }
+
+ /* frec7(sNaN) = canonical NaN */
+ if (float32_is_signaling_nan(f, s)) {
+ s->float_exception_flags |= float_flag_invalid;
+ return float32_default_nan(s);
+ }
+
+ /* frec7(qNaN) = canonical NaN */
+ if (float32_is_quiet_nan(f, s)) {
+ return float32_default_nan(s);
+ }
+
+ /* +-normal, +-subnormal */
+ uint64_t val = frec7(f, exp_size, frac_size, s);
+ return make_float32(val);
+}
+
+static float64 frec7_d(float64 f, float_status *s)
+{
+ int exp_size = 11, frac_size = 52;
+ bool sign = float64_is_neg(f);
+
+ /* frec7(+-inf) = +-0 */
+ if (float64_is_infinity(f)) {
+ return float64_set_sign(float64_zero, sign);
+ }
+
+ /* frec7(+-0) = +-inf */
+ if (float64_is_zero(f)) {
+ s->float_exception_flags |= float_flag_divbyzero;
+ return float64_set_sign(float64_infinity, sign);
+ }
+
+ /* frec7(sNaN) = canonical NaN */
+ if (float64_is_signaling_nan(f, s)) {
+ s->float_exception_flags |= float_flag_invalid;
+ return float64_default_nan(s);
+ }
+
+ /* frec7(qNaN) = canonical NaN */
+ if (float64_is_quiet_nan(f, s)) {
+ return float64_default_nan(s);
+ }
+
+ /* +-normal, +-subnormal */
+ uint64_t val = frec7(f, exp_size, frac_size, s);
+ return make_float64(val);
+}
+
+RVVCALL(OPFVV1, vfrec7_v_h, OP_UU_H, H2, H2, frec7_h)
+RVVCALL(OPFVV1, vfrec7_v_w, OP_UU_W, H4, H4, frec7_s)
+RVVCALL(OPFVV1, vfrec7_v_d, OP_UU_D, H8, H8, frec7_d)
+GEN_VEXT_V_ENV(vfrec7_v_h, 2, 2)
+GEN_VEXT_V_ENV(vfrec7_v_w, 4, 4)
+GEN_VEXT_V_ENV(vfrec7_v_d, 8, 8)
+
/* Vector Floating-Point MIN/MAX Instructions */
RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minnum_noprop)
RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minnum_noprop)
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 71/75] target/riscv: set mstatus.SD bit when writing fp CSRs
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (69 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 70/75] target/riscv: rvv-1.0: floating-point reciprocal " frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 72/75] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 frank.chang
` (3 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Alistair Francis, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/csr.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index e0f1106d909..0082db9cc0c 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -209,7 +209,7 @@ static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
return -RISCV_EXCP_ILLEGAL_INST;
}
- env->mstatus |= MSTATUS_FS;
+ env->mstatus |= MSTATUS_FS | MSTATUS_SD;
#endif
riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
return 0;
@@ -232,7 +232,7 @@ static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
return -RISCV_EXCP_ILLEGAL_INST;
}
- env->mstatus |= MSTATUS_FS;
+ env->mstatus |= MSTATUS_FS | MSTATUS_SD;
#endif
env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
return 0;
@@ -256,7 +256,7 @@ static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
return -RISCV_EXCP_ILLEGAL_INST;
}
- env->mstatus |= MSTATUS_FS;
+ env->mstatus |= MSTATUS_FS | MSTATUS_SD;
#endif
env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 72/75] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (70 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 71/75] target/riscv: set mstatus.SD bit when writing fp CSRs frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 73/75] target/riscv: rvv-1.0: add vsetivli instruction frank.chang
` (2 subsequent siblings)
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Alistair Francis, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
Rename r2_zimm to r2_zimm11 for the upcoming vsetivli instruction.
vsetivli has 10-bits of zimm but vsetvli has 11-bits of zimm.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 916367703f1..6fb85c83278 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -77,7 +77,7 @@
@r_vm_1 ...... . ..... ..... ... ..... ....... &rmrr vm=1 %rs2 %rs1 %rd
@r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=0 %rs2 %rs1 %rd
@r_wdvm ..... wd:1 vm:1 ..... ..... ... ..... ....... &rwdvm %rs2 %rs1 %rd
-@r2_zimm . zimm:11 ..... ... ..... ....... %rs1 %rd
+@r2_zimm11 . zimm:11 ..... ... ..... ....... %rs1 %rd
@r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1
@hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1
@@ -646,5 +646,5 @@ vsext_vf2 010010 . ..... 00111 010 ..... 1010111 @r2_vm
vsext_vf4 010010 . ..... 00101 010 ..... 1010111 @r2_vm
vsext_vf8 010010 . ..... 00011 010 ..... 1010111 @r2_vm
-vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
+vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm11
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 73/75] target/riscv: rvv-1.0: add vsetivli instruction
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (71 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 72/75] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 74/75] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() frank.chang
2021-02-26 3:18 ` [PATCH v7 75/75] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns frank.chang
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvv.c.inc | 30 +++++++++++++++++++++++++
2 files changed, 32 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 6fb85c83278..472626f1950 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -78,6 +78,7 @@
@r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=0 %rs2 %rs1 %rd
@r_wdvm ..... wd:1 vm:1 ..... ..... ... ..... ....... &rwdvm %rs2 %rs1 %rd
@r2_zimm11 . zimm:11 ..... ... ..... ....... %rs1 %rd
+@r2_zimm10 .. zimm:10 ..... ... ..... ....... %rs1 %rd
@r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1
@hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1
@@ -647,4 +648,5 @@ vsext_vf4 010010 . ..... 00101 010 ..... 1010111 @r2_vm
vsext_vf8 010010 . ..... 00011 010 ..... 1010111 @r2_vm
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm11
+vsetivli 11 .......... ..... 111 ..... 1010111 @r2_zimm10
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 120b32367e5..1e9f5148ccd 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -159,6 +159,29 @@ static bool do_vsetvl(DisasContext *ctx, int rd, int rs1, TCGv s2)
return true;
}
+static bool do_vsetivli(DisasContext *ctx, int rd, TCGv s1, TCGv s2)
+{
+ TCGv dst;
+
+ if (!require_rvv(ctx) || !has_ext(ctx, RVV)) {
+ return false;
+ }
+
+ dst = tcg_temp_new();
+
+ gen_helper_vsetvl(dst, cpu_env, s1, s2);
+ gen_set_gpr(rd, dst);
+ mark_vs_dirty(ctx);
+ tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
+ lookup_and_goto_ptr(ctx);
+ ctx->base.is_jmp = DISAS_NORETURN;
+
+ tcg_temp_free(s1);
+ tcg_temp_free(s2);
+ tcg_temp_free(dst);
+ return true;
+}
+
static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
{
TCGv s2 = tcg_temp_new();
@@ -172,6 +195,13 @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
return do_vsetvl(ctx, a->rd, a->rs1, s2);
}
+static bool trans_vsetivli(DisasContext *ctx, arg_vsetivli *a)
+{
+ TCGv s1 = tcg_const_tl(a->rs1);
+ TCGv s2 = tcg_const_tl(a->zimm);
+ return do_vsetivli(ctx, a->rd, s1, s2);
+}
+
/* vector register offset from env */
static uint32_t vreg_ofs(DisasContext *s, int reg)
{
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 74/75] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (72 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 73/75] target/riscv: rvv-1.0: add vsetivli instruction frank.chang
@ 2021-02-26 3:18 ` frank.chang
2021-02-26 3:18 ` [PATCH v7 75/75] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns frank.chang
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Alistair Francis, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
From: Frank Chang <frank.chang@sifive.com>
rvv v0.10 adds vector unit-stride mask load/store instructions
(vle1.v, vse1.v), which has:
evl (effective vector length) = ceil(env-vl/8).
The new instructions operate the same as unmasked byte loads and stores.
Add evl parameter to reuse vext_ldst_us().
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/vector_helper.c | 38 ++++++++++++++++++------------------
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index fc6834c1ec4..55560116ff6 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -292,17 +292,17 @@ GEN_VEXT_ST_STRIDE(vsse64_v, int64_t, ste_d)
/* unmasked unit-stride load and store operation*/
static void
vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
- vext_ldst_elem_fn *ldst_elem,
- uint32_t esz, uintptr_t ra, MMUAccessType access_type)
+ vext_ldst_elem_fn *ldst_elem, uint32_t esz, uint32_t evl,
+ uintptr_t ra, MMUAccessType access_type)
{
uint32_t i, k;
uint32_t nf = vext_nf(desc);
uint32_t max_elems = vext_max_elems(desc, esz);
/* probe every access */
- probe_pages(env, base, env->vl * (nf << esz), ra, access_type);
+ probe_pages(env, base, evl * (nf << esz), ra, access_type);
/* load bytes from guest memory */
- for (i = env->vstart; i < env->vl; i++) {
+ for (i = env->vstart; i < evl; i++) {
k = 0;
while (k < nf) {
target_ulong addr = base + ((i * nf + k) << esz);
@@ -332,7 +332,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
CPURISCVState *env, uint32_t desc) \
{ \
vext_ldst_us(vd, base, env, desc, LOAD_FN, \
- ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_LOAD); \
+ ctzl(sizeof(ETYPE)), env->vl, GETPC(), MMU_DATA_LOAD); \
}
GEN_VEXT_LD_US(vle8_v, int8_t, lde_b)
@@ -340,20 +340,20 @@ GEN_VEXT_LD_US(vle16_v, int16_t, lde_h)
GEN_VEXT_LD_US(vle32_v, int32_t, lde_w)
GEN_VEXT_LD_US(vle64_v, int64_t, lde_d)
-#define GEN_VEXT_ST_US(NAME, ETYPE, STORE_FN) \
-void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \
- CPURISCVState *env, uint32_t desc) \
-{ \
- uint32_t stride = vext_nf(desc) << ctzl(sizeof(ETYPE)); \
- vext_ldst_stride(vd, v0, base, stride, env, desc, false, STORE_FN, \
- ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_STORE); \
-} \
- \
-void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
- CPURISCVState *env, uint32_t desc) \
-{ \
- vext_ldst_us(vd, base, env, desc, STORE_FN, \
- ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_STORE); \
+#define GEN_VEXT_ST_US(NAME, ETYPE, STORE_FN) \
+void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ uint32_t stride = vext_nf(desc) << ctzl(sizeof(ETYPE)); \
+ vext_ldst_stride(vd, v0, base, stride, env, desc, false, STORE_FN, \
+ ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_STORE); \
+} \
+ \
+void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ vext_ldst_us(vd, base, env, desc, STORE_FN, \
+ ctzl(sizeof(ETYPE)), env->vl, GETPC(), MMU_DATA_STORE); \
}
GEN_VEXT_ST_US(vse8_v, int8_t, ste_b)
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
* [PATCH v7 75/75] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
` (73 preceding siblings ...)
2021-02-26 3:18 ` [PATCH v7 74/75] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() frank.chang
@ 2021-02-26 3:18 ` frank.chang
74 siblings, 0 replies; 76+ messages in thread
From: frank.chang @ 2021-02-26 3:18 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Frank Chang, Bastian Koppelmann,
Richard Henderson, Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/helper.h | 2 ++
target/riscv/insn32.decode | 4 +++
target/riscv/insn_trans/trans_rvv.c.inc | 40 +++++++++++++++++++++++++
target/riscv/vector_helper.c | 21 +++++++++++++
4 files changed, 67 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 6dffd9be45d..f0cbddcd94f 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -96,6 +96,8 @@ DEF_HELPER_5(vse8_v_mask, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vse16_v_mask, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vse32_v_mask, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vse64_v_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vle1_v, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(vse1_v, void, ptr, ptr, tl, env, i32)
DEF_HELPER_6(vlse8_v, void, ptr, ptr, tl, tl, env, i32)
DEF_HELPER_6(vlse16_v, void, ptr, ptr, tl, tl, env, i32)
DEF_HELPER_6(vlse32_v, void, ptr, ptr, tl, tl, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 472626f1950..bb7b1d30f4f 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -251,6 +251,10 @@ vse16_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm
vse32_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm
vse64_v ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm
+# Vector unit-stride mask load/store insns.
+vle1_v 000 000 1 01011 ..... 000 ..... 0000111 @r2
+vse1_v 000 000 1 01011 ..... 000 ..... 0100111 @r2
+
# Vector strided insns.
vlse8_v ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm
vlse16_v ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 1e9f5148ccd..4dd1e29368c 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -747,6 +747,46 @@ GEN_VEXT_TRANS(vse16_v, MO_16, r2nfvm, st_us_op, st_us_check)
GEN_VEXT_TRANS(vse32_v, MO_32, r2nfvm, st_us_op, st_us_check)
GEN_VEXT_TRANS(vse64_v, MO_64, r2nfvm, st_us_op, st_us_check)
+/*
+ *** unit stride mask load and store
+ */
+static bool ld_us_mask_op(DisasContext *s, arg_vle1_v *a, uint8_t eew)
+{
+ uint32_t data = 0;
+ gen_helper_ldst_us *fn = gen_helper_vle1_v;
+
+ /* EMUL = 1, NFIELDS = 1 */
+ data = FIELD_DP32(data, VDATA, LMUL, 0);
+ data = FIELD_DP32(data, VDATA, NF, 1);
+ return ldst_us_trans(a->rd, a->rs1, data, fn, s, false);
+}
+
+static bool ld_us_mask_check(DisasContext *s, arg_vle1_v *a, uint8_t eew)
+{
+ /* EMUL = 1, NFIELDS = 1 */
+ return require_rvv(s) && vext_check_isa_ill(s);
+}
+
+static bool st_us_mask_op(DisasContext *s, arg_vse1_v *a, uint8_t eew)
+{
+ uint32_t data = 0;
+ gen_helper_ldst_us *fn = gen_helper_vse1_v;
+
+ /* EMUL = 1, NFIELDS = 1 */
+ data = FIELD_DP32(data, VDATA, LMUL, 0);
+ data = FIELD_DP32(data, VDATA, NF, 1);
+ return ldst_us_trans(a->rd, a->rs1, data, fn, s, true);
+}
+
+static bool st_us_mask_check(DisasContext *s, arg_vse1_v *a, uint8_t eew)
+{
+ /* EMUL = 1, NFIELDS = 1 */
+ return require_rvv(s) && vext_check_isa_ill(s);
+}
+
+GEN_VEXT_TRANS(vle1_v, MO_8, vle1_v, ld_us_mask_op, ld_us_mask_check)
+GEN_VEXT_TRANS(vse1_v, MO_8, vse1_v, st_us_mask_op, st_us_mask_check)
+
/*
*** stride load and store
*/
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 55560116ff6..e7a3084876d 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -361,6 +361,27 @@ GEN_VEXT_ST_US(vse16_v, int16_t, ste_h)
GEN_VEXT_ST_US(vse32_v, int32_t, ste_w)
GEN_VEXT_ST_US(vse64_v, int64_t, ste_d)
+/*
+ *** unit stride mask load and store, EEW = 1
+ */
+void HELPER(vle1_v)(void *vd, void *v0, target_ulong base,
+ CPURISCVState *env, uint32_t desc)
+{
+ /* evl = ceil(vl/8) */
+ uint8_t evl = (env->vl + 7) >> 3;
+ vext_ldst_us(vd, base, env, desc, lde_b,
+ 0, evl, GETPC(), MMU_DATA_LOAD);
+}
+
+void HELPER(vse1_v)(void *vd, void *v0, target_ulong base,
+ CPURISCVState *env, uint32_t desc)
+{
+ /* evl = ceil(vl/8) */
+ uint8_t evl = (env->vl + 7) >> 3;
+ vext_ldst_us(vd, base, env, desc, ste_b,
+ 0, evl, GETPC(), MMU_DATA_STORE);
+}
+
/*
*** index: access vector element from indexed memory
*/
--
2.17.1
^ permalink raw reply related [flat|nested] 76+ messages in thread
end of thread, other threads:[~2021-02-26 4:28 UTC | newest]
Thread overview: 76+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-02-26 3:17 [PATCH v7 00/75] support vector extension v1.0 frank.chang
2021-02-26 3:17 ` [PATCH v7 01/75] target/riscv: drop vector 0.7.1 and add 1.0 support frank.chang
2021-02-26 3:17 ` [PATCH v7 02/75] target/riscv: Use FIELD_EX32() to extract wd field frank.chang
2021-02-26 3:17 ` [PATCH v7 03/75] target/riscv: rvv-1.0: add mstatus VS field frank.chang
2021-02-26 3:17 ` [PATCH v7 04/75] target/riscv: rvv-1.0: add sstatus " frank.chang
2021-02-26 3:17 ` [PATCH v7 05/75] target/riscv: rvv-1.0: introduce writable misa.v field frank.chang
2021-02-26 3:17 ` [PATCH v7 06/75] target/riscv: rvv-1.0: add translation-time vector context status frank.chang
2021-02-26 3:17 ` [PATCH v7 07/75] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers frank.chang
2021-02-26 3:17 ` [PATCH v7 08/75] target/riscv: rvv-1.0: add vcsr register frank.chang
2021-02-26 3:17 ` [PATCH v7 09/75] target/riscv: rvv-1.0: add vlenb register frank.chang
2021-02-26 3:17 ` [PATCH v7 10/75] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers frank.chang
2021-02-26 3:17 ` [PATCH v7 11/75] target/riscv: rvv-1.0: remove MLEN calculations frank.chang
2021-02-26 3:17 ` [PATCH v7 12/75] target/riscv: rvv-1.0: add fractional LMUL frank.chang
2021-02-26 3:17 ` [PATCH v7 13/75] target/riscv: rvv-1.0: add VMA and VTA frank.chang
2021-02-26 3:17 ` [PATCH v7 14/75] target/riscv: rvv-1.0: update check functions frank.chang
2021-02-26 3:17 ` [PATCH v7 15/75] target/riscv: introduce more imm value modes in translator functions frank.chang
2021-02-26 3:18 ` [PATCH v7 16/75] target/riscv: rvv:1.0: add translation-time nan-box helper function frank.chang
2021-02-26 3:18 ` [PATCH v7 17/75] target/riscv: rvv-1.0: configure instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 18/75] target/riscv: rvv-1.0: stride load and store instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 19/75] target/riscv: rvv-1.0: index " frank.chang
2021-02-26 3:18 ` [PATCH v7 20/75] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns frank.chang
2021-02-26 3:18 ` [PATCH v7 21/75] target/riscv: rvv-1.0: fault-only-first unit stride load frank.chang
2021-02-26 3:18 ` [PATCH v7 22/75] target/riscv: rvv-1.0: amo operations frank.chang
2021-02-26 3:18 ` [PATCH v7 23/75] target/riscv: rvv-1.0: load/store whole register instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 24/75] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns frank.chang
2021-02-26 3:18 ` [PATCH v7 25/75] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation frank.chang
2021-02-26 3:18 ` [PATCH v7 26/75] target/riscv: rvv-1.0: floating-point square-root instruction frank.chang
2021-02-26 3:18 ` [PATCH v7 27/75] target/riscv: rvv-1.0: floating-point classify instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 28/75] target/riscv: rvv-1.0: mask population count instruction frank.chang
2021-02-26 3:18 ` [PATCH v7 29/75] target/riscv: rvv-1.0: find-first-set mask bit instruction frank.chang
2021-02-26 3:18 ` [PATCH v7 30/75] target/riscv: rvv-1.0: set-X-first mask bit instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 31/75] target/riscv: rvv-1.0: iota instruction frank.chang
2021-02-26 3:18 ` [PATCH v7 32/75] target/riscv: rvv-1.0: element index instruction frank.chang
2021-02-26 3:18 ` [PATCH v7 33/75] target/riscv: rvv-1.0: allow load element with sign-extended frank.chang
2021-02-26 3:18 ` [PATCH v7 34/75] target/riscv: rvv-1.0: register gather instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 35/75] target/riscv: rvv-1.0: integer scalar move instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 36/75] target/riscv: rvv-1.0: floating-point move instruction frank.chang
2021-02-26 3:18 ` [PATCH v7 37/75] target/riscv: rvv-1.0: floating-point scalar move instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 38/75] target/riscv: rvv-1.0: whole register " frank.chang
2021-02-26 3:18 ` [PATCH v7 39/75] target/riscv: rvv-1.0: integer extension instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 40/75] target/riscv: rvv-1.0: single-width averaging add and subtract instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 41/75] target/riscv: rvv-1.0: single-width bit shift instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 42/75] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow frank.chang
2021-02-26 3:18 ` [PATCH v7 43/75] target/riscv: rvv-1.0: narrowing integer right shift instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 44/75] target/riscv: rvv-1.0: widening integer multiply-add instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 45/75] target/riscv: rvv-1.0: single-width saturating add and subtract instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 46/75] target/riscv: rvv-1.0: integer comparison instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 47/75] target/riscv: rvv-1.0: floating-point compare instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 48/75] target/riscv: rvv-1.0: mask-register logical instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 49/75] target/riscv: rvv-1.0: slide instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 50/75] target/riscv: rvv-1.0: floating-point " frank.chang
2021-02-26 3:18 ` [PATCH v7 51/75] target/riscv: rvv-1.0: narrowing fixed-point clip instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 52/75] target/riscv: rvv-1.0: single-width floating-point reduction frank.chang
2021-02-26 3:18 ` [PATCH v7 53/75] target/riscv: rvv-1.0: widening floating-point reduction instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 54/75] target/riscv: rvv-1.0: single-width scaling shift instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 55/75] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add frank.chang
2021-02-26 3:18 ` [PATCH v7 56/75] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf frank.chang
2021-02-26 3:18 ` [PATCH v7 57/75] target/riscv: rvv-1.0: remove integer extract instruction frank.chang
2021-02-26 3:18 ` [PATCH v7 58/75] target/riscv: rvv-1.0: floating-point min/max instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 59/75] target/riscv: introduce floating-point rounding mode enum frank.chang
2021-02-26 3:18 ` [PATCH v7 60/75] target/riscv: rvv-1.0: floating-point/integer type-convert instructions frank.chang
2021-02-26 3:18 ` [PATCH v7 61/75] target/riscv: rvv-1.0: widening floating-point/integer type-convert frank.chang
2021-02-26 3:18 ` [PATCH v7 62/75] target/riscv: add "set round to odd" rounding mode helper function frank.chang
2021-02-26 3:18 ` [PATCH v7 63/75] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert frank.chang
2021-02-26 3:18 ` [PATCH v7 64/75] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits frank.chang
2021-02-26 3:18 ` [PATCH v7 65/75] target/riscv: rvv-1.0: implement vstart CSR frank.chang
2021-02-26 3:18 ` [PATCH v7 66/75] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid frank.chang
2021-02-26 3:18 ` [PATCH v7 67/75] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs frank.chang
2021-02-26 3:18 ` [PATCH v7 68/75] target/riscv: gdb: support vector registers for rv64 & rv32 frank.chang
2021-02-26 3:18 ` [PATCH v7 69/75] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction frank.chang
2021-02-26 3:18 ` [PATCH v7 70/75] target/riscv: rvv-1.0: floating-point reciprocal " frank.chang
2021-02-26 3:18 ` [PATCH v7 71/75] target/riscv: set mstatus.SD bit when writing fp CSRs frank.chang
2021-02-26 3:18 ` [PATCH v7 72/75] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 frank.chang
2021-02-26 3:18 ` [PATCH v7 73/75] target/riscv: rvv-1.0: add vsetivli instruction frank.chang
2021-02-26 3:18 ` [PATCH v7 74/75] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() frank.chang
2021-02-26 3:18 ` [PATCH v7 75/75] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns frank.chang
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