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From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
To: qemu-arm@nongnu.org
Cc: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>,
	Peter Maydell <peter.maydell@linaro.org>,
	Leif Lindholm <leif@nuviainc.com>,
	qemu-devel@nongnu.org
Subject: [PATCH] arm: bump amount of PMU counters to pass SBSA ACS
Date: Wed,  3 Mar 2021 16:16:34 +0100
Message-ID: <20210303151634.3421880-1-marcin.juszkiewicz@linaro.org> (raw)

Arm BSA (Base System Architecture) specification says:

B_PE_09: PEs must implement the FEAT_PMUv3p1 extension, and the base
system must expose a minimum of four programmable PMU counters to the
operating system.

B_PE_21: The base system must expose a minimum of two programmable PMU
counters to a hypervisor.

It is then repeated in SBSA (Server Base System Architecture)
specification in level 3 requirements:

Each PE must implement a minimum of six programmable PMU counters.

So let make QEMU provide those 6 PMU counters.

SBSA-ACS says now:

  12 : Check number of PMU counters      : Result:  PASS

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
---
 target/arm/helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 0e1a3b9421..02e25b5c22 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -38,7 +38,7 @@
 #endif
 
 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
-#define PMCR_NUM_COUNTERS 4 /* QEMU IMPDEF choice */
+#define PMCR_NUM_COUNTERS 6 /* QEMU IMPDEF choice */
 
 #ifndef CONFIG_USER_ONLY
 
-- 
2.29.2



             reply index

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-03 15:16 Marcin Juszkiewicz [this message]
2021-03-03 17:48 ` Leif Lindholm
2021-03-03 18:06   ` Peter Maydell
2021-03-03 20:33     ` Marcin Juszkiewicz
2021-03-04 13:53     ` Leif Lindholm
2021-03-04 15:14       ` Peter Maydell
2021-03-04 15:25         ` Leif Lindholm
2021-03-11 17:02           ` Peter Maydell

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