From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
"Thomas Huth" <thuth@redhat.com>,
qemu-riscv@nongnu.org, "Eduardo Habkost" <ehabkost@redhat.com>,
"David Hildenbrand" <david@redhat.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Cornelia Huck" <cohuck@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Laurent Vivier" <laurent@vivier.eu>,
"Greg Kurz" <groug@kaod.org>,
qemu-s390x@nongnu.org, qemu-arm@nongnu.org, qemu-ppc@nongnu.org,
"Claudio Fontana" <cfontana@suse.de>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"David Gibson" <david@gibson.dropbear.id.au>
Subject: [RFC PATCH v2 5/8] target/ppc: Duplicate the TCGCPUOps structure for POWER CPUs
Date: Thu, 4 Mar 2021 23:23:20 +0100 [thread overview]
Message-ID: <20210304222323.1954755-6-f4bug@amsat.org> (raw)
In-Reply-To: <20210304222323.1954755-1-f4bug@amsat.org>
POWER CPUs have specific CPUClass::has_work() handlers.
In preparation of moving this field to TCGCPUOps, we need
to duplicate the current ppc_tcg_ops structure for the
POWER cpus.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/ppc/translate_init.c.inc | 69 +++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index 80239077e0b..fe76d0b3773 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -48,6 +48,11 @@
/* #define PPC_DUMP_SPR_ACCESSES */
/* #define USE_APPLE_GDB */
+static const struct TCGCPUOps power7_tcg_ops;
+static const struct TCGCPUOps power8_tcg_ops;
+static const struct TCGCPUOps power9_tcg_ops;
+static const struct TCGCPUOps power10_tcg_ops;
+
/*
* Generic callbacks:
* do nothing but store/retrieve spr value
@@ -8685,6 +8690,9 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
pcc->l1_dcache_size = 0x8000;
pcc->l1_icache_size = 0x8000;
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
+#ifdef CONFIG_TCG
+ cc->tcg_ops = &power7_tcg_ops;
+#endif /* CONFIG_TCG */
}
static void init_proc_POWER8(CPUPPCState *env)
@@ -8863,6 +8871,9 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
pcc->l1_dcache_size = 0x8000;
pcc->l1_icache_size = 0x8000;
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
+#ifdef CONFIG_TCG
+ cc->tcg_ops = &power8_tcg_ops;
+#endif /* CONFIG_TCG */
}
#ifdef CONFIG_SOFTMMU
@@ -9081,6 +9092,9 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
pcc->l1_dcache_size = 0x8000;
pcc->l1_icache_size = 0x8000;
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
+#ifdef CONFIG_TCG
+ cc->tcg_ops = &power9_tcg_ops;
+#endif /* CONFIG_TCG */
}
#ifdef CONFIG_SOFTMMU
@@ -9292,6 +9306,9 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
pcc->l1_dcache_size = 0x8000;
pcc->l1_icache_size = 0x8000;
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
+#ifdef CONFIG_TCG
+ cc->tcg_ops = &power10_tcg_ops;
+#endif /* CONFIG_TCG */
}
#if !defined(CONFIG_USER_ONLY)
@@ -10851,6 +10868,58 @@ static const struct TCGCPUOps ppc_tcg_ops = {
.cpu_exec_interrupt = ppc_cpu_exec_interrupt,
.tlb_fill = ppc_cpu_tlb_fill,
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = ppc_cpu_do_interrupt,
+ .cpu_exec_enter = ppc_cpu_exec_enter,
+ .cpu_exec_exit = ppc_cpu_exec_exit,
+ .do_unaligned_access = ppc_cpu_do_unaligned_access,
+#endif /* !CONFIG_USER_ONLY */
+};
+
+static const struct TCGCPUOps power7_tcg_ops = {
+ .initialize = ppc_translate_init,
+ .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
+ .tlb_fill = ppc_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = ppc_cpu_do_interrupt,
+ .cpu_exec_enter = ppc_cpu_exec_enter,
+ .cpu_exec_exit = ppc_cpu_exec_exit,
+ .do_unaligned_access = ppc_cpu_do_unaligned_access,
+#endif /* !CONFIG_USER_ONLY */
+};
+
+static const struct TCGCPUOps power8_tcg_ops = {
+ .initialize = ppc_translate_init,
+ .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
+ .tlb_fill = ppc_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = ppc_cpu_do_interrupt,
+ .cpu_exec_enter = ppc_cpu_exec_enter,
+ .cpu_exec_exit = ppc_cpu_exec_exit,
+ .do_unaligned_access = ppc_cpu_do_unaligned_access,
+#endif /* !CONFIG_USER_ONLY */
+};
+
+static const struct TCGCPUOps power9_tcg_ops = {
+ .initialize = ppc_translate_init,
+ .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
+ .tlb_fill = ppc_cpu_tlb_fill,
+
+#ifndef CONFIG_USER_ONLY
+ .do_interrupt = ppc_cpu_do_interrupt,
+ .cpu_exec_enter = ppc_cpu_exec_enter,
+ .cpu_exec_exit = ppc_cpu_exec_exit,
+ .do_unaligned_access = ppc_cpu_do_unaligned_access,
+#endif /* !CONFIG_USER_ONLY */
+};
+
+static const struct TCGCPUOps power10_tcg_ops = {
+ .initialize = ppc_translate_init,
+ .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
+ .tlb_fill = ppc_cpu_tlb_fill,
+
#ifndef CONFIG_USER_ONLY
.do_interrupt = ppc_cpu_do_interrupt,
.cpu_exec_enter = ppc_cpu_exec_enter,
--
2.26.2
next prev parent reply other threads:[~2021-03-04 22:45 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-04 22:23 [RFC PATCH v2 0/8] cpu: Move CPUClass::has_work() to TCGCPUOps Philippe Mathieu-Daudé
2021-03-04 22:23 ` [RFC PATCH v2 1/8] sysemu/tcg: Restrict tcg_exec_init() to CONFIG_TCG Philippe Mathieu-Daudé
2021-03-08 13:40 ` David Hildenbrand
2021-03-08 14:50 ` Claudio Fontana
2021-03-04 22:23 ` [RFC PATCH v2 2/8] sysemu/tcg: Restrict qemu_tcg_mttcg_enabled() to TCG Philippe Mathieu-Daudé
2021-03-08 14:52 ` Claudio Fontana
2021-03-04 22:23 ` [RFC PATCH v2 3/8] target/arm: Directly use arm_cpu_has_work instead of CPUClass::has_work Philippe Mathieu-Daudé
2021-03-08 14:53 ` Claudio Fontana
2021-03-04 22:23 ` [RFC PATCH v2 4/8] target/s390x: Move s390_cpu_has_work to excp_helper.c Philippe Mathieu-Daudé
2021-03-04 22:23 ` Philippe Mathieu-Daudé [this message]
2021-03-05 1:05 ` [RFC PATCH v2 5/8] target/ppc: Duplicate the TCGCPUOps structure for POWER CPUs David Gibson
2021-03-04 22:23 ` [RFC PATCH v2 6/8] cpu: Declare cpu_has_work() in 'sysemu/tcg.h' Philippe Mathieu-Daudé
2021-03-08 12:13 ` Claudio Fontana
2021-03-08 12:17 ` Claudio Fontana
2021-03-08 13:37 ` Philippe Mathieu-Daudé
2021-03-04 22:23 ` [RFC PATCH v2 7/8] cpu: Move CPUClass::has_work() to TCGCPUOps Philippe Mathieu-Daudé
2021-03-05 1:05 ` David Gibson
2021-03-04 22:23 ` [RFC PATCH v2 8/8] target/arm: Restrict arm_cpu_has_work() to TCG Philippe Mathieu-Daudé
2021-03-13 23:55 ` [RFC PATCH v2 0/8] cpu: Move CPUClass::has_work() to TCGCPUOps Philippe Mathieu-Daudé
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210304222323.1954755-6-f4bug@amsat.org \
--to=f4bug@amsat.org \
--cc=cfontana@suse.de \
--cc=cohuck@redhat.com \
--cc=david@gibson.dropbear.id.au \
--cc=david@redhat.com \
--cc=ehabkost@redhat.com \
--cc=groug@kaod.org \
--cc=laurent@vivier.eu \
--cc=pbonzini@redhat.com \
--cc=peter.maydell@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=qemu-s390x@nongnu.org \
--cc=richard.henderson@linaro.org \
--cc=thuth@redhat.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).