From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org
Subject: [PATCH v4 32/78] target/arm: Implement SVE2 bitwise ternary operations
Date: Tue, 9 Mar 2021 08:19:55 -0800 [thread overview]
Message-ID: <20210309162041.23124-33-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210309162041.23124-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper-sve.h | 6 ++
target/arm/sve.decode | 12 +++
target/arm/sve_helper.c | 50 +++++++++
target/arm/translate-sve.c | 213 +++++++++++++++++++++++++++++++++++++
4 files changed, 281 insertions(+)
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
index 5bf9fdc7a3..df617e3351 100644
--- a/target/arm/helper-sve.h
+++ b/target/arm/helper-sve.h
@@ -2543,3 +2543,9 @@ DEF_HELPER_FLAGS_6(sve2_fminp_zpzz_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_6(sve2_fminp_zpzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_5(sve2_eor3, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(sve2_bcax, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(sve2_bsl1n, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(sve2_bsl2n, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(sve2_nbsl, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index f365907518..bf673e2f16 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -124,6 +124,10 @@
@rda_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 \
&rrrr_esz ra=%reg_movprfx
+# Four operand with unused vector element size
+@rdn_ra_rm_e0 ........ ... rm:5 ... ... ra:5 rd:5 \
+ &rrrr_esz esz=0 rn=%reg_movprfx
+
# Three operand with "memory" size, aka immediate left shift
@rd_rn_msz_rm ........ ... rm:5 .... imm:2 rn:5 rd:5 &rrri
@@ -379,6 +383,14 @@ ORR_zzz 00000100 01 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
EOR_zzz 00000100 10 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
BIC_zzz 00000100 11 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
+# SVE2 bitwise ternary operations
+EOR3 00000100 00 1 ..... 001 110 ..... ..... @rdn_ra_rm_e0
+BSL 00000100 00 1 ..... 001 111 ..... ..... @rdn_ra_rm_e0
+BCAX 00000100 01 1 ..... 001 110 ..... ..... @rdn_ra_rm_e0
+BSL1N 00000100 01 1 ..... 001 111 ..... ..... @rdn_ra_rm_e0
+BSL2N 00000100 10 1 ..... 001 111 ..... ..... @rdn_ra_rm_e0
+NBSL 00000100 11 1 ..... 001 111 ..... ..... @rdn_ra_rm_e0
+
### SVE Index Generation Group
# SVE index generation (immediate start, immediate increment)
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index 700112e6cb..4af8661cf5 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -6824,3 +6824,53 @@ DO_ST1_ZPZ_D(dd_be, zd, MO_64)
#undef DO_ST1_ZPZ_S
#undef DO_ST1_ZPZ_D
+
+void HELPER(sve2_eor3)(void *vd, void *vn, void *vm, void *vk, uint32_t desc)
+{
+ intptr_t i, opr_sz = simd_oprsz(desc) / 8;
+ uint64_t *d = vd, *n = vn, *m = vm, *k = vk;
+
+ for (i = 0; i < opr_sz; ++i) {
+ d[i] = n[i] ^ m[i] ^ k[i];
+ }
+}
+
+void HELPER(sve2_bcax)(void *vd, void *vn, void *vm, void *vk, uint32_t desc)
+{
+ intptr_t i, opr_sz = simd_oprsz(desc) / 8;
+ uint64_t *d = vd, *n = vn, *m = vm, *k = vk;
+
+ for (i = 0; i < opr_sz; ++i) {
+ d[i] = n[i] ^ (m[i] & ~k[i]);
+ }
+}
+
+void HELPER(sve2_bsl1n)(void *vd, void *vn, void *vm, void *vk, uint32_t desc)
+{
+ intptr_t i, opr_sz = simd_oprsz(desc) / 8;
+ uint64_t *d = vd, *n = vn, *m = vm, *k = vk;
+
+ for (i = 0; i < opr_sz; ++i) {
+ d[i] = (~n[i] & k[i]) | (m[i] & ~k[i]);
+ }
+}
+
+void HELPER(sve2_bsl2n)(void *vd, void *vn, void *vm, void *vk, uint32_t desc)
+{
+ intptr_t i, opr_sz = simd_oprsz(desc) / 8;
+ uint64_t *d = vd, *n = vn, *m = vm, *k = vk;
+
+ for (i = 0; i < opr_sz; ++i) {
+ d[i] = (n[i] & k[i]) | (~m[i] & ~k[i]);
+ }
+}
+
+void HELPER(sve2_nbsl)(void *vd, void *vn, void *vm, void *vk, uint32_t desc)
+{
+ intptr_t i, opr_sz = simd_oprsz(desc) / 8;
+ uint64_t *d = vd, *n = vn, *m = vm, *k = vk;
+
+ for (i = 0; i < opr_sz; ++i) {
+ d[i] = ~((n[i] & k[i]) | (m[i] & ~k[i]));
+ }
+}
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 9e93223e62..a4e1230ef1 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -217,6 +217,17 @@ static void gen_gvec_fn_zzz(DisasContext *s, GVecGen3Fn *gvec_fn,
vec_full_reg_offset(s, rm), vsz, vsz);
}
+/* Invoke a vector expander on four Zregs. */
+static void gen_gvec_fn_zzzz(DisasContext *s, GVecGen4Fn *gvec_fn,
+ int esz, int rd, int rn, int rm, int ra)
+{
+ unsigned vsz = vec_full_reg_size(s);
+ gvec_fn(esz, vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn),
+ vec_full_reg_offset(s, rm),
+ vec_full_reg_offset(s, ra), vsz, vsz);
+}
+
/* Invoke a vector move on two Zregs. */
static bool do_mov_z(DisasContext *s, int rd, int rn)
{
@@ -329,6 +340,208 @@ static bool trans_BIC_zzz(DisasContext *s, arg_rrr_esz *a)
return do_zzz_fn(s, a, tcg_gen_gvec_andc);
}
+static bool do_sve2_zzzz_fn(DisasContext *s, arg_rrrr_esz *a, GVecGen4Fn *fn)
+{
+ if (!dc_isar_feature(aa64_sve2, s)) {
+ return false;
+ }
+ if (sve_access_check(s)) {
+ gen_gvec_fn_zzzz(s, fn, a->esz, a->rd, a->rn, a->rm, a->ra);
+ }
+ return true;
+}
+
+static void gen_eor3_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k)
+{
+ tcg_gen_xor_i64(d, n, m);
+ tcg_gen_xor_i64(d, d, k);
+}
+
+static void gen_eor3_vec(unsigned vece, TCGv_vec d, TCGv_vec n,
+ TCGv_vec m, TCGv_vec k)
+{
+ tcg_gen_xor_vec(vece, d, n, m);
+ tcg_gen_xor_vec(vece, d, d, k);
+}
+
+static void gen_eor3(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
+ uint32_t a, uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen4 op = {
+ .fni8 = gen_eor3_i64,
+ .fniv = gen_eor3_vec,
+ .fno = gen_helper_sve2_eor3,
+ .vece = MO_64,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ };
+ tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op);
+}
+
+static bool trans_EOR3(DisasContext *s, arg_rrrr_esz *a)
+{
+ return do_sve2_zzzz_fn(s, a, gen_eor3);
+}
+
+static void gen_bcax_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k)
+{
+ tcg_gen_andc_i64(d, m, k);
+ tcg_gen_xor_i64(d, d, n);
+}
+
+static void gen_bcax_vec(unsigned vece, TCGv_vec d, TCGv_vec n,
+ TCGv_vec m, TCGv_vec k)
+{
+ tcg_gen_andc_vec(vece, d, m, k);
+ tcg_gen_xor_vec(vece, d, d, n);
+}
+
+static void gen_bcax(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
+ uint32_t a, uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen4 op = {
+ .fni8 = gen_bcax_i64,
+ .fniv = gen_bcax_vec,
+ .fno = gen_helper_sve2_bcax,
+ .vece = MO_64,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ };
+ tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op);
+}
+
+static bool trans_BCAX(DisasContext *s, arg_rrrr_esz *a)
+{
+ return do_sve2_zzzz_fn(s, a, gen_bcax);
+}
+
+static void gen_bsl(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
+ uint32_t a, uint32_t oprsz, uint32_t maxsz)
+{
+ /* BSL differs from the generic bitsel in argument ordering. */
+ tcg_gen_gvec_bitsel(vece, d, a, n, m, oprsz, maxsz);
+}
+
+static bool trans_BSL(DisasContext *s, arg_rrrr_esz *a)
+{
+ return do_sve2_zzzz_fn(s, a, gen_bsl);
+}
+
+static void gen_bsl1n_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k)
+{
+ tcg_gen_andc_i64(n, k, n);
+ tcg_gen_andc_i64(m, m, k);
+ tcg_gen_or_i64(d, n, m);
+}
+
+static void gen_bsl1n_vec(unsigned vece, TCGv_vec d, TCGv_vec n,
+ TCGv_vec m, TCGv_vec k)
+{
+ if (TCG_TARGET_HAS_bitsel_vec) {
+ tcg_gen_not_vec(vece, n, n);
+ tcg_gen_bitsel_vec(vece, d, k, n, m);
+ } else {
+ tcg_gen_andc_vec(vece, n, k, n);
+ tcg_gen_andc_vec(vece, m, m, k);
+ tcg_gen_or_vec(vece, d, n, m);
+ }
+}
+
+static void gen_bsl1n(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
+ uint32_t a, uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen4 op = {
+ .fni8 = gen_bsl1n_i64,
+ .fniv = gen_bsl1n_vec,
+ .fno = gen_helper_sve2_bsl1n,
+ .vece = MO_64,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ };
+ tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op);
+}
+
+static bool trans_BSL1N(DisasContext *s, arg_rrrr_esz *a)
+{
+ return do_sve2_zzzz_fn(s, a, gen_bsl1n);
+}
+
+static void gen_bsl2n_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k)
+{
+ /*
+ * Z[dn] = (n & k) | (~m & ~k)
+ * = | ~(m | k)
+ */
+ tcg_gen_and_i64(n, n, k);
+ if (TCG_TARGET_HAS_orc_i64) {
+ tcg_gen_or_i64(m, m, k);
+ tcg_gen_orc_i64(d, n, m);
+ } else {
+ tcg_gen_nor_i64(m, m, k);
+ tcg_gen_or_i64(d, n, m);
+ }
+}
+
+static void gen_bsl2n_vec(unsigned vece, TCGv_vec d, TCGv_vec n,
+ TCGv_vec m, TCGv_vec k)
+{
+ if (TCG_TARGET_HAS_bitsel_vec) {
+ tcg_gen_not_vec(vece, m, m);
+ tcg_gen_bitsel_vec(vece, d, k, n, m);
+ } else {
+ tcg_gen_and_vec(vece, n, n, k);
+ tcg_gen_or_vec(vece, m, m, k);
+ tcg_gen_orc_vec(vece, d, n, m);
+ }
+}
+
+static void gen_bsl2n(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
+ uint32_t a, uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen4 op = {
+ .fni8 = gen_bsl2n_i64,
+ .fniv = gen_bsl2n_vec,
+ .fno = gen_helper_sve2_bsl2n,
+ .vece = MO_64,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ };
+ tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op);
+}
+
+static bool trans_BSL2N(DisasContext *s, arg_rrrr_esz *a)
+{
+ return do_sve2_zzzz_fn(s, a, gen_bsl2n);
+}
+
+static void gen_nbsl_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k)
+{
+ tcg_gen_and_i64(n, n, k);
+ tcg_gen_andc_i64(m, m, k);
+ tcg_gen_nor_i64(d, n, m);
+}
+
+static void gen_nbsl_vec(unsigned vece, TCGv_vec d, TCGv_vec n,
+ TCGv_vec m, TCGv_vec k)
+{
+ tcg_gen_bitsel_vec(vece, d, k, n, m);
+ tcg_gen_not_vec(vece, d, d);
+}
+
+static void gen_nbsl(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
+ uint32_t a, uint32_t oprsz, uint32_t maxsz)
+{
+ static const GVecGen4 op = {
+ .fni8 = gen_nbsl_i64,
+ .fniv = gen_nbsl_vec,
+ .fno = gen_helper_sve2_nbsl,
+ .vece = MO_64,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ };
+ tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op);
+}
+
+static bool trans_NBSL(DisasContext *s, arg_rrrr_esz *a)
+{
+ return do_sve2_zzzz_fn(s, a, gen_nbsl);
+}
+
/*
*** SVE Integer Arithmetic - Unpredicated Group
*/
--
2.25.1
next prev parent reply other threads:[~2021-03-09 17:38 UTC|newest]
Thread overview: 82+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-09 16:19 [PATCH v4 00/78] target/arm: Implement SVE2 Richard Henderson
2021-03-09 16:19 ` [PATCH v4 01/78] target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2 Richard Henderson
2021-03-09 16:19 ` [PATCH v4 02/78] target/arm: Implement SVE2 Integer Multiply - Unpredicated Richard Henderson
2021-03-09 16:19 ` [PATCH v4 03/78] target/arm: Implement SVE2 integer pairwise add and accumulate long Richard Henderson
2021-03-09 16:19 ` [PATCH v4 04/78] target/arm: Implement SVE2 integer unary operations (predicated) Richard Henderson
2021-03-09 16:19 ` [PATCH v4 05/78] target/arm: Split out saturating/rounding shifts from neon Richard Henderson
2021-03-09 16:19 ` [PATCH v4 06/78] target/arm: Implement SVE2 saturating/rounding bitwise shift left (predicated) Richard Henderson
2021-03-09 16:19 ` [PATCH v4 07/78] target/arm: Implement SVE2 integer halving add/subtract (predicated) Richard Henderson
2021-03-09 16:19 ` [PATCH v4 08/78] target/arm: Implement SVE2 integer pairwise arithmetic Richard Henderson
2021-03-09 16:19 ` [PATCH v4 09/78] target/arm: Implement SVE2 saturating add/subtract (predicated) Richard Henderson
2021-03-09 16:19 ` [PATCH v4 10/78] target/arm: Implement SVE2 integer add/subtract long Richard Henderson
2021-03-09 16:19 ` [PATCH v4 11/78] target/arm: Implement SVE2 integer add/subtract interleaved long Richard Henderson
2021-03-09 16:19 ` [PATCH v4 12/78] target/arm: Implement SVE2 integer add/subtract wide Richard Henderson
2021-03-09 16:19 ` [PATCH v4 13/78] target/arm: Implement SVE2 integer multiply long Richard Henderson
2021-03-09 16:19 ` [PATCH v4 14/78] target/arm: Implement PMULLB and PMULLT Richard Henderson
2021-03-09 16:19 ` [PATCH v4 15/78] target/arm: Implement SVE2 bitwise shift left long Richard Henderson
2021-03-09 16:19 ` [PATCH v4 16/78] target/arm: Implement SVE2 bitwise exclusive-or interleaved Richard Henderson
2021-03-09 16:19 ` [PATCH v4 17/78] target/arm: Implement SVE2 bitwise permute Richard Henderson
2021-03-09 16:19 ` [PATCH v4 18/78] target/arm: Implement SVE2 complex integer add Richard Henderson
2021-03-09 16:19 ` [PATCH v4 19/78] target/arm: Implement SVE2 integer absolute difference and accumulate long Richard Henderson
2021-03-09 16:19 ` [PATCH v4 20/78] target/arm: Implement SVE2 integer add/subtract long with carry Richard Henderson
2021-03-09 16:19 ` [PATCH v4 21/78] target/arm: Implement SVE2 bitwise shift right and accumulate Richard Henderson
2021-03-09 16:19 ` [PATCH v4 22/78] target/arm: Implement SVE2 bitwise shift and insert Richard Henderson
2021-03-09 16:19 ` [PATCH v4 23/78] target/arm: Implement SVE2 integer absolute difference and accumulate Richard Henderson
2021-03-09 16:19 ` [PATCH v4 24/78] target/arm: Implement SVE2 saturating extract narrow Richard Henderson
2021-03-09 16:19 ` [PATCH v4 25/78] target/arm: Implement SVE2 floating-point pairwise Richard Henderson
2021-03-09 16:19 ` [PATCH v4 26/78] target/arm: Implement SVE2 SHRN, RSHRN Richard Henderson
2021-03-09 16:19 ` [PATCH v4 27/78] target/arm: Implement SVE2 SQSHRUN, SQRSHRUN Richard Henderson
2021-03-09 16:19 ` [PATCH v4 28/78] target/arm: Implement SVE2 UQSHRN, UQRSHRN Richard Henderson
2021-03-09 16:19 ` [PATCH v4 29/78] target/arm: Implement SVE2 SQSHRN, SQRSHRN Richard Henderson
2021-03-09 16:19 ` [PATCH v4 30/78] target/arm: Implement SVE2 WHILEGT, WHILEGE, WHILEHI, WHILEHS Richard Henderson
2021-03-09 16:19 ` [PATCH v4 31/78] target/arm: Implement SVE2 WHILERW, WHILEWR Richard Henderson
2021-03-09 16:19 ` Richard Henderson [this message]
2021-03-09 16:19 ` [PATCH v4 33/78] target/arm: Implement SVE2 MATCH, NMATCH Richard Henderson
2021-03-09 16:19 ` [PATCH v4 34/78] target/arm: Implement SVE2 saturating multiply-add long Richard Henderson
2021-03-09 16:19 ` [PATCH v4 35/78] target/arm: Implement SVE2 saturating multiply-add high Richard Henderson
2021-03-09 16:19 ` [PATCH v4 36/78] target/arm: Implement SVE2 integer multiply-add long Richard Henderson
2021-03-09 16:20 ` [PATCH v4 37/78] target/arm: Implement SVE2 complex integer multiply-add Richard Henderson
2021-03-09 16:20 ` [PATCH v4 38/78] target/arm: Implement SVE2 ADDHNB, ADDHNT Richard Henderson
2021-03-09 16:20 ` [PATCH v4 39/78] target/arm: Implement SVE2 RADDHNB, RADDHNT Richard Henderson
2021-03-09 16:20 ` [PATCH v4 40/78] target/arm: Implement SVE2 SUBHNB, SUBHNT Richard Henderson
2021-03-09 16:20 ` [PATCH v4 41/78] target/arm: Implement SVE2 RSUBHNB, RSUBHNT Richard Henderson
2021-03-09 16:20 ` [PATCH v4 42/78] target/arm: Implement SVE2 HISTCNT, HISTSEG Richard Henderson
2021-03-09 16:20 ` [PATCH v4 43/78] target/arm: Implement SVE2 XAR Richard Henderson
2021-03-09 16:20 ` [PATCH v4 44/78] target/arm: Implement SVE2 scatter store insns Richard Henderson
2021-03-09 16:20 ` [PATCH v4 45/78] target/arm: Implement SVE2 gather load insns Richard Henderson
2021-03-09 16:20 ` [PATCH v4 46/78] target/arm: Implement SVE2 FMMLA Richard Henderson
2021-03-09 16:20 ` [PATCH v4 47/78] target/arm: Implement SVE2 SPLICE, EXT Richard Henderson
2021-03-09 16:20 ` [PATCH v4 48/78] target/arm: Pass separate addend to {U, S}DOT helpers Richard Henderson
2021-03-09 16:20 ` [PATCH v4 49/78] target/arm: Pass separate addend to FCMLA helpers Richard Henderson
2021-03-09 16:20 ` [PATCH v4 50/78] target/arm: Split out formats for 2 vectors + 1 index Richard Henderson
2021-03-09 16:20 ` [PATCH v4 51/78] target/arm: Split out formats for 3 " Richard Henderson
2021-03-09 16:20 ` [PATCH v4 52/78] target/arm: Implement SVE2 integer multiply (indexed) Richard Henderson
2021-03-09 16:20 ` [PATCH v4 53/78] target/arm: Implement SVE2 integer multiply-add (indexed) Richard Henderson
2021-03-09 16:20 ` [PATCH v4 54/78] target/arm: Implement SVE2 saturating multiply-add high (indexed) Richard Henderson
2021-03-09 16:20 ` [PATCH v4 55/78] target/arm: Implement SVE2 saturating multiply-add (indexed) Richard Henderson
2021-03-09 16:20 ` [PATCH v4 56/78] target/arm: Implement SVE2 integer multiply long (indexed) Richard Henderson
2021-03-09 16:20 ` [PATCH v4 57/78] target/arm: Implement SVE2 saturating multiply (indexed) Richard Henderson
2021-03-09 16:20 ` [PATCH v4 58/78] target/arm: Implement SVE2 signed saturating doubling multiply high Richard Henderson
2021-03-09 16:20 ` [PATCH v4 59/78] target/arm: Implement SVE2 saturating multiply high (indexed) Richard Henderson
2021-03-09 16:20 ` [PATCH v4 60/78] target/arm: Implement SVE2 multiply-add long (indexed) Richard Henderson
2021-03-09 16:20 ` [PATCH v4 61/78] target/arm: Implement SVE2 complex integer multiply-add (indexed) Richard Henderson
2021-03-09 16:20 ` [PATCH v4 62/78] target/arm: Implement SVE mixed sign dot product (indexed) Richard Henderson
2021-03-09 16:20 ` [PATCH v4 63/78] target/arm: Implement SVE mixed sign dot product Richard Henderson
2021-03-09 16:20 ` [PATCH v4 64/78] target/arm: Implement SVE2 crypto unary operations Richard Henderson
2021-03-09 16:20 ` [PATCH v4 65/78] target/arm: Implement SVE2 crypto destructive binary operations Richard Henderson
2021-03-09 16:20 ` [PATCH v4 66/78] target/arm: Implement SVE2 crypto constructive " Richard Henderson
2021-03-09 16:20 ` [PATCH v4 67/78] target/arm: Implement SVE2 TBL, TBX Richard Henderson
2021-03-09 16:20 ` [PATCH v4 68/78] target/arm: Implement SVE2 FCVTNT Richard Henderson
2021-03-09 16:20 ` [PATCH v4 69/78] target/arm: Implement SVE2 FCVTLT Richard Henderson
2021-03-09 16:20 ` [PATCH v4 70/78] target/arm: Implement SVE2 FCVTXNT, FCVTX Richard Henderson
2021-03-09 16:20 ` [PATCH v4 71/78] target/arm: Implement SVE2 FLOGB Richard Henderson
2021-03-09 16:20 ` [PATCH v4 72/78] target/arm: Share table of sve load functions Richard Henderson
2021-03-09 16:20 ` [PATCH v4 73/78] target/arm: Implement SVE2 LD1RO Richard Henderson
2021-03-09 16:20 ` [PATCH v4 74/78] target/arm: Implement 128-bit ZIP, UZP, TRN Richard Henderson
2021-03-09 16:20 ` [PATCH v4 75/78] target/arm: Implement SVE2 bitwise shift immediate Richard Henderson
2021-03-09 16:20 ` [PATCH v4 76/78] target/arm: Implement SVE2 fp multiply-add long Richard Henderson
2021-03-09 16:20 ` [PATCH v4 77/78] target/arm: Implement SVE2 complex integer dot product Richard Henderson
2021-03-09 16:20 ` [PATCH v4 78/78] target/arm: Enable SVE2 and some extensions Richard Henderson
2021-03-09 19:28 ` [PATCH v4 00/78] target/arm: Implement SVE2 no-reply
2021-03-10 20:17 ` Peter Maydell
2021-03-11 2:33 ` Richard Henderson
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