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* [RFC PATCH v3 cxl-2.0-doe 0/2] Version 3 patch series for PCIe DOE for PCIe and CXL 2.0
@ 2021-03-09 20:33 Chris Browy
  2021-03-09 21:03 ` [RFC PATCH v3 cxl-2.0-doe 1/2] Basic PCIe DOE support Chris Browy
                   ` (2 more replies)
  0 siblings, 3 replies; 6+ messages in thread
From: Chris Browy @ 2021-03-09 20:33 UTC (permalink / raw)
  To: qemu-devel, linux-cxl
  Cc: ben.widawsky, david, vishal.l.verma, jgroves, cbrowy, armbru,
	f4bug, mst, tyshao, hchkuo, Jonathan.Cameron, imammedo,
	dan.j.williams, ira.weiny

Version 3 patch series for PCIe DOE for PCIe and CXL 2.0 implements
all planned functionality.

Based on QEMU version:
https://gitlab.com/bwidawsk/qemu/-/tree/cxl-2.0v4

Summary:
1: PCIe DOE support for Discovery
   - Support multiple DOE instances for each own protocol set 
   - MSI-X and polling supported
   - Update error and interrupt status in DOE Status register
   - Use static array to register callback function for DOE protocols 
   - Deprecate DOE_SUCCESS and DOE_DISCARD
   - Add license headers
2: CXL DOE for CDAT and Compliance Mode.
   - Device supports pre-defined CDAT or user-provided CDAT.
   - Support on reading the iASL aml file via specifying
     "cdat=<filename.aml>" property to -device cxl-type3
	 skips over the ACPI header and writes only CDAT table entries
   - Clean up CXL compliance structures
   - DOE CDAT response returns one CDAT Structure instance based on
     request EntryHandle value.

Example cdat.dat file: (compile with iasl -G cdat.dat)
CDAT file may contain any mix and number of supported CDAT Structure types
----------------------
/* Header */ 
Signature : "CDAT"
Table Length : 00000000
Revision : 01
Checksum : 00
Oem ID : AVERY 
Oem Table ID : 0 
Oem Revision : 1 
Asl Compiler ID : "INTL"
Asl Compiler Revision : 20160527

/* CDAT structures */
Label : DSMAS               // Field        Byte Length
UINT8  : 0                  // Type             1
UINT8  : 00                 // Reserved         1
UINT16 : 0018               // Length           2
UINT8  : 00                 // DSMADHandle      1
UINT8  : 00                 // Flags            1
UINT16 : 0000               // Reserved         2
UINT64 : 0000000000000000   // DPA Base         8
UINT64 : ffffffffffffffff   // DPA Length       8

Label : DSLBIS              // Field          Byte Length
UINT8  : 01                 // Type             1
UINT8  : 00                 // Reserved         1
UINT16 : 0018               // Length           2
UINT8  : 00                 // Handle           1
UINT8  : 00                 // Flags            1
UINT8  : 00                 // Data Type        1
UINT8  : 00                 // Reserved         1
UINT64 : 0000000000000000   // Entry Base Unit  8
UINT16 : 0000               // Entry[0]         2
UINT16 : 0000               // Entry[1]         2
UINT16 : 0000               // Entry[2]         2
UINT16 : 0000               // Reserved         2

Label: DSMSCIS              // Field        Byte Length
UINT8  : 02                 // Type             1
UINT8  : 00                 // Reserved         1
UINT16 : 0014               // Length           2
UINT8  : 00                 // DSMASHandle      1
UINT24 : 000000             // Reserved         3
UINT64 : 0000000000000000   // Memory Side Cache Size    8
UINT32 : 00000000           // Cache Attributes 4 

Label : DSIS                // Field        Byte Length
UINT8  : 03                 // Type             1
UINT8  : 00                 // Reserved         1
UINT16 : 0008               // Length           2
UINT8  : 00                 // Flags            1
UINT8  : 00                 // Handle           1
UINT16 : 0000               // Reserved         2

Label : DSEMTS              // Field        Byte Length
UINT8  : 04                 // Type             1
UINT8  : 00                 // Reserved         1
UINT16 : 0018               // Length           2
UINT8  : 00                 // DSMAS Handle     1
UINT8  : 00                 // EFI Memory Type and Attribute    1
UINT16 : 0000               // Reserved         2
UINT64 : 0000000000000000   // DPA Offset       8
UINT64 : 0000000000000000   // DPA Length       8

Label : SSLBIS              // Field        Byte Length
UINT8  : 05                 // Type             1
UINT8  : 00                 // Reserved         1
UINT16 : 0020               // Length           2
UINT8  : 00                 // Data Type        1
UINT24 : 000000             // Reserved         3
UINT64 : 0000000000000000   // Entry Base Unit  8
Label : SSLBE               // SSLBE[0]
UINT16 : 0000               // Port X ID        2
UINT16 : 0000               // Port Y ID        2
UINT16 : 0000               // Latency or Bandwidth    2
UINT16 : BBBB               // Reserved         2
Label : SSLBE               // SSLBE[1]
UINT16 : 0000               // Port X ID        2
UINT16 : 0000               // Port Y ID        2
UINT16 : 0000               // Latency or Bandwidth    2
UINT16 : BBBC               // Reserved         2
----

References:
1. CXL 2.0 specification
https://www.computeexpresslink.org/download-the-specification
2. PCI-SIG ECN: Data Object Exchange (DOE)
http://www.pcisig.com
3. Coherent Device Attribute Table	CDAT 1.02
https://uefi.org/sites/default/files/resources/Coherent%20Device%20Attribute%20Table_1.02.pdf

---
Chris Browy (2):
  Basic PCIe DOE support
  CXL DOE support for CDAT and Compliance Mode

 MAINTAINERS                               |  49 +--
 hw/cxl/cxl-component-utils.c              |  93 +++++
 hw/mem/cxl_type3.c                        | 184 ++++++++++
 hw/pci/meson.build                        |   1 +
 hw/pci/pci.c                              |  13 +-
 hw/pci/pcie_doe.c                         | 416 ++++++++++++++++++++++
 include/hw/cxl/cxl_cdat.h                 | 127 +++++++
 include/hw/cxl/cxl_compl.h                | 252 +++++++++++++
 include/hw/cxl/cxl_component.h            |  74 ++++
 include/hw/cxl/cxl_device.h               |   4 +
 include/hw/cxl/cxl_pci.h                  |   2 +
 include/hw/pci/pci_ids.h                  |   5 +-
 include/hw/pci/pcie.h                     |   1 +
 include/hw/pci/pcie_doe.h                 | 142 ++++++++
 include/hw/pci/pcie_regs.h                |   4 +
 include/standard-headers/linux/pci_regs.h |   3 +-
 16 files changed, 1327 insertions(+), 43 deletions(-)
 create mode 100644 hw/pci/pcie_doe.c
 create mode 100644 include/hw/cxl/cxl_cdat.h
 create mode 100644 include/hw/cxl/cxl_compl.h
 create mode 100644 include/hw/pci/pcie_doe.h

-- 
2.17.1



^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2021-03-12 11:57 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-03-09 20:33 [RFC PATCH v3 cxl-2.0-doe 0/2] Version 3 patch series for PCIe DOE for PCIe and CXL 2.0 Chris Browy
2021-03-09 21:03 ` [RFC PATCH v3 cxl-2.0-doe 1/2] Basic PCIe DOE support Chris Browy
2021-03-11 19:05   ` Jonathan Cameron
2021-03-09 21:04 ` [RFC PATCH v3 cxl-2.0-doe 2/2] CXL DOE support for CDAT and Compliance Mode Chris Browy
2021-03-12 11:51   ` Jonathan Cameron
2021-03-12 11:54 ` [RFC PATCH v3 cxl-2.0-doe 0/2] Version 3 patch series for PCIe DOE for PCIe and CXL 2.0 Jonathan Cameron

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