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From: Rebecca Cran <rebecca@nuviainc.com>
To: Peter Maydell <peter.maydell@linaro.org>,
	Richard Henderson <richard.henderson@linaro.org>,
	qemu-arm@nongnu.org
Cc: Rebecca Cran <rebecca@nuviainc.com>, qemu-devel@nongnu.org
Subject: [PATCH v5 4/4] target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type
Date: Wed, 17 Mar 2021 17:33:01 -0600	[thread overview]
Message-ID: <20210317233301.4130-5-rebecca@nuviainc.com> (raw)
In-Reply-To: <20210317233301.4130-1-rebecca@nuviainc.com>

Indicate support for FEAT_TLBIOS and FEAT_TLBIRANGE by setting
ID_AA64ISAR0.TLB to 2 for the max AARCH64 CPU type.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/cpu64.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index f0a9e968c9c1..f42803ecaf1d 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -651,6 +651,7 @@ static void aarch64_max_initfn(Object *obj)
         t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
         t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
         t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */
+        t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */
         t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1);
         cpu->isar.id_aa64isar0 = t;
 
-- 
2.26.2



  parent reply	other threads:[~2021-03-17 23:37 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-17 23:32 [PATCH v5 0/4] target/arm: Add support for FEAT_TLBIOS and FEAT_TLBIRANGE Rebecca Cran
2021-03-17 23:32 ` [PATCH v5 1/4] accel/tcg: Add TLB invalidation support for ranges of addresses Rebecca Cran
2021-03-17 23:32 ` [PATCH v5 2/4] target/arm: Add support for FEAT_TLBIRANGE Rebecca Cran
2021-03-17 23:33 ` [PATCH v5 3/4] target/arm: Add support for FEAT_TLBIOS Rebecca Cran
2021-03-17 23:33 ` Rebecca Cran [this message]
2021-03-17 23:42 ` [PATCH v5 0/4] target/arm: Add support for FEAT_TLBIOS and FEAT_TLBIRANGE no-reply

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