From: Igor Mammedov <email@example.com> To: Ben Widawsky <firstname.lastname@example.org> Cc: email@example.com, "Dan Williams" <firstname.lastname@example.org>, "Jonathan Cameron" <Jonathan.Cameron@huawei.com>, "Philippe Mathieu-Daudé" <email@example.com>, "Markus Armbruster" <firstname.lastname@example.org> Subject: Re: CXL 2.0 memory device design Date: Fri, 19 Mar 2021 18:07:05 +0100 [thread overview] Message-ID: <email@example.com> (raw) In-Reply-To: <firstname.lastname@example.org> On Wed, 17 Mar 2021 14:40:58 -0700 Ben Widawsky <email@example.com> wrote: > Phil, Igor, Markus > > TL;DR: What to do about multiple capacities in a single device, and what to do > about interleave? > > I've hacked together a basic CXL 2.0 implementation which exposes a CXL "Type 3" > memory device (CXL 2.0 Chapter 2.3). For what we were trying to do this was > sufficient. There are two main capabilities that CXL spec exposes which I've not > implemented that I'd like to start working toward and am realizing that I what I > have so far might not be able to carry forward to that next milestone. > > Capability 1. A CXL memory device may have both a volatile, and a persistent > capacity. https://bwidawsk.net/HDM_decoders.svg (lower right > side). The current work only supports a single persistent > capacity. > Capability 2. CXL topologies can be interleaved. Basic example: > https://bwidawsk.net/HDM_decoders.svg (lower left side) > > Memory regions are configured via a CXL spec defined HDM decoder. The HDM > decoder which is minimally implemented supports all the functionality mentioned > above (base, size, interleave, type, etc.). A CXL component may have up to 10 > HDMs. > > What I have today: https://bwidawsk.net/QEMU_objects.svg > There's a single memory backend device for each host bridge. That backend is > passed to any CXL component that is part of the hierarchy underneath that > hostbridge. In the case of a Type 3 device memory capacity a subregion is > created for that capacity from within the main backend. The device itself > implements the TYPE_MEMORY_DEVICE interface. This allows me to utilize the > existing memory region code to determine the next free address, and warn on > overlaps. It hopefully will help when I'm ready to support hotplug. As was mentioned on IRC (and maybe on my first attempt to review your patches) Backends are for managing host resource (RAM/file/fd) and its properties. A backend should match a corresponding device model (frontend/emulated hw, i.e. CXL type 3 device), the later should manage how it looks to guest. i.e. in CXL case I'd imagine CLI adding memory look like: -machine cxl=on \ -device cxl-host-bridge,id=foo \ -device cxl-rp,id=rp0,bus="foo" ] -object memory-backend-file,mem-path=somefile,id=mem1 \ -device cxl-mem,backend=mem1[,bus=rp0] if you need to add CXL memory you add pair memory-backend-file + cxl-mem (which practically reflects what would happen on real hw) Sharing a single backend between several CXL devices as a means to implement interleaving, looks to me as abusing backend concept. (that's not how it's done on real hw, memory chips (backend) that belong to a CXL memory card are not shared with other CXL devices). It's probably address space that gets partitioned in small chunks to map them to one or another CXL memory dev. I'd suggest to forget about interleaving for now and implement a simplified variant without it. > Where I've gotten stuck: A Memory Device expects only to have one region of > memory. Trying to add a second breaks pretty much everything. Memory device has very simplistic rules to map devices in address space (we basically open-coded part of 'memory controller' into machine code to do address allocation/mapping, due to PC machine historically not having it implemented properly). > I'm hoping to start the discussion about what the right way to emulate this in > QEMU. Ideally something upstreamable would be great. I think adding a secondary > (or more) capacity to a memory class device is doable, but probably not the > right approach. Also earlier you mentioned that it's guest who programs where CXL memory is mapped, that isn't compatible with simplistic Memory device interface where guest has no say where memory is mapped, in Memory Device case, machine code picks the next free gap in fixed hotplug region and maps it there. So I would not use Memory Device interface in CXL case, but rather implement CXL own interfaces that work as spec declares. Somewhere in hierarchy there will be a device that manages mapping memory into address space (maybe host-bridge or a dedicated memory controller above it). And BIOS will program window for mapping as it's done on real hw. PS: I don't we hardcode in QEMU PCI device initialization, usually it's done by BIOS, probably the same should apply to CXL. In case of secondary volatile region, I'd add the second backend to cxl device. > For context, I've posted v3 previously. Here's a link to v4 which has some minor > changes as well as moving back to using subregions instead of aliases: > https://gitlab.com/bwidawsk/qemu/-/tree/cxl-2.0v4 > > Thanks. > Ben >
next prev parent reply other threads:[~2021-03-19 17:08 UTC|newest] Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-03-17 21:40 Ben Widawsky 2021-03-18 23:41 ` Ben Widawsky 2021-03-19 17:07 ` Igor Mammedov [this message] 2021-03-19 17:47 ` Ben Widawsky 2021-04-06 18:11 ` Igor Mammedov
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