From: "Michael S. Tsirkin" <mst@redhat.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-riscv@nongnu.org, qemu-arm@nongnu.org,
Arnd Bergmann <arnd@arndb.de>,
qemu-devel@nongnu.org, Dmitry Vyukov <dvyukov@google.com>
Subject: Re: [PATCH] hw/pci-host/gpex: Don't fault for unmapped parts of MMIO and PIO windows
Date: Mon, 22 Mar 2021 18:35:08 -0400 [thread overview]
Message-ID: <20210322183320-mutt-send-email-mst@kernel.org> (raw)
In-Reply-To: <20210322201336.9539-1-peter.maydell@linaro.org>
On Mon, Mar 22, 2021 at 08:13:36PM +0000, Peter Maydell wrote:
> Currently the gpex PCI controller implements no special behaviour for
> guest accesses to areas of the PIO and MMIO where it has not mapped
> any PCI devices, which means that for Arm you end up with a CPU
> exception due to a data abort.
>
> Most host OSes expect "like an x86 PC" behaviour, where bad accesses
> like this return -1 for reads and ignore writes. In the interests of
> not being surprising, make host CPU accesses to these windows behave
> as -1/discard where there's no mapped PCI device.
>
> Reported-by: Dmitry Vyukov <dvyukov@google.com>
> Fixes: https://bugs.launchpad.net/qemu/+bug/1918917
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
BTW it looks like launchpad butchered the lore.kernel.org
link so one can't find out what was the guest issue this is
fixing. Want to include a bit more data in the commit log
instead?
> ---
> Not convinced that this is 6.0 material, because IMHO the
> kernel shouldn't be doing this in the first place.
> Do we need to have the property machinery so that old
> virt-5.2 etc retain the previous behaviour ?
> ---
> include/hw/pci-host/gpex.h | 2 ++
> hw/pci-host/gpex.c | 37 +++++++++++++++++++++++++++++++++++--
> 2 files changed, 37 insertions(+), 2 deletions(-)
>
> diff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h
> index d48a020a952..ad876ecd209 100644
> --- a/include/hw/pci-host/gpex.h
> +++ b/include/hw/pci-host/gpex.h
> @@ -49,6 +49,8 @@ struct GPEXHost {
>
> MemoryRegion io_ioport;
> MemoryRegion io_mmio;
> + MemoryRegion io_ioport_window;
> + MemoryRegion io_mmio_window;
> qemu_irq irq[GPEX_NUM_IRQS];
> int irq_num[GPEX_NUM_IRQS];
> };
> diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c
> index 2bdbe7b4561..1f48c89ac6a 100644
> --- a/hw/pci-host/gpex.c
> +++ b/hw/pci-host/gpex.c
> @@ -82,13 +82,46 @@ static void gpex_host_realize(DeviceState *dev, Error **errp)
> PCIExpressHost *pex = PCIE_HOST_BRIDGE(dev);
> int i;
>
> + /*
> + * Note that the MemoryRegions io_mmio and io_ioport that we pass
> + * to pci_register_root_bus() are not the same as the
> + * MemoryRegions io_mmio_window and io_ioport_window that we
> + * expose as SysBus MRs. The difference is in the behaviour of
> + * accesses to addresses where no PCI device has been mapped.
> + *
> + * io_mmio and io_ioport are the underlying PCI view of the PCI
> + * address space, and when a PCI device does a bus master access
> + * to a bad address this is reported back to it as a transaction
> + * failure.
> + *
> + * io_mmio_window and io_ioport_window implement "unmapped
> + * addresses read as -1 and ignore writes"; this is traditional
> + * x86 PC behaviour, which is not mandated by the PCI spec proper
> + * but expected by much PCI-using guest software, including Linux.
> + *
> + * In the interests of not being unnecessarily surprising, we
> + * implement it in the gpex PCI host controller, by providing the
> + * _window MRs, which are containers with io ops that implement
> + * the 'background' behaviour and which hold the real PCI MRs as
> + * subregions.
> + */
> pcie_host_mmcfg_init(pex, PCIE_MMCFG_SIZE_MAX);
> memory_region_init(&s->io_mmio, OBJECT(s), "gpex_mmio", UINT64_MAX);
> memory_region_init(&s->io_ioport, OBJECT(s), "gpex_ioport", 64 * 1024);
>
> + memory_region_init_io(&s->io_mmio_window, OBJECT(s),
> + &unassigned_io_ops, OBJECT(s),
> + "gpex_mmio_window", UINT64_MAX);
> + memory_region_init_io(&s->io_ioport_window, OBJECT(s),
> + &unassigned_io_ops, OBJECT(s),
> + "gpex_ioport_window", 64 * 1024);
> +
> + memory_region_add_subregion(&s->io_mmio_window, 0, &s->io_mmio);
> + memory_region_add_subregion(&s->io_ioport_window, 0, &s->io_ioport);
> +
> sysbus_init_mmio(sbd, &pex->mmio);
> - sysbus_init_mmio(sbd, &s->io_mmio);
> - sysbus_init_mmio(sbd, &s->io_ioport);
> + sysbus_init_mmio(sbd, &s->io_mmio_window);
> + sysbus_init_mmio(sbd, &s->io_ioport_window);
> for (i = 0; i < GPEX_NUM_IRQS; i++) {
> sysbus_init_irq(sbd, &s->irq[i]);
> s->irq_num[i] = -1;
> --
> 2.20.1
next prev parent reply other threads:[~2021-03-22 22:37 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-22 20:13 [PATCH] hw/pci-host/gpex: Don't fault for unmapped parts of MMIO and PIO windows Peter Maydell
2021-03-22 21:34 ` Arnd Bergmann
2021-03-22 22:35 ` Michael S. Tsirkin [this message]
2021-03-23 10:54 ` Peter Maydell
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