From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org
Cc: Frank Chang <frank.chang@sifive.com>,
alistair23@gmail.com, Alistair Francis <alistair.francis@wdc.com>,
Richard Henderson <richard.henderson@linaro.org>,
qemu-devel@nongnu.org
Subject: [PULL 01/16] target/riscv: fix vs() to return proper error code
Date: Mon, 22 Mar 2021 21:57:41 -0400 [thread overview]
Message-ID: <20210323015756.3168650-2-alistair.francis@wdc.com> (raw)
In-Reply-To: <20210323015756.3168650-1-alistair.francis@wdc.com>
From: Frank Chang <frank.chang@sifive.com>
vs() should return -RISCV_EXCP_ILLEGAL_INST instead of -1 if rvv feature
is not enabled.
If -1 is returned, exception will be raised and cs->exception_index will
be set to the negative return value. The exception will then be treated
as an instruction access fault instead of illegal instruction fault.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210223065935.20208-1-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index fd2e6363f3..d2ae73e4a0 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -54,7 +54,7 @@ static int vs(CPURISCVState *env, int csrno)
if (env->misa & RVV) {
return 0;
}
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
static int ctr(CPURISCVState *env, int csrno)
--
2.30.1
next prev parent reply other threads:[~2021-03-23 2:01 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-23 1:57 [PULL 00/16] riscv-to-apply queue Alistair Francis
2021-03-23 1:57 ` Alistair Francis [this message]
2021-03-23 1:57 ` [PULL 02/16] hw/char: disable ibex uart receive if the buffer is full Alistair Francis
2021-03-23 1:57 ` [PULL 03/16] target/riscv: propagate PMP permission to TLB page Alistair Francis
2021-03-23 1:57 ` [PULL 04/16] target/riscv: add log of PMP permission checking Alistair Francis
2021-03-23 1:57 ` [PULL 05/16] target/riscv: flush TLB pages if PMP permission has been changed Alistair Francis
2021-03-23 1:57 ` [PULL 06/16] target/riscv: Adjust privilege level for HLV(X)/HSV instructions Alistair Francis
2021-03-23 1:57 ` [PULL 07/16] target/riscv: Make VSTIP and VSEIP read-only in hip Alistair Francis
2021-03-23 1:57 ` [PULL 08/16] target/riscv: Use background registers also for MSTATUS_MPV Alistair Francis
2021-03-23 1:57 ` [PULL 09/16] hw/riscv: Add fw_cfg support to virt Alistair Francis
2021-03-23 1:57 ` [PULL 10/16] hw/riscv: allow ramfb on virt Alistair Francis
2021-03-23 1:57 ` [PULL 11/16] target/riscv: Fix read and write accesses to vsip and vsie Alistair Francis
2021-03-23 1:57 ` [PULL 12/16] target/riscv: Add proper two-stage lookup exception detection Alistair Francis
2021-03-23 1:57 ` [PULL 13/16] hw/block: m25p80: Support fast read for SST flashes Alistair Francis
2021-03-23 1:57 ` [PULL 14/16] hw/riscv: microchip_pfsoc: Map EMMC/SD mux register Alistair Francis
2021-03-23 1:57 ` [PULL 15/16] docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine Alistair Francis
2021-03-23 1:57 ` [PULL 16/16] target/riscv: Prevent lost illegal instruction exceptions Alistair Francis
2021-03-23 16:48 ` [PULL 00/16] riscv-to-apply queue Peter Maydell
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