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From: Vijai Kumar K <vijai@behindbytes.com>
To: qemu-riscv@nongnu.org, alistair23@gmail.com
Cc: Vijai Kumar K <vijai@behindbytes.com>, qemu-devel@nongnu.org
Subject: [PATCH v3 0/4] Add support for Shakti SoC from IIT-M
Date: Thu,  1 Apr 2021 23:44:53 +0530	[thread overview]
Message-ID: <20210401181457.73039-1-vijai@behindbytes.com> (raw)

Changes in v3:
 - Drop SHAKTI_C_DEBUG register

Changes in v2:
 - Moved CPU addition to a separate patch(P1)
 - Use riscv_setup_rom_resetvec API to setup reset vector
 - Dropped unused DPRINTF and unwanted break statements
 - Fixed uart_can_receive logic
 - Reused sifive_u_cpu_init routine for shakti
 - Error out when an unsupported CPU is specified
 - Addressed formatting changes pointed out in review

Vijai Kumar K (4):
  target/riscv: Add Shakti C class CPU
  riscv: Add initial support for Shakti C machine
  hw/char: Add Shakti UART emulation
  hw/riscv: Connect Shakti UART to Shakti platform

 MAINTAINERS                                 |   9 +
 default-configs/devices/riscv64-softmmu.mak |   1 +
 hw/char/meson.build                         |   1 +
 hw/char/shakti_uart.c                       | 185 ++++++++++++++++++++
 hw/char/trace-events                        |   4 +
 hw/riscv/Kconfig                            |  10 ++
 hw/riscv/meson.build                        |   1 +
 hw/riscv/shakti_c.c                         | 178 +++++++++++++++++++
 include/hw/char/shakti_uart.h               |  74 ++++++++
 include/hw/riscv/shakti_c.h                 |  75 ++++++++
 target/riscv/cpu.c                          |   1 +
 target/riscv/cpu.h                          |   1 +
 12 files changed, 540 insertions(+)
 create mode 100644 hw/char/shakti_uart.c
 create mode 100644 hw/riscv/shakti_c.c
 create mode 100644 include/hw/char/shakti_uart.h
 create mode 100644 include/hw/riscv/shakti_c.h

-- 
2.25.1




             reply	other threads:[~2021-04-01 18:28 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-01 18:14 Vijai Kumar K [this message]
2021-04-01 18:14 ` [PATCH v3 1/4] target/riscv: Add Shakti C class CPU Vijai Kumar K
2021-04-02 13:04   ` Alistair Francis
2021-04-01 18:14 ` [PATCH v3 2/4] riscv: Add initial support for Shakti C machine Vijai Kumar K
2021-04-02 13:03   ` Alistair Francis
2021-04-01 18:14 ` [PATCH v3 3/4] hw/char: Add Shakti UART emulation Vijai Kumar K
2021-04-02 16:12   ` Alistair Francis
2021-04-01 18:14 ` [PATCH v3 4/4] hw/riscv: Connect Shakti UART to Shakti platform Vijai Kumar K
2021-04-02 13:05   ` Alistair Francis
2021-04-02 15:41     ` Vijai Kumar K
2021-04-02 20:05 ` [PATCH v3 0/4] Add support for Shakti SoC from IIT-M Alistair Francis
2021-04-04 11:43   ` Vijai Kumar K

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