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Thu, 1 Apr 2021 23:44:59 +0530 (IST) From: Vijai Kumar K To: qemu-riscv@nongnu.org, alistair23@gmail.com Message-ID: <20210401181457.73039-1-vijai@behindbytes.com> Subject: [PATCH v3 0/4] Add support for Shakti SoC from IIT-M Date: Thu, 1 Apr 2021 23:44:53 +0530 X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMailClient: External Content-Type: text/plain; charset=utf8 Received-SPF: pass client-ip=103.117.158.51; envelope-from=vijai@behindbytes.com; helo=sender-of-o51.zoho.in X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Vijai Kumar K , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Changes in v3: - Drop SHAKTI_C_DEBUG register Changes in v2: - Moved CPU addition to a separate patch(P1) - Use riscv_setup_rom_resetvec API to setup reset vector - Dropped unused DPRINTF and unwanted break statements - Fixed uart_can_receive logic - Reused sifive_u_cpu_init routine for shakti - Error out when an unsupported CPU is specified - Addressed formatting changes pointed out in review Vijai Kumar K (4): target/riscv: Add Shakti C class CPU riscv: Add initial support for Shakti C machine hw/char: Add Shakti UART emulation hw/riscv: Connect Shakti UART to Shakti platform MAINTAINERS | 9 + default-configs/devices/riscv64-softmmu.mak | 1 + hw/char/meson.build | 1 + hw/char/shakti_uart.c | 185 ++++++++++++++++++++ hw/char/trace-events | 4 + hw/riscv/Kconfig | 10 ++ hw/riscv/meson.build | 1 + hw/riscv/shakti_c.c | 178 +++++++++++++++++++ include/hw/char/shakti_uart.h | 74 ++++++++ include/hw/riscv/shakti_c.h | 75 ++++++++ target/riscv/cpu.c | 1 + target/riscv/cpu.h | 1 + 12 files changed, 540 insertions(+) create mode 100644 hw/char/shakti_uart.c create mode 100644 hw/riscv/shakti_c.c create mode 100644 include/hw/char/shakti_uart.h create mode 100644 include/hw/riscv/shakti_c.h --=20 2.25.1