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From: Vijai Kumar K <vijai@behindbytes.com>
To: qemu-riscv@nongnu.org, alistair23@gmail.com
Cc: Vijai Kumar K <vijai@behindbytes.com>, qemu-devel@nongnu.org
Subject: [PATCH v3 1/4] target/riscv: Add Shakti C class CPU
Date: Thu,  1 Apr 2021 23:44:54 +0530	[thread overview]
Message-ID: <20210401181457.73039-2-vijai@behindbytes.com> (raw)
In-Reply-To: <20210401181457.73039-1-vijai@behindbytes.com>

C-Class is a member of the SHAKTI family of processors from IIT-M.

It is an extremely configurable and commercial-grade 5-stage in-order
core supporting the standard RV64GCSUN ISA extensions.

Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
---
 target/riscv/cpu.c | 1 +
 target/riscv/cpu.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 2a990f6253..140094fd52 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -707,6 +707,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
     DEFINE_CPU(TYPE_RISCV_CPU_BASE64,           rv64_base_cpu_init),
     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,       rv64_sifive_e_cpu_init),
     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,       rv64_sifive_u_cpu_init),
+    DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C,         rv64_sifive_u_cpu_init),
 #endif
 };
 
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0edb2826a2..ebbf15fb1c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -38,6 +38,7 @@
 #define TYPE_RISCV_CPU_BASE32           RISCV_CPU_TYPE_NAME("rv32")
 #define TYPE_RISCV_CPU_BASE64           RISCV_CPU_TYPE_NAME("rv64")
 #define TYPE_RISCV_CPU_IBEX             RISCV_CPU_TYPE_NAME("lowrisc-ibex")
+#define TYPE_RISCV_CPU_SHAKTI_C         RISCV_CPU_TYPE_NAME("shakti-c")
 #define TYPE_RISCV_CPU_SIFIVE_E31       RISCV_CPU_TYPE_NAME("sifive-e31")
 #define TYPE_RISCV_CPU_SIFIVE_E34       RISCV_CPU_TYPE_NAME("sifive-e34")
 #define TYPE_RISCV_CPU_SIFIVE_E51       RISCV_CPU_TYPE_NAME("sifive-e51")
-- 
2.25.1




  reply	other threads:[~2021-04-01 18:21 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-01 18:14 [PATCH v3 0/4] Add support for Shakti SoC from IIT-M Vijai Kumar K
2021-04-01 18:14 ` Vijai Kumar K [this message]
2021-04-02 13:04   ` [PATCH v3 1/4] target/riscv: Add Shakti C class CPU Alistair Francis
2021-04-01 18:14 ` [PATCH v3 2/4] riscv: Add initial support for Shakti C machine Vijai Kumar K
2021-04-02 13:03   ` Alistair Francis
2021-04-01 18:14 ` [PATCH v3 3/4] hw/char: Add Shakti UART emulation Vijai Kumar K
2021-04-02 16:12   ` Alistair Francis
2021-04-01 18:14 ` [PATCH v3 4/4] hw/riscv: Connect Shakti UART to Shakti platform Vijai Kumar K
2021-04-02 13:05   ` Alistair Francis
2021-04-02 15:41     ` Vijai Kumar K
2021-04-02 20:05 ` [PATCH v3 0/4] Add support for Shakti SoC from IIT-M Alistair Francis
2021-04-04 11:43   ` Vijai Kumar K

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