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Tue, 06 Apr 2021 09:47:33 -0700 (PDT) Received: from minyard.net ([2001:470:b8f6:1b:f584:ff80:e7e9:e850]) by smtp.gmail.com with ESMTPSA id s83sm3728205oif.43.2021.04.06.09.47.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Apr 2021 09:47:32 -0700 (PDT) Date: Tue, 6 Apr 2021 11:47:31 -0500 From: Corey Minyard To: Patrick Venture Subject: Re: [PATCH 0/2] hw/i2c: Adds pca954x i2c mux switch device Message-ID: <20210406164731.GP7167@minyard.net> References: <20210403222810.3481372-1-venture@google.com> <20210405195834.GF7167@minyard.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=2607:f8b0:4864:20::32a; envelope-from=cminyard@mvista.com; helo=mail-ot1-x32a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: cminyard@mvista.com Cc: Hao Wu , qemu-arm@nongnu.org, Havard Skinnemoen , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, Apr 06, 2021 at 08:41:50AM -0700, Patrick Venture wrote: > On Mon, Apr 5, 2021 at 12:58 PM Corey Minyard wrote: > > > > On Sat, Apr 03, 2021 at 03:28:08PM -0700, Patrick Venture wrote: > > > The i2c mux device pca954x implements two devices: > > > - the pca9546 and pca9548. > > > > > > Patrick Venture (2): > > > hw/i2c/core: add reachable state boolean > > > hw/i2c: add pca954x i2c-mux switch > > > > Looking this over, the code looks good, but I have a few general > > questions: > > > > * Can you register the same slave address on different channels? That's > > something you could do with real hardware and might be required at > > some time. It looks like to me that you can't with this patch set, > > but maybe I'm missing something. > > If I understand the hardware's implementation properly you can have > collisions, and this allows for collisions. I'm not sure what you > mean by having both accessible. For instance, on hardware you can > have a switch with N channels, and on two of the channels there is an > eeprom at 50. But you're unable to talk to both eeproms at the same > time, because the addresses collide -- so how would the hardware know > which you're talking to? My understanding of the behavior in this > collision case is that it just talks to the first one that responds > and can lead to unexpected things. I wasn't talking about the collision case, I was talking about two devices at the same address on two different channels. (In a collision, BTW, both devices will generaly be active and you will get undefined results.) My understanding of what you are doing, and I may be wrong, is that you are adding the devices to the main bus and using an enable/disable to turn the devices on/off depending on which channel is enabled. It does look like you can add multiple devices to the same bus at the same address, so I do think that works. > > There is a board, the quanta-q71l where we had to set the > idle-disconnect because there were two muxes on the same bus, with > conflicting addresses, and so we had to use idle disconnect explicitly > to make the software happy talking to the hardware -- not ideal as > having two devices behind different channels, but ultimately it's the > same idea because the devices are conflicting. > > > > > * Can you add devices to the secondary I2C busses on the mux using the > > standard QEMU device model, or is the function call required? > > I added the function call because I didn't see a clean way to bridge > the issue as well as, the quasi-arbitrary bus numbering used by the > kernel isn't how the hardware truly behaves, and my goal was to > implement closer to the hardware. I thought about adding an I2cBus to > the device and then you'd be able to access it, but wasn't sure of a > nice clean way to plumb that through -- I considered adding/removing > devices from the parent i2c bus instead of the boolean reachable, but > that seemed way less clean - although do-able. The only way I can think of with the method that you are using would be to add a mux and channel to the i2c device, but that's not very natural. The patch I did implements it by plumbing through, like you say. It's a little bit of a hack, but not too bad. > > > > > I ask because I did a pca9540 and pca9541 device, but I've never > > submitted it because I didn't think it would ever be needed. It takes a > > different tack on the problem; it creates the secondary busses as > > standard QEMU I2C busses and bridges them. You can see it at > > > > github.com:cminyard/qemu.git master-i2c-rebase > > > > I'll have to take a look at your approach, but the idea that it > wouldn't be needed sounds bizarre to me as nearly all BMC-based qemu > boards leverage i2c muxes to handle their PCIe slot i2c routing. Yeah, I don't work in that world :). I can see the need there, and nobody has asked up til now. I wish I had pushed it in earlier, then your job would have been a lot easier. -corey > > > If you design can do the things I ask, then it's better. If not, then > > I'm not sure. > > > > -corey > > > > > > > > MAINTAINERS | 6 + > > > hw/i2c/Kconfig | 4 + > > > hw/i2c/core.c | 6 + > > > hw/i2c/i2c_mux_pca954x.c | 182 +++++++++++++++++++++++++++++++ > > > hw/i2c/meson.build | 1 + > > > hw/i2c/trace-events | 5 + > > > include/hw/i2c/i2c.h | 3 + > > > include/hw/i2c/i2c_mux_pca954x.h | 60 ++++++++++ > > > 8 files changed, 267 insertions(+) > > > create mode 100644 hw/i2c/i2c_mux_pca954x.c > > > create mode 100644 include/hw/i2c/i2c_mux_pca954x.h > > > > > > -- > > > 2.31.0.208.g409f899ff0-goog > > >