From: Rebecca Cran <rebecca@nuviainc.com>
To: peter.maydell@linaro.org, richard.henderson@linaro.org
Cc: Rebecca Cran <rebecca@nuviainc.com>,
qemu-devel@nongnu.org, qemu-arm@nongnu.org
Subject: [PATCH v6 0/4] target/arm: Add support for FEAT_TLBIOS and FEAT_TLBIRANGE
Date: Wed, 7 Apr 2021 18:20:35 -0600 [thread overview]
Message-ID: <20210408002039.18027-1-rebecca@nuviainc.com> (raw)
ARMv8.4 adds the mandatory FEAT_TLBIOS and FEAT_TLBIRANGE.
They provides TLBI maintenance instructions that extend to the Outer
Shareable domain and that apply to a range of input addresses.
Changes from v5 to v6:
Fixed wrapping of functions in exec-all.h to avoid exceeding the
80 character limit. checkpatch.pl now passes.
Rebecca Cran (4):
accel/tcg: Add TLB invalidation support for ranges of addresses
target/arm: Add support for FEAT_TLBIRANGE
target/arm: Add support for FEAT_TLBIOS
target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type
accel/tcg/cputlb.c | 130 ++++++-
include/exec/exec-all.h | 46 +++
target/arm/cpu.h | 10 +
target/arm/cpu64.c | 1 +
target/arm/helper.c | 369 ++++++++++++++++++++
5 files changed, 553 insertions(+), 3 deletions(-)
--
2.26.2
next reply other threads:[~2021-04-08 0:26 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-08 0:20 Rebecca Cran [this message]
2021-04-08 0:20 ` [PATCH v6 1/4] accel/tcg: Add TLB invalidation support for ranges of addresses Rebecca Cran
2021-04-08 0:20 ` [PATCH v6 2/4] target/arm: Add support for FEAT_TLBIRANGE Rebecca Cran
2021-04-08 0:20 ` [PATCH v6 3/4] target/arm: Add support for FEAT_TLBIOS Rebecca Cran
2021-04-08 0:20 ` [PATCH v6 4/4] target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type Rebecca Cran
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